335         TII.getNamedOperand(MI, AMDGPU::OpName::dmask)->getImm();  in getOpcodeWidth()
798     DMask = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm();  in setMI()
807     Format = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::format)->getImm();  in setMI()
814     CPol = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::cpol)->getImm();  in setMI()
927   const auto *TFEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::tfe);  in dmasksCanBeCombined()
928   const auto *LWEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::lwe);  in dmasksCanBeCombined()
1145   if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)) {  in getDataRegClass()
1148   if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::vdata)) {  in getDataRegClass()
1151   if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0)) {  in getDataRegClass()
1154   if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) {  in getDataRegClass()
1157   if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::sdata)) {  in getDataRegClass()
1231   auto *Dest0 = TII->getNamedOperand(*CI.I, OpName);  in copyToDestRegs()
1232   auto *Dest1 = TII->getNamedOperand(*Paired.I, OpName);  in copyToDestRegs()
1263   const auto *Src0 = TII->getNamedOperand(*CI.I, OpName);  in copyFromSrcRegs()
1264   const auto *Src1 = TII->getNamedOperand(*Paired.I, OpName);  in copyFromSrcRegs()
1296   const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr);  in mergeRead2Pair()
1372       TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr);  in mergeWrite2Pair()
1374       TII->getNamedOperand(*CI.I, AMDGPU::OpName::data0);  in mergeWrite2Pair()
1376       TII->getNamedOperand(*Paired.I, AMDGPU::OpName::data0);  in mergeWrite2Pair()
1485           .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::sbase));  in mergeSMemLoadImmPair()
1487     New.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset));  in mergeSMemLoadImmPair()
1517     MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr));  in mergeBufferLoadPair()
1525     MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc))  in mergeBufferLoadPair()
1526         .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset))  in mergeBufferLoadPair()
1558     MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr));  in mergeTBufferLoadPair()
1569       MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc))  in mergeTBufferLoadPair()
1570           .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset))  in mergeTBufferLoadPair()
1601     MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr));  in mergeTBufferStorePair()
1612       MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc))  in mergeTBufferStorePair()
1613           .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset))  in mergeTBufferStorePair()
1638   if (auto *SAddr = TII->getNamedOperand(*CI.I, AMDGPU::OpName::saddr))  in mergeFlatLoadPair()
1642     MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr))  in mergeFlatLoadPair()
1666                  .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr))  in mergeFlatStorePair()
1669   if (auto *SAddr = TII->getNamedOperand(*CI.I, AMDGPU::OpName::saddr))  in mergeFlatStorePair()
1898     MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr));  in mergeBufferStorePair()
1907     MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc))  in mergeBufferStorePair()
1908         .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset))  in mergeBufferStorePair()
1997   auto Base = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr);  in updateBaseAndOffset()
2000   TII->getNamedOperand(MI, AMDGPU::OpName::offset)->setImm(NewOffset);  in updateBaseAndOffset()
2051   const auto *Src0 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src0);  in processBaseWithConstOffset()
2052   const auto *Src1 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src1);  in processBaseWithConstOffset()
2063   Src0 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src0);  in processBaseWithConstOffset()
2064   Src1 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src1);  in processBaseWithConstOffset()
2102   if (TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm()) {  in promoteConstantOffsetToImm()
2108   MachineOperand &Base = *TII->getNamedOperand(MI, AMDGPU::OpName::vaddr);  in promoteConstantOffsetToImm()
2167         TII->getNamedOperand(MINext, AMDGPU::OpName::offset)->getImm())  in promoteConstantOffsetToImm()
2171       *TII->getNamedOperand(MINext, AMDGPU::OpName::vaddr);  in promoteConstantOffsetToImm()