Lines Matching refs:v16i16
172 addRegisterClass(MVT::v16i16, &AMDGPU::SGPR_256RegClass); in SITargetLowering()
242 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand); in SITargetLowering()
252 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Expand); in SITargetLowering()
318 MVT::v8i16, MVT::v8f16, MVT::v8bf16, MVT::v16i16, MVT::v16f16, in SITargetLowering()
620 MVT::v4bf16, MVT::v8i16, MVT::v8f16, MVT::v8bf16, MVT::v16i16, in SITargetLowering()
706 setOperationAction(ISD::LOAD, MVT::v16i16, Promote); in SITargetLowering()
707 AddPromotedToType(ISD::LOAD, MVT::v16i16, MVT::v8i32); in SITargetLowering()
713 setOperationAction(ISD::STORE, MVT::v16i16, Promote); in SITargetLowering()
714 AddPromotedToType(ISD::STORE, MVT::v16i16, MVT::v8i32); in SITargetLowering()
764 {MVT::v8i16, MVT::v8f16, MVT::v8bf16, MVT::v16i16, MVT::v16f16, in SITargetLowering()
788 MVT::v16f16, MVT::v16i16, MVT::v32f16, MVT::v32i16}, in SITargetLowering()
791 for (MVT VT : {MVT::v4i16, MVT::v8i16, MVT::v16i16, MVT::v32i16}) in SITargetLowering()
837 MVT::v16i16, MVT::v16f16, MVT::v16bf16, MVT::v32i16, in SITargetLowering()
5677 VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v16i16 || in splitUnaryVectorOp()
5700 VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v16i16 || in splitBinaryVectorOp()
5724 VT == MVT::v8f16 || VT == MVT::v4f32 || VT == MVT::v16i16 || in splitTernaryVectorOp()
7481 if (VT == MVT::v16i16 || VT == MVT::v16f16 || VT == MVT::v16bf16) { in lowerBUILD_VECTOR()