Lines Matching refs:SelectionDAG
35 SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
41 static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
46 static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
49 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
54 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
55 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
56 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
58 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
60 SDValue LowerFROUNDEVEN(SDValue Op, SelectionDAG &DAG) const;
61 SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
62 SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
64 static bool allowApproxFunc(const SelectionDAG &DAG, SDNodeFlags Flags);
65 static bool needsDenormHandlingF32(const SelectionDAG &DAG, SDValue Src,
67 SDValue getIsLtSmallestNormal(SelectionDAG &DAG, SDValue Op,
69 SDValue getIsFinite(SelectionDAG &DAG, SDValue Op, SDNodeFlags Flags) const;
70 std::pair<SDValue, SDValue> getScaledLogInput(SelectionDAG &DAG,
74 SDValue LowerFLOG2(SDValue Op, SelectionDAG &DAG) const;
75 SDValue LowerFLOGCommon(SDValue Op, SelectionDAG &DAG) const;
76 SDValue LowerFLOG10(SDValue Op, SelectionDAG &DAG) const;
77 SDValue LowerFLOGUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
79 SDValue lowerFEXP2(SDValue Op, SelectionDAG &DAG) const;
81 SDValue lowerFEXPUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
83 SDValue lowerFEXP10Unsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
85 SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const;
87 SDValue lowerCTLZResults(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
91 SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
92 SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
93 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
94 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
96 SDValue LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
97 SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
98 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
100 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
139 SelectionDAG &DAG) const;
143 SelectionDAG &DAG) const;
144 SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
145 SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
150 std::pair<EVT, EVT> getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const;
156 SelectionDAG &DAG) const;
159 SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
163 SDValue WidenOrSplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
166 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
168 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
169 SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
170 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
171 SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
172 void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
199 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG,
222 bool isLoadBitCastBeneficial(EVT, EVT, const SelectionDAG &DAG,
253 SelectionDAG &DAG) const override;
256 SelectionDAG &DAG,
266 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
267 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
271 SelectionDAG &DAG) const override;
293 bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override { in isFsqrtCheap()
296 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
299 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
303 SelectionDAG &DAG) const = 0;
311 const SelectionDAG &DAG,
315 const SelectionDAG &DAG,
325 const SelectionDAG &DAG,
337 SDValue CreateLiveInRegister(SelectionDAG &DAG,
342 SDValue CreateLiveInRegister(SelectionDAG &DAG, in CreateLiveInRegister()
349 SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG, in CreateLiveInRegisterRaw()
357 SDValue loadStackInputValue(SelectionDAG &DAG,
362 SDValue storeStackInputValue(SelectionDAG &DAG,
368 SDValue loadInputValue(SelectionDAG &DAG,