234   unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
235   unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
2827   MVT DestVT;  in selectFPToInt()  local
2828   if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())  in selectFPToInt()
2842       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;  in selectFPToInt()
2844       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;  in selectFPToInt()
2847       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;  in selectFPToInt()
2849       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;  in selectFPToInt()
2852       DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);  in selectFPToInt()
2860   MVT DestVT;  in selectIntToFP()  local
2861   if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())  in selectIntToFP()
2864   if (DestVT == MVT::f16 || DestVT == MVT::bf16)  in selectIntToFP()
2867   assert((DestVT == MVT::f32 || DestVT == MVT::f64) &&  in selectIntToFP()
2887       Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri;  in selectIntToFP()
2889       Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri;  in selectIntToFP()
2892       Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri;  in selectIntToFP()
2894       Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;  in selectIntToFP()
2897   Register ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg);  in selectIntToFP()
3044       MVT DestVT = VA.getLocVT();  in processCallArgs()  local
3046       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);  in processCallArgs()
3054       MVT DestVT = VA.getLocVT();  in processCallArgs()  local
3056       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);  in processCallArgs()
3914     MVT DestVT = VA.getValVT();  in selectRet()  local
3916     if (RVVT != DestVT) {  in selectRet()
3924       SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);  in selectRet()
3962   MVT DestVT = DestEVT.getSimpleVT();  in selectTrunc()  local
3967   if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 &&  in selectTrunc()
3968       DestVT != MVT::i1)  in selectTrunc()
3983     switch (DestVT.SimpleTy) {  in selectTrunc()
4014 unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) {  in emiti1Ext()  argument
4015   assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||  in emiti1Ext()
4016           DestVT == MVT::i64) &&  in emiti1Ext()
4019   if (DestVT == MVT::i8 || DestVT == MVT::i16)  in emiti1Ext()
4020     DestVT = MVT::i32;  in emiti1Ext()
4025     if (DestVT == MVT::i64) {  in emiti1Ext()
4038     if (DestVT == MVT::i64) {  in emiti1Ext()
4404 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,  in emitIntExt()  argument
4406   assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?");  in emitIntExt()
4412   if (((DestVT != MVT::i8) && (DestVT != MVT::i16) &&  in emitIntExt()
4413        (DestVT != MVT::i32) && (DestVT != MVT::i64)) ||  in emitIntExt()
4425     return emiti1Ext(SrcReg, DestVT, IsZExt);  in emitIntExt()
4427     if (DestVT == MVT::i64)  in emitIntExt()
4434     if (DestVT == MVT::i64)  in emitIntExt()
4441     assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?");  in emitIntExt()
4448   if (DestVT == MVT::i8 || DestVT == MVT::i16)  in emitIntExt()
4449     DestVT = MVT::i32;  in emitIntExt()
4450   else if (DestVT == MVT::i64) {  in emitIntExt()
4461       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitIntExt()
4618   MVT DestVT = DestEVT.getSimpleVT();  in selectRem()  local
4619   if (DestVT != MVT::i64 && DestVT != MVT::i32)  in selectRem()
4623   bool Is64bit = (DestVT == MVT::i64);  in selectRem()
4644       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in selectRem()