Lines Matching refs:SU

79   SUnit *SU = &SUnits.back();  in newSUnit()  local
84 SU->SchedulingPref = Sched::None; in newSUnit()
86 SU->SchedulingPref = TLI.getSchedulingPreference(N); in newSUnit()
87 return SU; in newSUnit()
91 SUnit *SU = newSUnit(Old->getNode()); in Clone() local
92 SU->OrigNode = Old->OrigNode; in Clone()
93 SU->Latency = Old->Latency; in Clone()
94 SU->isVRegCycle = Old->isVRegCycle; in Clone()
95 SU->isCall = Old->isCall; in Clone()
96 SU->isCallOp = Old->isCallOp; in Clone()
97 SU->isTwoAddress = Old->isTwoAddress; in Clone()
98 SU->isCommutable = Old->isCommutable; in Clone()
99 SU->hasPhysRegDefs = Old->hasPhysRegDefs; in Clone()
100 SU->hasPhysRegClobbers = Old->hasPhysRegClobbers; in Clone()
101 SU->isScheduleHigh = Old->isScheduleHigh; in Clone()
102 SU->isScheduleLow = Old->isScheduleLow; in Clone()
103 SU->SchedulingPref = Old->SchedulingPref; in Clone()
105 return SU; in Clone()
429 SUnit *SU = CallSUnits.pop_back_val(); in BuildSchedUnits() local
430 for (const SDNode *SUNode = SU->getNode(); SUNode; in BuildSchedUnits()
449 for (SUnit &SU : SUnits) { in AddSchedEdges()
450 SDNode *MainNode = SU.getNode(); in AddSchedEdges()
457 SU.isTwoAddress = true; in AddSchedEdges()
462 SU.isCommutable = true; in AddSchedEdges()
466 for (SDNode *N = SU.getNode(); N; N = N->getGluedNode()) { in AddSchedEdges()
469 SU.hasPhysRegClobbers = true; in AddSchedEdges()
474 SU.hasPhysRegDefs = true; in AddSchedEdges()
483 if (OpSU == &SU) in AddSchedEdges()
516 ST.adjustSchedDependency(OpSU, DefIdx, &SU, i, Dep, nullptr); in AddSchedEdges()
519 if (!SU.addPred(Dep) && !Dep.isCtrl() && OpSU->NumRegDefsLeft > 1) { in AddSchedEdges()
583 ScheduleDAGSDNodes::RegDefIter::RegDefIter(const SUnit *SU, in RegDefIter() argument
585 : SchedDAG(SD), Node(SU->getNode()) { in RegDefIter()
608 void ScheduleDAGSDNodes::InitNumRegDefsLeft(SUnit *SU) { in InitNumRegDefsLeft() argument
609 assert(SU->NumRegDefsLeft == 0 && "expect a new node"); in InitNumRegDefsLeft()
610 for (RegDefIter I(SU, this); I.IsValid(); I.Advance()) { in InitNumRegDefsLeft()
611 assert(SU->NumRegDefsLeft < USHRT_MAX && "overflow is ok but unexpected"); in InitNumRegDefsLeft()
612 ++SU->NumRegDefsLeft; in InitNumRegDefsLeft()
616 void ScheduleDAGSDNodes::computeLatency(SUnit *SU) { in computeLatency() argument
617 SDNode *N = SU->getNode(); in computeLatency()
623 SU->Latency = 0; in computeLatency()
629 SU->Latency = 1; in computeLatency()
636 SU->Latency = HighLatencyCycles; in computeLatency()
638 SU->Latency = 1; in computeLatency()
644 SU->Latency = 0; in computeLatency()
645 for (SDNode *N = SU->getNode(); N; N = N->getGluedNode()) in computeLatency()
647 SU->Latency += TII->getInstrLatency(InstrItins, N); in computeLatency()
678 void ScheduleDAGSDNodes::dumpNode(const SUnit &SU) const { in dumpNode()
680 dumpNodeName(SU); in dumpNode()
683 if (!SU.getNode()) { in dumpNode()
688 SU.getNode()->dump(DAG); in dumpNode()
691 for (SDNode *N = SU.getNode()->getGluedNode(); N; N = N->getGluedNode()) in dumpNode()
706 for (const SUnit &SU : SUnits) in dump() local
707 dumpNodeAll(SU); in dump()
715 for (const SUnit *SU : Sequence) { in dumpSchedule() local
716 if (SU) in dumpSchedule()
717 dumpNode(*SU); in dumpSchedule()
811 EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, Register> &VRBaseMap, in EmitPhysRegCopy() argument
813 for (const SDep &Pred : SU->Preds) { in EmitPhysRegCopy()
823 for (const SDep &Succ : SU->Succs) { in EmitPhysRegCopy()
836 Register VRBase = MRI.createVirtualRegister(SU->CopyDstRC); in EmitPhysRegCopy()
837 bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second; in EmitPhysRegCopy()
929 for (SUnit *SU : Sequence) { in EmitSchedule()
930 if (!SU) { in EmitSchedule()
938 if (!SU->getNode()) { in EmitSchedule()
940 EmitPhysRegCopy(SU, CopyVRBaseMap, InsertPos); in EmitSchedule()
945 for (SDNode *N = SU->getNode()->getGluedNode(); N; N = N->getGluedNode()) in EmitSchedule()
949 auto NewInsn = EmitNode(N, SU->OrigNode != SU, SU->isCloned, VRBaseMap); in EmitSchedule()
961 EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned, VRBaseMap); in EmitSchedule()
964 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders, Seen, in EmitSchedule()
967 if (MDNode *MD = DAG->getHeapAllocSite(SU->getNode())) { in EmitSchedule()