2466 	u64 src_offset, dst_offset;  in r600_dma_cs_parse()  local
2489 				dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2490 				dst_offset <<= 8;  in r600_dma_cs_parse()
2495 				dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2496 				dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;  in r600_dma_cs_parse()
2502 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in r600_dma_cs_parse()
2504 					 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in r600_dma_cs_parse()
2528 					dst_offset = radeon_get_ib_value(p, idx+5);  in r600_dma_cs_parse()
2529 					dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;  in r600_dma_cs_parse()
2539 					dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2540 					dst_offset <<= 8;  in r600_dma_cs_parse()
2548 					dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2549 					dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;  in r600_dma_cs_parse()
2559 					dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2560 					dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16;  in r600_dma_cs_parse()
2574 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in r600_dma_cs_parse()
2576 					 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in r600_dma_cs_parse()
2590 			dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2591 			dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;  in r600_dma_cs_parse()
2592 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in r600_dma_cs_parse()
2594 					 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in r600_dma_cs_parse()