1268 	tmp += (((u32)reloc->lobj.gpu_offset) >> 10);  in r100_reloc_pitch_offset()
1271 		if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)  in r100_reloc_pitch_offset()
1273 		if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {  in r100_reloc_pitch_offset()
1319 		ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);  in r100_packet3_load_vbpntr()
1331 		ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);  in r100_packet3_load_vbpntr()
1345 		ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);  in r100_packet3_load_vbpntr()
1697 		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);  in r100_packet0_check()
1710 		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);  in r100_packet0_check()
1724 			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)  in r100_packet0_check()
1726 			if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)  in r100_packet0_check()
1731 			ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);  in r100_packet0_check()
1733 			ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);  in r100_packet0_check()
1751 		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);  in r100_packet0_check()
1769 		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);  in r100_packet0_check()
1787 		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);  in r100_packet0_check()
1805 			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)  in r100_packet0_check()
1807 			if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)  in r100_packet0_check()
1875 		ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);  in r100_packet0_check()
2035 		ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);  in r100_packet3_check()
2049 		ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);  in r100_packet3_check()