2895 	u64 src_offset, dst_offset, dst2_offset;  in evergreen_dma_cs_parse()  local
2920 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2921 				dst_offset <<= 8;  in evergreen_dma_cs_parse()
2926 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2927 				dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2933 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
2935 					 (uintmax_t)dst_offset, radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
2965 						dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2966 						dst_offset <<= 8;  in evergreen_dma_cs_parse()
2976 						if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
2978 								 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
3025 						dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3026 						dst_offset <<= 8;  in evergreen_dma_cs_parse()
3036 						if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
3038 								 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
3061 							dst_offset = radeon_get_ib_value(p, idx+7);  in evergreen_dma_cs_parse()
3062 							dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3072 							dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3073 							dst_offset <<= 8;  in evergreen_dma_cs_parse()
3081 						if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
3083 								 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
3109 						dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3110 						dst_offset <<= 8;  in evergreen_dma_cs_parse()
3120 						if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
3122 								 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
3150 							dst_offset = radeon_get_ib_value(p, idx+7);  in evergreen_dma_cs_parse()
3151 							dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3161 							dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3162 							dst_offset <<= 8;  in evergreen_dma_cs_parse()
3170 						if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
3172 								 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
3189 						dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3190 						dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3196 						if ((dst_offset + count) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
3198 								 (uintmax_t)dst_offset + count, radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
3227 						dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3228 						dst_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3238 						if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
3240 								 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
3264 					dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3265 					dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3271 					if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
3273 							 (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
3290 			dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3291 			dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;  in evergreen_dma_cs_parse()
3292 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
3294 					 (uintmax_t)dst_offset, radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()