2365 	dev_priv->ips.max_delay = fstart;  in ironlake_enable_drps()
2436 	if (*val >= dev_priv->rps.max_delay)  in gen6_rps_limits()
2437 		*val = dev_priv->rps.max_delay;  in gen6_rps_limits()
2438 	limits |= dev_priv->rps.max_delay << 24;  in gen6_rps_limits()
2460 	WARN_ON(val > dev_priv->rps.max_delay);  in gen6_set_rps()
2559 	dev_priv->rps.max_delay = rp_state_cap & 0xff;  in gen6_enable_rps()
2614 		   dev_priv->rps.max_delay << 24 |  in gen6_enable_rps()
2636 			dev_priv->rps.max_delay = pcu_mbox & 0xff;  in gen6_enable_rps()
2703 	for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;  in gen6_update_ring_freq()
2705 		int diff = dev_priv->rps.max_delay - gpu_freq;  in gen6_update_ring_freq()
3240 	if (dev_priv->ips.max_delay > dev_priv->ips.fmax)  in i915_gpu_raise()
3241 		dev_priv->ips.max_delay--;  in i915_gpu_raise()
3268 	if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)  in i915_gpu_lower()
3269 		dev_priv->ips.max_delay++;  in i915_gpu_lower()
3323 	dev_priv->ips.max_delay = dev_priv->ips.fstart;  in i915_gpu_turbo_disable()