4017 	int enable_reg;		/* INT_ENABLE register */  member
4042 	enable = t4_read_reg(adap, ii->enable_reg);  in t4_show_intr_info()
4044 		fatal = ii->fatal & t4_read_reg(adap, ii->enable_reg);  in t4_show_intr_info()
4083 		cause &= t4_read_reg(adap, ii->enable_reg);  in t4_handle_intr()
4088 		fatal &= t4_read_reg(adap, ii->enable_reg);  in t4_handle_intr()
4123 		.enable_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE,  in pcie_intr_handler()
4144 		.enable_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE,  in pcie_intr_handler()
4221 		.enable_reg = A_PCIE_INT_ENABLE,  in pcie_intr_handler()
4255 		.enable_reg = A_TP_INT_ENABLE,  in tp_intr_handler()
4273 		.enable_reg = A_SGE_INT_ENABLE1,  in sge_intr_handler()
4282 		.enable_reg = A_SGE_INT_ENABLE2,  in sge_intr_handler()
4362 		.enable_reg = A_SGE_INT_ENABLE3,  in sge_intr_handler()
4371 		.enable_reg = A_SGE_INT_ENABLE4,  in sge_intr_handler()
4380 		.enable_reg = A_SGE_INT_ENABLE5,  in sge_intr_handler()
4389 		.enable_reg = A_SGE_INT_ENABLE6,  in sge_intr_handler()
4477 		.enable_reg = A_CIM_HOST_INT_ENABLE,  in cim_intr_handler()
4528 		.enable_reg = A_CIM_HOST_UPACC_INT_ENABLE,  in cim_intr_handler()
4537 		.enable_reg = MYPF_REG(A_CIM_PF_HOST_INT_ENABLE),  in cim_intr_handler()
4590 		.enable_reg = A_ULP_RX_INT_ENABLE,  in ulprx_intr_handler()
4599 		.enable_reg = A_ULP_RX_INT_ENABLE_2,  in ulprx_intr_handler()
4629 		.enable_reg = A_ULP_TX_INT_ENABLE,  in ulptx_intr_handler()
4638 		.enable_reg = A_ULP_TX_INT_ENABLE_2,  in ulptx_intr_handler()
4696 		.enable_reg = A_PM_TX_INT_ENABLE,  in pmtx_intr_handler()
4736 		.enable_reg = A_PM_RX_INT_ENABLE,  in pmrx_intr_handler()
4768 		.enable_reg = A_CPL_INTR_ENABLE,  in cplsw_intr_handler()
4826 		.enable_reg = A_LE_DB_INT_ENABLE,  in le_intr_handler()
4856 		.enable_reg = A_MPS_RX_PERR_INT_ENABLE,  in mps_intr_handler()
4876 		.enable_reg = A_MPS_TX_INT_ENABLE,  in mps_intr_handler()
4891 		.enable_reg = A_MPS_TRC_INT_ENABLE,  in mps_intr_handler()
4904 		.enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM,  in mps_intr_handler()
4917 		.enable_reg = A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO,  in mps_intr_handler()
4930 		.enable_reg = A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO,  in mps_intr_handler()
4945 		.enable_reg = A_MPS_CLS_INT_ENABLE,  in mps_intr_handler()
4958 		.enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM1,  in mps_intr_handler()
5012 		ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 0);  in mem_intr_handler()
5018 		ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 1);  in mem_intr_handler()
5025 			ii.enable_reg = A_MC_INT_ENABLE;  in mem_intr_handler()
5029 			ii.enable_reg = A_MC_P_INT_ENABLE;  in mem_intr_handler()
5036 		ii.enable_reg = MC_REG(A_MC_P_INT_ENABLE, 1);  in mem_intr_handler()
5089 		.enable_reg = A_MA_INT_ENABLE,  in ma_intr_handler()
5098 		.enable_reg = A_MA_PARITY_ERROR_ENABLE1,  in ma_intr_handler()
5107 		.enable_reg = A_MA_PARITY_ERROR_ENABLE2,  in ma_intr_handler()
5138 		.enable_reg = A_SMB_INT_ENABLE,  in smb_intr_handler()
5163 		.enable_reg = A_NCSI_INT_ENABLE,  in ncsi_intr_handler()
5192 		ii.enable_reg = PORT_REG(port, A_XGMAC_PORT_INT_EN);  in mac_intr_handler()
5201 		ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_INT_EN);  in mac_intr_handler()
5213 		ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN);  in mac_intr_handler()
5225 		ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN_100G);  in mac_intr_handler()
5246 		.enable_reg = A_PL_PL_INT_ENABLE,  in plpl_intr_handler()
5303 		.enable_reg = A_PL_PERR_ENABLE,  in t4_slow_intr_handler()
5338 		.enable_reg = A_PL_INT_ENABLE,  in t4_slow_intr_handler()
5353 			perr |= t4_read_reg(adap, pl_intr_info.enable_reg);  in t4_slow_intr_handler()