Lines Matching refs:block_id
56 static inline uint64_t CVMX_TRAX_BIST_STATUS(unsigned long block_id) in CVMX_TRAX_BIST_STATUS() argument
59 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_TRAX_BIST_STATUS()
60 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || in CVMX_TRAX_BIST_STATUS()
61 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_TRAX_BIST_STATUS()
62 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || in CVMX_TRAX_BIST_STATUS()
63 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || in CVMX_TRAX_BIST_STATUS()
64 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_TRAX_BIST_STATUS()
65 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_TRAX_BIST_STATUS()
66 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_TRAX_BIST_STATUS()
67 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || in CVMX_TRAX_BIST_STATUS()
68 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_TRAX_BIST_STATUS()
69 cvmx_warn("CVMX_TRAX_BIST_STATUS(%lu) is invalid on this chip\n", block_id); in CVMX_TRAX_BIST_STATUS()
70 return CVMX_ADD_IO_SEG(0x00011800A8000010ull) + ((block_id) & 3) * 0x100000ull; in CVMX_TRAX_BIST_STATUS()
73 #define CVMX_TRAX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000010ull) + ((block_id) & 3) … argument
76 static inline uint64_t CVMX_TRAX_CTL(unsigned long block_id) in CVMX_TRAX_CTL() argument
79 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_TRAX_CTL()
80 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || in CVMX_TRAX_CTL()
81 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_TRAX_CTL()
82 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || in CVMX_TRAX_CTL()
83 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || in CVMX_TRAX_CTL()
84 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_TRAX_CTL()
85 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_TRAX_CTL()
86 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_TRAX_CTL()
87 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || in CVMX_TRAX_CTL()
88 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_TRAX_CTL()
89 cvmx_warn("CVMX_TRAX_CTL(%lu) is invalid on this chip\n", block_id); in CVMX_TRAX_CTL()
90 return CVMX_ADD_IO_SEG(0x00011800A8000000ull) + ((block_id) & 3) * 0x100000ull; in CVMX_TRAX_CTL()
93 #define CVMX_TRAX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000000ull) + ((block_id) & 3) * 0x1000… argument
96 static inline uint64_t CVMX_TRAX_CYCLES_SINCE(unsigned long block_id) in CVMX_TRAX_CYCLES_SINCE() argument
99 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_TRAX_CYCLES_SINCE()
100 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || in CVMX_TRAX_CYCLES_SINCE()
101 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_TRAX_CYCLES_SINCE()
102 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || in CVMX_TRAX_CYCLES_SINCE()
103 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || in CVMX_TRAX_CYCLES_SINCE()
104 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_TRAX_CYCLES_SINCE()
105 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_TRAX_CYCLES_SINCE()
106 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_TRAX_CYCLES_SINCE()
107 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || in CVMX_TRAX_CYCLES_SINCE()
108 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_TRAX_CYCLES_SINCE()
109 cvmx_warn("CVMX_TRAX_CYCLES_SINCE(%lu) is invalid on this chip\n", block_id); in CVMX_TRAX_CYCLES_SINCE()
110 return CVMX_ADD_IO_SEG(0x00011800A8000018ull) + ((block_id) & 3) * 0x100000ull; in CVMX_TRAX_CYCLES_SINCE()
113 #define CVMX_TRAX_CYCLES_SINCE(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000018ull) + ((block_id) & 3)… argument
116 static inline uint64_t CVMX_TRAX_CYCLES_SINCE1(unsigned long block_id) in CVMX_TRAX_CYCLES_SINCE1() argument
119 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_TRAX_CYCLES_SINCE1()
120 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || in CVMX_TRAX_CYCLES_SINCE1()
121 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || in CVMX_TRAX_CYCLES_SINCE1()
122 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_TRAX_CYCLES_SINCE1()
123 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_TRAX_CYCLES_SINCE1()
124 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_TRAX_CYCLES_SINCE1()
125 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || in CVMX_TRAX_CYCLES_SINCE1()
126 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_TRAX_CYCLES_SINCE1()
127 cvmx_warn("CVMX_TRAX_CYCLES_SINCE1(%lu) is invalid on this chip\n", block_id); in CVMX_TRAX_CYCLES_SINCE1()
128 return CVMX_ADD_IO_SEG(0x00011800A8000028ull) + ((block_id) & 3) * 0x100000ull; in CVMX_TRAX_CYCLES_SINCE1()
131 #define CVMX_TRAX_CYCLES_SINCE1(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000028ull) + ((block_id) & 3… argument
134 static inline uint64_t CVMX_TRAX_FILT_ADR_ADR(unsigned long block_id) in CVMX_TRAX_FILT_ADR_ADR() argument
137 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_ADR_ADR()
138 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_ADR_ADR()
139 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_ADR_ADR()
140 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_ADR_ADR()
141 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_ADR_ADR()
142 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_ADR_ADR()
143 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_ADR_ADR()
144 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_ADR_ADR()
145 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || in CVMX_TRAX_FILT_ADR_ADR()
146 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_TRAX_FILT_ADR_ADR()
147 cvmx_warn("CVMX_TRAX_FILT_ADR_ADR(%lu) is invalid on this chip\n", block_id); in CVMX_TRAX_FILT_ADR_ADR()
148 return CVMX_ADD_IO_SEG(0x00011800A8000058ull) + ((block_id) & 3) * 0x100000ull; in CVMX_TRAX_FILT_ADR_ADR()
151 #define CVMX_TRAX_FILT_ADR_ADR(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000058ull) + ((block_id) & 3)… argument
154 static inline uint64_t CVMX_TRAX_FILT_ADR_MSK(unsigned long block_id) in CVMX_TRAX_FILT_ADR_MSK() argument
157 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_ADR_MSK()
158 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_ADR_MSK()
159 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_ADR_MSK()
160 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_ADR_MSK()
161 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_ADR_MSK()
162 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_ADR_MSK()
163 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_ADR_MSK()
164 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_ADR_MSK()
165 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || in CVMX_TRAX_FILT_ADR_MSK()
166 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_TRAX_FILT_ADR_MSK()
167 cvmx_warn("CVMX_TRAX_FILT_ADR_MSK(%lu) is invalid on this chip\n", block_id); in CVMX_TRAX_FILT_ADR_MSK()
168 return CVMX_ADD_IO_SEG(0x00011800A8000060ull) + ((block_id) & 3) * 0x100000ull; in CVMX_TRAX_FILT_ADR_MSK()
171 #define CVMX_TRAX_FILT_ADR_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000060ull) + ((block_id) & 3)… argument
174 static inline uint64_t CVMX_TRAX_FILT_CMD(unsigned long block_id) in CVMX_TRAX_FILT_CMD() argument
177 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_CMD()
178 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_CMD()
179 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_CMD()
180 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_CMD()
181 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_CMD()
182 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_CMD()
183 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_CMD()
184 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_CMD()
185 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || in CVMX_TRAX_FILT_CMD()
186 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_TRAX_FILT_CMD()
187 cvmx_warn("CVMX_TRAX_FILT_CMD(%lu) is invalid on this chip\n", block_id); in CVMX_TRAX_FILT_CMD()
188 return CVMX_ADD_IO_SEG(0x00011800A8000040ull) + ((block_id) & 3) * 0x100000ull; in CVMX_TRAX_FILT_CMD()
191 #define CVMX_TRAX_FILT_CMD(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000040ull) + ((block_id) & 3) * 0… argument
194 static inline uint64_t CVMX_TRAX_FILT_DID(unsigned long block_id) in CVMX_TRAX_FILT_DID() argument
197 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_DID()
198 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_DID()
199 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_DID()
200 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_DID()
201 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_DID()
202 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_DID()
203 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_DID()
204 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_DID()
205 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || in CVMX_TRAX_FILT_DID()
206 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_TRAX_FILT_DID()
207 cvmx_warn("CVMX_TRAX_FILT_DID(%lu) is invalid on this chip\n", block_id); in CVMX_TRAX_FILT_DID()
208 return CVMX_ADD_IO_SEG(0x00011800A8000050ull) + ((block_id) & 3) * 0x100000ull; in CVMX_TRAX_FILT_DID()
211 #define CVMX_TRAX_FILT_DID(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000050ull) + ((block_id) & 3) * 0… argument
214 static inline uint64_t CVMX_TRAX_FILT_SID(unsigned long block_id) in CVMX_TRAX_FILT_SID() argument
217 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_SID()
218 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_SID()
219 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_SID()
220 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_SID()
221 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_SID()
222 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_SID()
223 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_SID()
224 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_TRAX_FILT_SID()
225 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || in CVMX_TRAX_FILT_SID()
226 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_TRAX_FILT_SID()
227 cvmx_warn("CVMX_TRAX_FILT_SID(%lu) is invalid on this chip\n", block_id); in CVMX_TRAX_FILT_SID()
228 return CVMX_ADD_IO_SEG(0x00011800A8000048ull) + ((block_id) & 3) * 0x100000ull; in CVMX_TRAX_FILT_SID()
231 #define CVMX_TRAX_FILT_SID(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000048ull) + ((block_id) & 3) * 0… argument
234 static inline uint64_t CVMX_TRAX_INT_STATUS(unsigned long block_id) in CVMX_TRAX_INT_STATUS() argument
237 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_TRAX_INT_STATUS()
238 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || in CVMX_TRAX_INT_STATUS()
239 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_TRAX_INT_STATUS()
240 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || in CVMX_TRAX_INT_STATUS()
241 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || in CVMX_TRAX_INT_STATUS()
242 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_TRAX_INT_STATUS()
243 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_TRAX_INT_STATUS()
244 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_TRAX_INT_STATUS()
245 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || in CVMX_TRAX_INT_STATUS()
246 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_TRAX_INT_STATUS()
247 cvmx_warn("CVMX_TRAX_INT_STATUS(%lu) is invalid on this chip\n", block_id); in CVMX_TRAX_INT_STATUS()
248 return CVMX_ADD_IO_SEG(0x00011800A8000008ull) + ((block_id) & 3) * 0x100000ull; in CVMX_TRAX_INT_STATUS()
251 #define CVMX_TRAX_INT_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000008ull) + ((block_id) & 3) *… argument
254 static inline uint64_t CVMX_TRAX_READ_DAT(unsigned long block_id) in CVMX_TRAX_READ_DAT() argument
257 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_TRAX_READ_DAT()
258 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || in CVMX_TRAX_READ_DAT()
259 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_TRAX_READ_DAT()
260 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || in CVMX_TRAX_READ_DAT()
261 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || in CVMX_TRAX_READ_DAT()
262 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_TRAX_READ_DAT()
263 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_TRAX_READ_DAT()
264 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_TRAX_READ_DAT()
265 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || in CVMX_TRAX_READ_DAT()
266 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_TRAX_READ_DAT()
267 cvmx_warn("CVMX_TRAX_READ_DAT(%lu) is invalid on this chip\n", block_id); in CVMX_TRAX_READ_DAT()
268 return CVMX_ADD_IO_SEG(0x00011800A8000020ull) + ((block_id) & 3) * 0x100000ull; in CVMX_TRAX_READ_DAT()
271 #define CVMX_TRAX_READ_DAT(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000020ull) + ((block_id) & 3) * 0… argument
274 static inline uint64_t CVMX_TRAX_READ_DAT_HI(unsigned long block_id) in CVMX_TRAX_READ_DAT_HI() argument
277 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_TRAX_READ_DAT_HI()
278 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_TRAX_READ_DAT_HI()
279 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_TRAX_READ_DAT_HI()
280 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || in CVMX_TRAX_READ_DAT_HI()
281 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_TRAX_READ_DAT_HI()
282 cvmx_warn("CVMX_TRAX_READ_DAT_HI(%lu) is invalid on this chip\n", block_id); in CVMX_TRAX_READ_DAT_HI()
283 return CVMX_ADD_IO_SEG(0x00011800A8000030ull) + ((block_id) & 3) * 0x100000ull; in CVMX_TRAX_READ_DAT_HI()
286 #define CVMX_TRAX_READ_DAT_HI(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000030ull) + ((block_id) & 3) … argument
289 static inline uint64_t CVMX_TRAX_TRIG0_ADR_ADR(unsigned long block_id) in CVMX_TRAX_TRIG0_ADR_ADR() argument
292 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_ADR_ADR()
293 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_ADR_ADR()
294 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_ADR_ADR()
295 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_ADR_ADR()
296 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_ADR_ADR()
297 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_ADR_ADR()
298 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_ADR_ADR()
299 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_ADR_ADR()
300 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || in CVMX_TRAX_TRIG0_ADR_ADR()
301 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_TRAX_TRIG0_ADR_ADR()
302 cvmx_warn("CVMX_TRAX_TRIG0_ADR_ADR(%lu) is invalid on this chip\n", block_id); in CVMX_TRAX_TRIG0_ADR_ADR()
303 return CVMX_ADD_IO_SEG(0x00011800A8000098ull) + ((block_id) & 3) * 0x100000ull; in CVMX_TRAX_TRIG0_ADR_ADR()
306 #define CVMX_TRAX_TRIG0_ADR_ADR(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000098ull) + ((block_id) & 3… argument
309 static inline uint64_t CVMX_TRAX_TRIG0_ADR_MSK(unsigned long block_id) in CVMX_TRAX_TRIG0_ADR_MSK() argument
312 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_ADR_MSK()
313 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_ADR_MSK()
314 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_ADR_MSK()
315 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_ADR_MSK()
316 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_ADR_MSK()
317 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_ADR_MSK()
318 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_ADR_MSK()
319 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_ADR_MSK()
320 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || in CVMX_TRAX_TRIG0_ADR_MSK()
321 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_TRAX_TRIG0_ADR_MSK()
322 cvmx_warn("CVMX_TRAX_TRIG0_ADR_MSK(%lu) is invalid on this chip\n", block_id); in CVMX_TRAX_TRIG0_ADR_MSK()
323 return CVMX_ADD_IO_SEG(0x00011800A80000A0ull) + ((block_id) & 3) * 0x100000ull; in CVMX_TRAX_TRIG0_ADR_MSK()
326 #define CVMX_TRAX_TRIG0_ADR_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000A0ull) + ((block_id) & 3… argument
329 static inline uint64_t CVMX_TRAX_TRIG0_CMD(unsigned long block_id) in CVMX_TRAX_TRIG0_CMD() argument
332 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_CMD()
333 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_CMD()
334 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_CMD()
335 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_CMD()
336 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_CMD()
337 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_CMD()
338 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_CMD()
339 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_CMD()
340 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || in CVMX_TRAX_TRIG0_CMD()
341 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_TRAX_TRIG0_CMD()
342 cvmx_warn("CVMX_TRAX_TRIG0_CMD(%lu) is invalid on this chip\n", block_id); in CVMX_TRAX_TRIG0_CMD()
343 return CVMX_ADD_IO_SEG(0x00011800A8000080ull) + ((block_id) & 3) * 0x100000ull; in CVMX_TRAX_TRIG0_CMD()
346 #define CVMX_TRAX_TRIG0_CMD(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000080ull) + ((block_id) & 3) * … argument
349 static inline uint64_t CVMX_TRAX_TRIG0_DID(unsigned long block_id) in CVMX_TRAX_TRIG0_DID() argument
352 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_DID()
353 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_DID()
354 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_DID()
355 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_DID()
356 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_DID()
357 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_DID()
358 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_DID()
359 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_DID()
360 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || in CVMX_TRAX_TRIG0_DID()
361 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_TRAX_TRIG0_DID()
362 cvmx_warn("CVMX_TRAX_TRIG0_DID(%lu) is invalid on this chip\n", block_id); in CVMX_TRAX_TRIG0_DID()
363 return CVMX_ADD_IO_SEG(0x00011800A8000090ull) + ((block_id) & 3) * 0x100000ull; in CVMX_TRAX_TRIG0_DID()
366 #define CVMX_TRAX_TRIG0_DID(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000090ull) + ((block_id) & 3) * … argument
369 static inline uint64_t CVMX_TRAX_TRIG0_SID(unsigned long block_id) in CVMX_TRAX_TRIG0_SID() argument
372 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_SID()
373 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_SID()
374 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_SID()
375 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_SID()
376 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_SID()
377 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_SID()
378 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_SID()
379 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG0_SID()
380 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || in CVMX_TRAX_TRIG0_SID()
381 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_TRAX_TRIG0_SID()
382 cvmx_warn("CVMX_TRAX_TRIG0_SID(%lu) is invalid on this chip\n", block_id); in CVMX_TRAX_TRIG0_SID()
383 return CVMX_ADD_IO_SEG(0x00011800A8000088ull) + ((block_id) & 3) * 0x100000ull; in CVMX_TRAX_TRIG0_SID()
386 #define CVMX_TRAX_TRIG0_SID(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000088ull) + ((block_id) & 3) * … argument
389 static inline uint64_t CVMX_TRAX_TRIG1_ADR_ADR(unsigned long block_id) in CVMX_TRAX_TRIG1_ADR_ADR() argument
392 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_ADR_ADR()
393 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_ADR_ADR()
394 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_ADR_ADR()
395 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_ADR_ADR()
396 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_ADR_ADR()
397 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_ADR_ADR()
398 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_ADR_ADR()
399 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_ADR_ADR()
400 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || in CVMX_TRAX_TRIG1_ADR_ADR()
401 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_TRAX_TRIG1_ADR_ADR()
402 cvmx_warn("CVMX_TRAX_TRIG1_ADR_ADR(%lu) is invalid on this chip\n", block_id); in CVMX_TRAX_TRIG1_ADR_ADR()
403 return CVMX_ADD_IO_SEG(0x00011800A80000D8ull) + ((block_id) & 3) * 0x100000ull; in CVMX_TRAX_TRIG1_ADR_ADR()
406 #define CVMX_TRAX_TRIG1_ADR_ADR(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000D8ull) + ((block_id) & 3… argument
409 static inline uint64_t CVMX_TRAX_TRIG1_ADR_MSK(unsigned long block_id) in CVMX_TRAX_TRIG1_ADR_MSK() argument
412 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_ADR_MSK()
413 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_ADR_MSK()
414 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_ADR_MSK()
415 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_ADR_MSK()
416 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_ADR_MSK()
417 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_ADR_MSK()
418 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_ADR_MSK()
419 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_ADR_MSK()
420 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || in CVMX_TRAX_TRIG1_ADR_MSK()
421 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_TRAX_TRIG1_ADR_MSK()
422 cvmx_warn("CVMX_TRAX_TRIG1_ADR_MSK(%lu) is invalid on this chip\n", block_id); in CVMX_TRAX_TRIG1_ADR_MSK()
423 return CVMX_ADD_IO_SEG(0x00011800A80000E0ull) + ((block_id) & 3) * 0x100000ull; in CVMX_TRAX_TRIG1_ADR_MSK()
426 #define CVMX_TRAX_TRIG1_ADR_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000E0ull) + ((block_id) & 3… argument
429 static inline uint64_t CVMX_TRAX_TRIG1_CMD(unsigned long block_id) in CVMX_TRAX_TRIG1_CMD() argument
432 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_CMD()
433 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_CMD()
434 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_CMD()
435 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_CMD()
436 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_CMD()
437 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_CMD()
438 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_CMD()
439 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_CMD()
440 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || in CVMX_TRAX_TRIG1_CMD()
441 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_TRAX_TRIG1_CMD()
442 cvmx_warn("CVMX_TRAX_TRIG1_CMD(%lu) is invalid on this chip\n", block_id); in CVMX_TRAX_TRIG1_CMD()
443 return CVMX_ADD_IO_SEG(0x00011800A80000C0ull) + ((block_id) & 3) * 0x100000ull; in CVMX_TRAX_TRIG1_CMD()
446 #define CVMX_TRAX_TRIG1_CMD(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000C0ull) + ((block_id) & 3) * … argument
449 static inline uint64_t CVMX_TRAX_TRIG1_DID(unsigned long block_id) in CVMX_TRAX_TRIG1_DID() argument
452 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_DID()
453 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_DID()
454 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_DID()
455 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_DID()
456 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_DID()
457 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_DID()
458 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_DID()
459 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_DID()
460 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || in CVMX_TRAX_TRIG1_DID()
461 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_TRAX_TRIG1_DID()
462 cvmx_warn("CVMX_TRAX_TRIG1_DID(%lu) is invalid on this chip\n", block_id); in CVMX_TRAX_TRIG1_DID()
463 return CVMX_ADD_IO_SEG(0x00011800A80000D0ull) + ((block_id) & 3) * 0x100000ull; in CVMX_TRAX_TRIG1_DID()
466 #define CVMX_TRAX_TRIG1_DID(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000D0ull) + ((block_id) & 3) * … argument
469 static inline uint64_t CVMX_TRAX_TRIG1_SID(unsigned long block_id) in CVMX_TRAX_TRIG1_SID() argument
472 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_SID()
473 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_SID()
474 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_SID()
475 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_SID()
476 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_SID()
477 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_SID()
478 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_SID()
479 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_TRAX_TRIG1_SID()
480 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || in CVMX_TRAX_TRIG1_SID()
481 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_TRAX_TRIG1_SID()
482 cvmx_warn("CVMX_TRAX_TRIG1_SID(%lu) is invalid on this chip\n", block_id); in CVMX_TRAX_TRIG1_SID()
483 return CVMX_ADD_IO_SEG(0x00011800A80000C8ull) + ((block_id) & 3) * 0x100000ull; in CVMX_TRAX_TRIG1_SID()
486 #define CVMX_TRAX_TRIG1_SID(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000C8ull) + ((block_id) & 3) * … argument