Lines Matching refs:val

315 #define	WR4(sc, offs, val)						\  argument
316 bus_write_4(sc->mem_res, offs, val)
319 reg_wait(struct usbphy_softc *sc, uint32_t reg, uint32_t mask, uint32_t val) in reg_wait() argument
324 if ((RD4(sc, reg) & mask) == val) in reg_wait()
334 uint32_t val; in usbphy_utmi_phy_clk() local
337 val = RD4(sc, CTRL_USB_HOSTPC1_DEVLC); in usbphy_utmi_phy_clk()
339 val &= ~USB_HOSTPC1_DEVLC_PHCD; in usbphy_utmi_phy_clk()
341 val |= USB_HOSTPC1_DEVLC_PHCD; in usbphy_utmi_phy_clk()
342 WR4(sc, CTRL_USB_HOSTPC1_DEVLC, val); in usbphy_utmi_phy_clk()
357 uint32_t val; in usbphy_utmi_enable() local
360 val = RD4(sc, IF_USB_SUSP_CTRL); in usbphy_utmi_enable()
361 val |= UTMIP_RESET; in usbphy_utmi_enable()
362 WR4(sc, IF_USB_SUSP_CTRL, val); in usbphy_utmi_enable()
365 val = RD4(sc, UTMIP_TX_CFG0); in usbphy_utmi_enable()
366 val |= UTMIP_FS_PREAMBLE_J; in usbphy_utmi_enable()
367 WR4(sc, UTMIP_TX_CFG0, val); in usbphy_utmi_enable()
369 val = RD4(sc, UTMIP_HSRX_CFG0); in usbphy_utmi_enable()
370 val &= ~UTMIP_IDLE_WAIT(~0); in usbphy_utmi_enable()
371 val &= ~UTMIP_ELASTIC_LIMIT(~0); in usbphy_utmi_enable()
372 val |= UTMIP_IDLE_WAIT(sc->idle_wait_delay); in usbphy_utmi_enable()
373 val |= UTMIP_ELASTIC_LIMIT(sc->elastic_limit); in usbphy_utmi_enable()
374 WR4(sc, UTMIP_HSRX_CFG0, val); in usbphy_utmi_enable()
376 val = RD4(sc, UTMIP_HSRX_CFG1); in usbphy_utmi_enable()
377 val &= ~UTMIP_HS_SYNC_START_DLY(~0); in usbphy_utmi_enable()
378 val |= UTMIP_HS_SYNC_START_DLY(sc->hssync_start_delay); in usbphy_utmi_enable()
379 WR4(sc, UTMIP_HSRX_CFG1, val); in usbphy_utmi_enable()
381 val = RD4(sc, UTMIP_DEBOUNCE_CFG0); in usbphy_utmi_enable()
382 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0); in usbphy_utmi_enable()
383 val |= UTMIP_BIAS_DEBOUNCE_A(0x7530); /* For 12MHz */ in usbphy_utmi_enable()
384 WR4(sc, UTMIP_DEBOUNCE_CFG0, val); in usbphy_utmi_enable()
386 val = RD4(sc, UTMIP_MISC_CFG0); in usbphy_utmi_enable()
387 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE; in usbphy_utmi_enable()
388 WR4(sc, UTMIP_MISC_CFG0, val); in usbphy_utmi_enable()
391 val = RD4(sc,IF_USB_SUSP_CTRL); in usbphy_utmi_enable()
392 val &= ~USB_WAKE_ON_CNNT_EN_DEV; in usbphy_utmi_enable()
393 val &= ~USB_WAKE_ON_DISCON_EN_DEV; in usbphy_utmi_enable()
394 WR4(sc, IF_USB_SUSP_CTRL, val); in usbphy_utmi_enable()
396 val = RD4(sc, UTMIP_BAT_CHRG_CFG0); in usbphy_utmi_enable()
397 val &= ~UTMIP_PD_CHRG; in usbphy_utmi_enable()
398 WR4(sc, UTMIP_BAT_CHRG_CFG0, val); in usbphy_utmi_enable()
400 val = RD4(sc, UTMIP_BAT_CHRG_CFG0); in usbphy_utmi_enable()
401 val |= UTMIP_PD_CHRG; in usbphy_utmi_enable()
402 WR4(sc, UTMIP_BAT_CHRG_CFG0, val); in usbphy_utmi_enable()
420 val = bus_read_4(sc->pads_res, UTMIP_BIAS_CFG0); in usbphy_utmi_enable()
421 val &= ~UTMIP_OTGPD; in usbphy_utmi_enable()
422 val &= ~UTMIP_BIASPD; in usbphy_utmi_enable()
423 val &= ~UTMIP_HSSQUELCH_LEVEL(~0); in usbphy_utmi_enable()
424 val &= ~UTMIP_HSDISCON_LEVEL(~0); in usbphy_utmi_enable()
425 val &= ~UTMIP_HSDISCON_LEVEL_MSB(~0); in usbphy_utmi_enable()
426 val |= UTMIP_HSSQUELCH_LEVEL(sc->hssquelch_level); in usbphy_utmi_enable()
427 val |= UTMIP_HSDISCON_LEVEL(sc->hsdiscon_level); in usbphy_utmi_enable()
428 val |= UTMIP_HSDISCON_LEVEL_MSB(sc->hsdiscon_level); in usbphy_utmi_enable()
429 bus_write_4(sc->pads_res, UTMIP_BIAS_CFG0, val); in usbphy_utmi_enable()
439 val = RD4(sc, UTMIP_XCVR_CFG0); in usbphy_utmi_enable()
440 val &= ~UTMIP_FORCE_PD_POWERDOWN; in usbphy_utmi_enable()
441 val &= ~UTMIP_FORCE_PD2_POWERDOWN ; in usbphy_utmi_enable()
442 val &= ~UTMIP_FORCE_PDZI_POWERDOWN; in usbphy_utmi_enable()
443 val &= ~UTMIP_XCVR_LSBIAS_SEL; in usbphy_utmi_enable()
444 val &= ~UTMIP_XCVR_LSFSLEW(~0); in usbphy_utmi_enable()
445 val &= ~UTMIP_XCVR_LSRSLEW(~0); in usbphy_utmi_enable()
446 val &= ~UTMIP_XCVR_HSSLEW(~0); in usbphy_utmi_enable()
447 val &= ~UTMIP_XCVR_HSSLEW_MSB(~0); in usbphy_utmi_enable()
448 val |= UTMIP_XCVR_LSFSLEW(sc->xcvr_lsfslew); in usbphy_utmi_enable()
449 val |= UTMIP_XCVR_LSRSLEW(sc->xcvr_lsrslew); in usbphy_utmi_enable()
450 val |= UTMIP_XCVR_HSSLEW(sc->xcvr_hsslew); in usbphy_utmi_enable()
451 val |= UTMIP_XCVR_HSSLEW_MSB(sc->xcvr_hsslew); in usbphy_utmi_enable()
453 val &= ~UTMIP_XCVR_SETUP(~0); in usbphy_utmi_enable()
454 val &= ~UTMIP_XCVR_SETUP_MSB(~0); in usbphy_utmi_enable()
455 val |= UTMIP_XCVR_SETUP(sc->xcvr_setup); in usbphy_utmi_enable()
456 val |= UTMIP_XCVR_SETUP_MSB(sc->xcvr_setup); in usbphy_utmi_enable()
458 WR4(sc, UTMIP_XCVR_CFG0, val); in usbphy_utmi_enable()
460 val = RD4(sc, UTMIP_XCVR_CFG1); in usbphy_utmi_enable()
461 val &= ~UTMIP_FORCE_PDDISC_POWERDOWN; in usbphy_utmi_enable()
462 val &= ~UTMIP_FORCE_PDCHRP_POWERDOWN; in usbphy_utmi_enable()
463 val &= ~UTMIP_FORCE_PDDR_POWERDOWN; in usbphy_utmi_enable()
464 val &= ~UTMIP_XCVR_TERM_RANGE_ADJ(~0); in usbphy_utmi_enable()
465 val |= UTMIP_XCVR_TERM_RANGE_ADJ(sc->term_range_adj); in usbphy_utmi_enable()
466 WR4(sc, UTMIP_XCVR_CFG1, val); in usbphy_utmi_enable()
469 val = RD4(sc, UTMIP_BIAS_CFG1); in usbphy_utmi_enable()
470 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0); in usbphy_utmi_enable()
471 val |= UTMIP_BIAS_PDTRK_COUNT(0x5); in usbphy_utmi_enable()
472 WR4(sc, UTMIP_BIAS_CFG1, val); in usbphy_utmi_enable()
474 val = RD4(sc, UTMIP_SPARE_CFG0); in usbphy_utmi_enable()
476 val |= FUSE_SETUP_SEL; in usbphy_utmi_enable()
478 val &= ~FUSE_SETUP_SEL; in usbphy_utmi_enable()
479 WR4(sc, UTMIP_SPARE_CFG0, val); in usbphy_utmi_enable()
481 val = RD4(sc, IF_USB_SUSP_CTRL); in usbphy_utmi_enable()
482 val |= UTMIP_PHY_ENB; in usbphy_utmi_enable()
483 WR4(sc, IF_USB_SUSP_CTRL, val); in usbphy_utmi_enable()
485 val = RD4(sc, IF_USB_SUSP_CTRL); in usbphy_utmi_enable()
486 val &= ~UTMIP_RESET; in usbphy_utmi_enable()
487 WR4(sc, IF_USB_SUSP_CTRL, val); in usbphy_utmi_enable()
491 val = RD4(sc, CTRL_USB_USBMODE); in usbphy_utmi_enable()
492 val &= ~USB_USBMODE_MASK; in usbphy_utmi_enable()
494 val |= USB_USBMODE_HOST; in usbphy_utmi_enable()
496 val |= USB_USBMODE_DEVICE; in usbphy_utmi_enable()
497 WR4(sc, CTRL_USB_USBMODE, val); in usbphy_utmi_enable()
499 val = RD4(sc, CTRL_USB_HOSTPC1_DEVLC); in usbphy_utmi_enable()
500 val &= ~USB_HOSTPC1_DEVLC_PTS(~0); in usbphy_utmi_enable()
501 val |= USB_HOSTPC1_DEVLC_PTS(0); in usbphy_utmi_enable()
502 WR4(sc, CTRL_USB_HOSTPC1_DEVLC, val); in usbphy_utmi_enable()
511 uint32_t val; in usbphy_utmi_disable() local
516 val = RD4(sc, IF_USB_SUSP_CTRL); in usbphy_utmi_disable()
517 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0); in usbphy_utmi_disable()
518 val |= USB_WAKE_ON_CNNT_EN_DEV; in usbphy_utmi_disable()
519 val |= USB_WAKEUP_DEBOUNCE_COUNT(5); in usbphy_utmi_disable()
520 WR4(sc, IF_USB_SUSP_CTRL, val); in usbphy_utmi_disable()
523 val = RD4(sc, IF_USB_SUSP_CTRL); in usbphy_utmi_disable()
524 val |= UTMIP_RESET; in usbphy_utmi_disable()
525 WR4(sc, IF_USB_SUSP_CTRL, val); in usbphy_utmi_disable()
527 val = RD4(sc, UTMIP_BAT_CHRG_CFG0); in usbphy_utmi_disable()
528 val |= UTMIP_PD_CHRG; in usbphy_utmi_disable()
529 WR4(sc, UTMIP_BAT_CHRG_CFG0, val); in usbphy_utmi_disable()
531 val = RD4(sc, UTMIP_XCVR_CFG0); in usbphy_utmi_disable()
532 val |= UTMIP_FORCE_PD_POWERDOWN; in usbphy_utmi_disable()
533 val |= UTMIP_FORCE_PD2_POWERDOWN; in usbphy_utmi_disable()
534 val |= UTMIP_FORCE_PDZI_POWERDOWN; in usbphy_utmi_disable()
535 WR4(sc, UTMIP_XCVR_CFG0, val); in usbphy_utmi_disable()
537 val = RD4(sc, UTMIP_XCVR_CFG1); in usbphy_utmi_disable()
538 val |= UTMIP_FORCE_PDDISC_POWERDOWN; in usbphy_utmi_disable()
539 val |= UTMIP_FORCE_PDCHRP_POWERDOWN; in usbphy_utmi_disable()
540 val |= UTMIP_FORCE_PDDR_POWERDOWN; in usbphy_utmi_disable()
541 WR4(sc, UTMIP_XCVR_CFG1, val); in usbphy_utmi_disable()
551 val =bus_read_4(sc->pads_res, UTMIP_BIAS_CFG0); in usbphy_utmi_disable()
552 val |= UTMIP_OTGPD; in usbphy_utmi_disable()
553 val |= UTMIP_BIASPD; in usbphy_utmi_disable()
554 bus_write_4(sc->pads_res, UTMIP_BIAS_CFG0, val); in usbphy_utmi_disable()