Lines Matching refs:RegisterClassHierarchy
65 const CodeGenRegBank &RegisterClassHierarchy) const { in getExplicitlySpecifiedRegisterClasses()
68 RCs.push_back(RegisterClassHierarchy.getRegClass(RCDef)); in getExplicitlySpecifiedRegisterClasses()
170 const CodeGenRegBank &RegisterClassHierarchy, in visitRegisterBankClasses() argument
183 for (const auto &PossibleSubclass : RegisterClassHierarchy.getRegClasses()) { in visitRegisterBankClasses()
189 visitRegisterBankClasses(RegisterClassHierarchy, &PossibleSubclass, in visitRegisterBankClasses()
199 for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) { in visitRegisterBankClasses()
200 BitVector BV(RegisterClassHierarchy.getRegClasses().size()); in visitRegisterBankClasses()
215 const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank(); in emitBaseClassImplementation() local
221 (RegisterClassHierarchy.getRegClasses().size() + 31) / 32); in emitBaseClassImplementation()
253 << RegisterClassHierarchy.getRegClasses().size() << ");\n"; in emitBaseClassImplementation()
280 const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank(); in run() local
289 Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) { in run()
291 RegisterClassHierarchy, RC, "explicit", in run()
305 for (const auto &Class : RegisterClassHierarchy.getRegClasses()) { in run()