Lines Matching refs:RegMO
4348 MachineOperand *&RegMO) const { in isDefMIElgibleForForwarding()
4355 RegMO = &DefMI.getOperand(1); in isDefMIElgibleForForwarding()
4359 if (!RegMO->isReg()) in isDefMIElgibleForForwarding()
4369 const MachineOperand &RegMO, const MachineInstr &DefMI, in isRegElgibleForForwarding() argument
4382 Register Reg = RegMO.getReg(); in isRegElgibleForForwarding()
4741 MachineOperand *RegMO = nullptr; in transformToNewImmFormFedByAdd() local
4742 if (!isDefMIElgibleForForwarding(DefMI, III, ImmMO, RegMO)) in transformToNewImmFormFedByAdd()
4744 assert(ImmMO && RegMO && "Imm and Reg operand must have been set"); in transformToNewImmFormFedByAdd()
4765 MI.getOperand(III.OpNoForForwarding).setReg(RegMO->getReg()); in transformToNewImmFormFedByAdd()
4766 if (RegMO->isKill()) { in transformToNewImmFormFedByAdd()
4770 RegMO->setIsKill(false); in transformToNewImmFormFedByAdd()
4789 if (RegMO->isKill() || IsKilledFor(RegMO->getReg())) in transformToNewImmFormFedByAdd()
4790 fixupIsDeadOrKill(&DefMI, &MI, RegMO->getReg()); in transformToNewImmFormFedByAdd()
4820 MachineOperand *RegMO = nullptr; in transformToImmFormFedByAdd() local
4821 if (!isDefMIElgibleForForwarding(DefMI, III, ImmMO, RegMO)) in transformToImmFormFedByAdd()
4823 assert(ImmMO && RegMO && "Imm and Reg operand must have been set"); in transformToImmFormFedByAdd()
4833 if (!isRegElgibleForForwarding(*RegMO, DefMI, MI, KillDefMI, in transformToImmFormFedByAdd()
4853 MI.getOperand(III.OpNoForForwarding).ChangeToRegister(RegMO->getReg(), in transformToImmFormFedByAdd()
4855 RegMO->isKill()); in transformToImmFormFedByAdd()
4902 if (IsFwdFeederRegKilled || RegMO->isKill()) in transformToImmFormFedByAdd()
4903 fixupIsDeadOrKill(&DefMI, &MI, RegMO->getReg()); in transformToImmFormFedByAdd()