Lines Matching refs:BankedReg
112 class BankedReg<string name, bits<8> enc>
123 def : BankedReg<"r8_usr", 0x00>;
124 def : BankedReg<"r9_usr", 0x01>;
125 def : BankedReg<"r10_usr", 0x02>;
126 def : BankedReg<"r11_usr", 0x03>;
127 def : BankedReg<"r12_usr", 0x04>;
128 def : BankedReg<"sp_usr", 0x05>;
129 def : BankedReg<"lr_usr", 0x06>;
130 def : BankedReg<"r8_fiq", 0x08>;
131 def : BankedReg<"r9_fiq", 0x09>;
132 def : BankedReg<"r10_fiq", 0x0a>;
133 def : BankedReg<"r11_fiq", 0x0b>;
134 def : BankedReg<"r12_fiq", 0x0c>;
135 def : BankedReg<"sp_fiq", 0x0d>;
136 def : BankedReg<"lr_fiq", 0x0e>;
137 def : BankedReg<"lr_irq", 0x10>;
138 def : BankedReg<"sp_irq", 0x11>;
139 def : BankedReg<"lr_svc", 0x12>;
140 def : BankedReg<"sp_svc", 0x13>;
141 def : BankedReg<"lr_abt", 0x14>;
142 def : BankedReg<"sp_abt", 0x15>;
143 def : BankedReg<"lr_und", 0x16>;
144 def : BankedReg<"sp_und", 0x17>;
145 def : BankedReg<"lr_mon", 0x1c>;
146 def : BankedReg<"sp_mon", 0x1d>;
147 def : BankedReg<"elr_hyp", 0x1e>;
148 def : BankedReg<"sp_hyp", 0x1f>;
149 def : BankedReg<"spsr_fiq", 0x2e>;
150 def : BankedReg<"spsr_irq", 0x30>;
151 def : BankedReg<"spsr_svc", 0x32>;
152 def : BankedReg<"spsr_abt", 0x34>;
153 def : BankedReg<"spsr_und", 0x36>;
154 def : BankedReg<"spsr_mon", 0x3c>;
155 def : BankedReg<"spsr_hyp", 0x3e>;