Lines Matching refs:ARM
209 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead()) in definesCPSR()
220 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD; in getMemoryOpOffset()
224 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 || in getMemoryOpOffset()
225 Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 || in getMemoryOpOffset()
226 Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 || in getMemoryOpOffset()
227 Opcode == ARM::LDRi12 || Opcode == ARM::STRi12) in getMemoryOpOffset()
231 if (Opcode == ARM::tLDRi || Opcode == ARM::tSTRi || in getMemoryOpOffset()
232 Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) in getMemoryOpOffset()
257 case ARM::LDRi12: in getLoadStoreMultipleOpcode()
261 case ARM_AM::ia: return ARM::LDMIA; in getLoadStoreMultipleOpcode()
262 case ARM_AM::da: return ARM::LDMDA; in getLoadStoreMultipleOpcode()
263 case ARM_AM::db: return ARM::LDMDB; in getLoadStoreMultipleOpcode()
264 case ARM_AM::ib: return ARM::LDMIB; in getLoadStoreMultipleOpcode()
266 case ARM::STRi12: in getLoadStoreMultipleOpcode()
270 case ARM_AM::ia: return ARM::STMIA; in getLoadStoreMultipleOpcode()
271 case ARM_AM::da: return ARM::STMDA; in getLoadStoreMultipleOpcode()
272 case ARM_AM::db: return ARM::STMDB; in getLoadStoreMultipleOpcode()
273 case ARM_AM::ib: return ARM::STMIB; in getLoadStoreMultipleOpcode()
275 case ARM::tLDRi: in getLoadStoreMultipleOpcode()
276 case ARM::tLDRspi: in getLoadStoreMultipleOpcode()
282 case ARM_AM::ia: return ARM::tLDMIA; in getLoadStoreMultipleOpcode()
284 case ARM::tSTRi: in getLoadStoreMultipleOpcode()
285 case ARM::tSTRspi: in getLoadStoreMultipleOpcode()
290 case ARM_AM::ia: return ARM::tSTMIA_UPD; in getLoadStoreMultipleOpcode()
292 case ARM::t2LDRi8: in getLoadStoreMultipleOpcode()
293 case ARM::t2LDRi12: in getLoadStoreMultipleOpcode()
297 case ARM_AM::ia: return ARM::t2LDMIA; in getLoadStoreMultipleOpcode()
298 case ARM_AM::db: return ARM::t2LDMDB; in getLoadStoreMultipleOpcode()
300 case ARM::t2STRi8: in getLoadStoreMultipleOpcode()
301 case ARM::t2STRi12: in getLoadStoreMultipleOpcode()
305 case ARM_AM::ia: return ARM::t2STMIA; in getLoadStoreMultipleOpcode()
306 case ARM_AM::db: return ARM::t2STMDB; in getLoadStoreMultipleOpcode()
308 case ARM::VLDRS: in getLoadStoreMultipleOpcode()
312 case ARM_AM::ia: return ARM::VLDMSIA; in getLoadStoreMultipleOpcode()
315 case ARM::VSTRS: in getLoadStoreMultipleOpcode()
319 case ARM_AM::ia: return ARM::VSTMSIA; in getLoadStoreMultipleOpcode()
322 case ARM::VLDRD: in getLoadStoreMultipleOpcode()
326 case ARM_AM::ia: return ARM::VLDMDIA; in getLoadStoreMultipleOpcode()
329 case ARM::VSTRD: in getLoadStoreMultipleOpcode()
333 case ARM_AM::ia: return ARM::VSTMDIA; in getLoadStoreMultipleOpcode()
342 case ARM::LDMIA_RET: in getLoadStoreMultipleSubMode()
343 case ARM::LDMIA: in getLoadStoreMultipleSubMode()
344 case ARM::LDMIA_UPD: in getLoadStoreMultipleSubMode()
345 case ARM::STMIA: in getLoadStoreMultipleSubMode()
346 case ARM::STMIA_UPD: in getLoadStoreMultipleSubMode()
347 case ARM::tLDMIA: in getLoadStoreMultipleSubMode()
348 case ARM::tLDMIA_UPD: in getLoadStoreMultipleSubMode()
349 case ARM::tSTMIA_UPD: in getLoadStoreMultipleSubMode()
350 case ARM::t2LDMIA_RET: in getLoadStoreMultipleSubMode()
351 case ARM::t2LDMIA: in getLoadStoreMultipleSubMode()
352 case ARM::t2LDMIA_UPD: in getLoadStoreMultipleSubMode()
353 case ARM::t2STMIA: in getLoadStoreMultipleSubMode()
354 case ARM::t2STMIA_UPD: in getLoadStoreMultipleSubMode()
355 case ARM::VLDMSIA: in getLoadStoreMultipleSubMode()
356 case ARM::VLDMSIA_UPD: in getLoadStoreMultipleSubMode()
357 case ARM::VSTMSIA: in getLoadStoreMultipleSubMode()
358 case ARM::VSTMSIA_UPD: in getLoadStoreMultipleSubMode()
359 case ARM::VLDMDIA: in getLoadStoreMultipleSubMode()
360 case ARM::VLDMDIA_UPD: in getLoadStoreMultipleSubMode()
361 case ARM::VSTMDIA: in getLoadStoreMultipleSubMode()
362 case ARM::VSTMDIA_UPD: in getLoadStoreMultipleSubMode()
365 case ARM::LDMDA: in getLoadStoreMultipleSubMode()
366 case ARM::LDMDA_UPD: in getLoadStoreMultipleSubMode()
367 case ARM::STMDA: in getLoadStoreMultipleSubMode()
368 case ARM::STMDA_UPD: in getLoadStoreMultipleSubMode()
371 case ARM::LDMDB: in getLoadStoreMultipleSubMode()
372 case ARM::LDMDB_UPD: in getLoadStoreMultipleSubMode()
373 case ARM::STMDB: in getLoadStoreMultipleSubMode()
374 case ARM::STMDB_UPD: in getLoadStoreMultipleSubMode()
375 case ARM::t2LDMDB: in getLoadStoreMultipleSubMode()
376 case ARM::t2LDMDB_UPD: in getLoadStoreMultipleSubMode()
377 case ARM::t2STMDB: in getLoadStoreMultipleSubMode()
378 case ARM::t2STMDB_UPD: in getLoadStoreMultipleSubMode()
379 case ARM::VLDMSDB_UPD: in getLoadStoreMultipleSubMode()
380 case ARM::VSTMSDB_UPD: in getLoadStoreMultipleSubMode()
381 case ARM::VLDMDDB_UPD: in getLoadStoreMultipleSubMode()
382 case ARM::VSTMDDB_UPD: in getLoadStoreMultipleSubMode()
385 case ARM::LDMIB: in getLoadStoreMultipleSubMode()
386 case ARM::LDMIB_UPD: in getLoadStoreMultipleSubMode()
387 case ARM::STMIB: in getLoadStoreMultipleSubMode()
388 case ARM::STMIB_UPD: in getLoadStoreMultipleSubMode()
394 return Opc == ARM::tLDRi || Opc == ARM::tLDRspi; in isT1i32Load()
398 return Opc == ARM::t2LDRi12 || Opc == ARM::t2LDRi8; in isT2i32Load()
402 return Opc == ARM::LDRi12 || isT1i32Load(Opc) || isT2i32Load(Opc) ; in isi32Load()
406 return Opc == ARM::tSTRi || Opc == ARM::tSTRspi; in isT1i32Store()
410 return Opc == ARM::t2STRi12 || Opc == ARM::t2STRi8; in isT2i32Store()
414 return Opc == ARM::STRi12 || isT1i32Store(Opc) || isT2i32Store(Opc); in isi32Store()
418 return isi32Load(Opc) || Opc == ARM::VLDRS || Opc == ARM::VLDRD; in isLoadSingle()
424 case ARM::tLDRi: in getImmScale()
425 case ARM::tSTRi: in getImmScale()
426 case ARM::tLDRspi: in getImmScale()
427 case ARM::tSTRspi: in getImmScale()
429 case ARM::tLDRHi: in getImmScale()
430 case ARM::tSTRHi: in getImmScale()
432 case ARM::tLDRBi: in getImmScale()
433 case ARM::tSTRBi: in getImmScale()
441 case ARM::LDRi12: in getLSMultipleTransferSize()
442 case ARM::STRi12: in getLSMultipleTransferSize()
443 case ARM::tLDRi: in getLSMultipleTransferSize()
444 case ARM::tSTRi: in getLSMultipleTransferSize()
445 case ARM::tLDRspi: in getLSMultipleTransferSize()
446 case ARM::tSTRspi: in getLSMultipleTransferSize()
447 case ARM::t2LDRi8: in getLSMultipleTransferSize()
448 case ARM::t2LDRi12: in getLSMultipleTransferSize()
449 case ARM::t2STRi8: in getLSMultipleTransferSize()
450 case ARM::t2STRi12: in getLSMultipleTransferSize()
451 case ARM::VLDRS: in getLSMultipleTransferSize()
452 case ARM::VSTRS: in getLSMultipleTransferSize()
454 case ARM::VLDRD: in getLSMultipleTransferSize()
455 case ARM::VSTRD: in getLSMultipleTransferSize()
457 case ARM::LDMIA: in getLSMultipleTransferSize()
458 case ARM::LDMDA: in getLSMultipleTransferSize()
459 case ARM::LDMDB: in getLSMultipleTransferSize()
460 case ARM::LDMIB: in getLSMultipleTransferSize()
461 case ARM::STMIA: in getLSMultipleTransferSize()
462 case ARM::STMDA: in getLSMultipleTransferSize()
463 case ARM::STMDB: in getLSMultipleTransferSize()
464 case ARM::STMIB: in getLSMultipleTransferSize()
465 case ARM::tLDMIA: in getLSMultipleTransferSize()
466 case ARM::tLDMIA_UPD: in getLSMultipleTransferSize()
467 case ARM::tSTMIA_UPD: in getLSMultipleTransferSize()
468 case ARM::t2LDMIA: in getLSMultipleTransferSize()
469 case ARM::t2LDMDB: in getLSMultipleTransferSize()
470 case ARM::t2STMIA: in getLSMultipleTransferSize()
471 case ARM::t2STMDB: in getLSMultipleTransferSize()
472 case ARM::VLDMSIA: in getLSMultipleTransferSize()
473 case ARM::VSTMSIA: in getLSMultipleTransferSize()
475 case ARM::VLDMDIA: in getLSMultipleTransferSize()
476 case ARM::VSTMDIA: in getLSMultipleTransferSize()
499 Opc == ARM::tLDRi || Opc == ARM::tLDRHi || Opc == ARM::tLDRBi; in UpdateBaseRegUses()
501 Opc == ARM::tSTRi || Opc == ARM::tSTRHi || Opc == ARM::tSTRBi; in UpdateBaseRegUses()
520 } else if ((Opc == ARM::tSUBi8 || Opc == ARM::tADDi8) && in UpdateBaseRegUses()
527 Offset = (Opc == ARM::tSUBi8) ? in UpdateBaseRegUses()
552 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base) in UpdateBaseRegUses()
573 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base) in UpdateBaseRegUses()
637 (MBB.computeRegisterLiveness(TRI, ARM::CPSR, InsertBefore, 20) == in CreateLoadStoreMulti()
646 assert(Base != ARM::SP && "Thumb1 does not allow SP in register list"); in CreateLoadStoreMulti()
647 if (Opcode == ARM::tLDRi) in CreateLoadStoreMulti()
649 else if (Opcode == ARM::tSTRi) in CreateLoadStoreMulti()
665 } else if (Offset != 0 || Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) { in CreateLoadStoreMulti()
696 NewBase = findFreeReg(isThumb1 ? ARM::tGPRRegClass : ARM::GPRRegClass); in CreateLoadStoreMulti()
701 int BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2ADDspImm in CreateLoadStoreMulti()
702 : ARM::t2ADDri) in CreateLoadStoreMulti()
703 : (isThumb1 && Base == ARM::SP) in CreateLoadStoreMulti()
704 ? ARM::tADDrSPi in CreateLoadStoreMulti()
706 ? ARM::tADDi3 in CreateLoadStoreMulti()
707 : isThumb1 ? ARM::tADDi8 : ARM::ADDri; in CreateLoadStoreMulti()
713 BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2SUBspImm in CreateLoadStoreMulti()
714 : ARM::t2SUBri) in CreateLoadStoreMulti()
715 : (isThumb1 && Offset < 8 && Base != ARM::SP) in CreateLoadStoreMulti()
716 ? ARM::tSUBi3 in CreateLoadStoreMulti()
717 : isThumb1 ? ARM::tSUBi8 : ARM::SUBri; in CreateLoadStoreMulti()
736 (BaseOpc == ARM::tADDi8 || BaseOpc == ARM::tSUBi8)) { in CreateLoadStoreMulti()
743 BuildMI(MBB, InsertBefore, DL, TII->get(ARM::tMOVSr), NewBase) in CreateLoadStoreMulti()
746 BuildMI(MBB, InsertBefore, DL, TII->get(ARM::tMOVr), NewBase) in CreateLoadStoreMulti()
754 if (BaseOpc == ARM::tADDrSPi) { in CreateLoadStoreMulti()
800 if (Opcode == ARM::tLDMIA) { in CreateLoadStoreMulti()
803 Opcode = ARM::tLDMIA_UPD; in CreateLoadStoreMulti()
840 unsigned LoadStoreOpcode = IsLoad ? ARM::t2LDRDi8 : ARM::t2STRDi8; in CreateLoadStoreDouble()
961 assert(isi32Store(Opcode) || Opcode == ARM::VSTRS || Opcode == ARM::VSTRD); in MergeOpsUpdate()
995 if (getLoadStoreBaseOp(MI).getReg() == ARM::SP && in mayCombineMisaligned()
1037 if (PReg == ARM::SP || PReg == ARM::PC) in FormCandidates()
1050 case ARM::VLDRD: in FormCandidates()
1051 case ARM::VSTRD: in FormCandidates()
1063 if (Reg == ARM::SP || Reg == ARM::PC) in FormCandidates()
1122 case ARM::LDMIA: in getUpdatingLSMultipleOpcode()
1123 case ARM::LDMDA: in getUpdatingLSMultipleOpcode()
1124 case ARM::LDMDB: in getUpdatingLSMultipleOpcode()
1125 case ARM::LDMIB: in getUpdatingLSMultipleOpcode()
1128 case ARM_AM::ia: return ARM::LDMIA_UPD; in getUpdatingLSMultipleOpcode()
1129 case ARM_AM::ib: return ARM::LDMIB_UPD; in getUpdatingLSMultipleOpcode()
1130 case ARM_AM::da: return ARM::LDMDA_UPD; in getUpdatingLSMultipleOpcode()
1131 case ARM_AM::db: return ARM::LDMDB_UPD; in getUpdatingLSMultipleOpcode()
1133 case ARM::STMIA: in getUpdatingLSMultipleOpcode()
1134 case ARM::STMDA: in getUpdatingLSMultipleOpcode()
1135 case ARM::STMDB: in getUpdatingLSMultipleOpcode()
1136 case ARM::STMIB: in getUpdatingLSMultipleOpcode()
1139 case ARM_AM::ia: return ARM::STMIA_UPD; in getUpdatingLSMultipleOpcode()
1140 case ARM_AM::ib: return ARM::STMIB_UPD; in getUpdatingLSMultipleOpcode()
1141 case ARM_AM::da: return ARM::STMDA_UPD; in getUpdatingLSMultipleOpcode()
1142 case ARM_AM::db: return ARM::STMDB_UPD; in getUpdatingLSMultipleOpcode()
1144 case ARM::t2LDMIA: in getUpdatingLSMultipleOpcode()
1145 case ARM::t2LDMDB: in getUpdatingLSMultipleOpcode()
1148 case ARM_AM::ia: return ARM::t2LDMIA_UPD; in getUpdatingLSMultipleOpcode()
1149 case ARM_AM::db: return ARM::t2LDMDB_UPD; in getUpdatingLSMultipleOpcode()
1151 case ARM::t2STMIA: in getUpdatingLSMultipleOpcode()
1152 case ARM::t2STMDB: in getUpdatingLSMultipleOpcode()
1155 case ARM_AM::ia: return ARM::t2STMIA_UPD; in getUpdatingLSMultipleOpcode()
1156 case ARM_AM::db: return ARM::t2STMDB_UPD; in getUpdatingLSMultipleOpcode()
1158 case ARM::VLDMSIA: in getUpdatingLSMultipleOpcode()
1161 case ARM_AM::ia: return ARM::VLDMSIA_UPD; in getUpdatingLSMultipleOpcode()
1162 case ARM_AM::db: return ARM::VLDMSDB_UPD; in getUpdatingLSMultipleOpcode()
1164 case ARM::VLDMDIA: in getUpdatingLSMultipleOpcode()
1167 case ARM_AM::ia: return ARM::VLDMDIA_UPD; in getUpdatingLSMultipleOpcode()
1168 case ARM_AM::db: return ARM::VLDMDDB_UPD; in getUpdatingLSMultipleOpcode()
1170 case ARM::VSTMSIA: in getUpdatingLSMultipleOpcode()
1173 case ARM_AM::ia: return ARM::VSTMSIA_UPD; in getUpdatingLSMultipleOpcode()
1174 case ARM_AM::db: return ARM::VSTMSDB_UPD; in getUpdatingLSMultipleOpcode()
1176 case ARM::VSTMDIA: in getUpdatingLSMultipleOpcode()
1179 case ARM_AM::ia: return ARM::VSTMDIA_UPD; in getUpdatingLSMultipleOpcode()
1180 case ARM_AM::db: return ARM::VSTMDDB_UPD; in getUpdatingLSMultipleOpcode()
1193 case ARM::tADDi8: Scale = 4; CheckCPSRDef = true; break; in isIncrementOrDecrement()
1194 case ARM::tSUBi8: Scale = -4; CheckCPSRDef = true; break; in isIncrementOrDecrement()
1195 case ARM::t2SUBri: in isIncrementOrDecrement()
1196 case ARM::t2SUBspImm: in isIncrementOrDecrement()
1197 case ARM::SUBri: Scale = -1; CheckCPSRDef = true; break; in isIncrementOrDecrement()
1198 case ARM::t2ADDri: in isIncrementOrDecrement()
1199 case ARM::t2ADDspImm: in isIncrementOrDecrement()
1200 case ARM::ADDri: Scale = 1; CheckCPSRDef = true; break; in isIncrementOrDecrement()
1201 case ARM::tADDspi: Scale = 4; CheckCPSRDef = false; break; in isIncrementOrDecrement()
1202 case ARM::tSUBspi: Scale = -4; CheckCPSRDef = false; break; in isIncrementOrDecrement()
1265 if (Reg == ARM::SP || NextMBBI->readsRegister(Reg, TRI) || in findIncDecAfter()
1330 if (MI->getOperand(i).getReg() >= ARM::R8) { in MergeBaseUpdateLSMultiple()
1367 case ARM::LDRi12: in getPreIndexedLoadStoreOpcode()
1368 return ARM::LDR_PRE_IMM; in getPreIndexedLoadStoreOpcode()
1369 case ARM::STRi12: in getPreIndexedLoadStoreOpcode()
1370 return ARM::STR_PRE_IMM; in getPreIndexedLoadStoreOpcode()
1371 case ARM::VLDRS: in getPreIndexedLoadStoreOpcode()
1372 return Mode == ARM_AM::add ? ARM::VLDMSIA_UPD : ARM::VLDMSDB_UPD; in getPreIndexedLoadStoreOpcode()
1373 case ARM::VLDRD: in getPreIndexedLoadStoreOpcode()
1374 return Mode == ARM_AM::add ? ARM::VLDMDIA_UPD : ARM::VLDMDDB_UPD; in getPreIndexedLoadStoreOpcode()
1375 case ARM::VSTRS: in getPreIndexedLoadStoreOpcode()
1376 return Mode == ARM_AM::add ? ARM::VSTMSIA_UPD : ARM::VSTMSDB_UPD; in getPreIndexedLoadStoreOpcode()
1377 case ARM::VSTRD: in getPreIndexedLoadStoreOpcode()
1378 return Mode == ARM_AM::add ? ARM::VSTMDIA_UPD : ARM::VSTMDDB_UPD; in getPreIndexedLoadStoreOpcode()
1379 case ARM::t2LDRi8: in getPreIndexedLoadStoreOpcode()
1380 case ARM::t2LDRi12: in getPreIndexedLoadStoreOpcode()
1381 return ARM::t2LDR_PRE; in getPreIndexedLoadStoreOpcode()
1382 case ARM::t2STRi8: in getPreIndexedLoadStoreOpcode()
1383 case ARM::t2STRi12: in getPreIndexedLoadStoreOpcode()
1384 return ARM::t2STR_PRE; in getPreIndexedLoadStoreOpcode()
1392 case ARM::LDRi12: in getPostIndexedLoadStoreOpcode()
1393 return ARM::LDR_POST_IMM; in getPostIndexedLoadStoreOpcode()
1394 case ARM::STRi12: in getPostIndexedLoadStoreOpcode()
1395 return ARM::STR_POST_IMM; in getPostIndexedLoadStoreOpcode()
1396 case ARM::VLDRS: in getPostIndexedLoadStoreOpcode()
1397 return Mode == ARM_AM::add ? ARM::VLDMSIA_UPD : ARM::VLDMSDB_UPD; in getPostIndexedLoadStoreOpcode()
1398 case ARM::VLDRD: in getPostIndexedLoadStoreOpcode()
1399 return Mode == ARM_AM::add ? ARM::VLDMDIA_UPD : ARM::VLDMDDB_UPD; in getPostIndexedLoadStoreOpcode()
1400 case ARM::VSTRS: in getPostIndexedLoadStoreOpcode()
1401 return Mode == ARM_AM::add ? ARM::VSTMSIA_UPD : ARM::VSTMSDB_UPD; in getPostIndexedLoadStoreOpcode()
1402 case ARM::VSTRD: in getPostIndexedLoadStoreOpcode()
1403 return Mode == ARM_AM::add ? ARM::VSTMDIA_UPD : ARM::VSTMDDB_UPD; in getPostIndexedLoadStoreOpcode()
1404 case ARM::t2LDRi8: in getPostIndexedLoadStoreOpcode()
1405 case ARM::t2LDRi12: in getPostIndexedLoadStoreOpcode()
1406 return ARM::t2LDR_POST; in getPostIndexedLoadStoreOpcode()
1407 case ARM::t2LDRBi8: in getPostIndexedLoadStoreOpcode()
1408 case ARM::t2LDRBi12: in getPostIndexedLoadStoreOpcode()
1409 return ARM::t2LDRB_POST; in getPostIndexedLoadStoreOpcode()
1410 case ARM::t2LDRSBi8: in getPostIndexedLoadStoreOpcode()
1411 case ARM::t2LDRSBi12: in getPostIndexedLoadStoreOpcode()
1412 return ARM::t2LDRSB_POST; in getPostIndexedLoadStoreOpcode()
1413 case ARM::t2LDRHi8: in getPostIndexedLoadStoreOpcode()
1414 case ARM::t2LDRHi12: in getPostIndexedLoadStoreOpcode()
1415 return ARM::t2LDRH_POST; in getPostIndexedLoadStoreOpcode()
1416 case ARM::t2LDRSHi8: in getPostIndexedLoadStoreOpcode()
1417 case ARM::t2LDRSHi12: in getPostIndexedLoadStoreOpcode()
1418 return ARM::t2LDRSH_POST; in getPostIndexedLoadStoreOpcode()
1419 case ARM::t2STRi8: in getPostIndexedLoadStoreOpcode()
1420 case ARM::t2STRi12: in getPostIndexedLoadStoreOpcode()
1421 return ARM::t2STR_POST; in getPostIndexedLoadStoreOpcode()
1422 case ARM::t2STRBi8: in getPostIndexedLoadStoreOpcode()
1423 case ARM::t2STRBi12: in getPostIndexedLoadStoreOpcode()
1424 return ARM::t2STRB_POST; in getPostIndexedLoadStoreOpcode()
1425 case ARM::t2STRHi8: in getPostIndexedLoadStoreOpcode()
1426 case ARM::t2STRHi12: in getPostIndexedLoadStoreOpcode()
1427 return ARM::t2STRH_POST; in getPostIndexedLoadStoreOpcode()
1429 case ARM::MVE_VLDRBS16: in getPostIndexedLoadStoreOpcode()
1430 return ARM::MVE_VLDRBS16_post; in getPostIndexedLoadStoreOpcode()
1431 case ARM::MVE_VLDRBS32: in getPostIndexedLoadStoreOpcode()
1432 return ARM::MVE_VLDRBS32_post; in getPostIndexedLoadStoreOpcode()
1433 case ARM::MVE_VLDRBU16: in getPostIndexedLoadStoreOpcode()
1434 return ARM::MVE_VLDRBU16_post; in getPostIndexedLoadStoreOpcode()
1435 case ARM::MVE_VLDRBU32: in getPostIndexedLoadStoreOpcode()
1436 return ARM::MVE_VLDRBU32_post; in getPostIndexedLoadStoreOpcode()
1437 case ARM::MVE_VLDRHS32: in getPostIndexedLoadStoreOpcode()
1438 return ARM::MVE_VLDRHS32_post; in getPostIndexedLoadStoreOpcode()
1439 case ARM::MVE_VLDRHU32: in getPostIndexedLoadStoreOpcode()
1440 return ARM::MVE_VLDRHU32_post; in getPostIndexedLoadStoreOpcode()
1441 case ARM::MVE_VLDRBU8: in getPostIndexedLoadStoreOpcode()
1442 return ARM::MVE_VLDRBU8_post; in getPostIndexedLoadStoreOpcode()
1443 case ARM::MVE_VLDRHU16: in getPostIndexedLoadStoreOpcode()
1444 return ARM::MVE_VLDRHU16_post; in getPostIndexedLoadStoreOpcode()
1445 case ARM::MVE_VLDRWU32: in getPostIndexedLoadStoreOpcode()
1446 return ARM::MVE_VLDRWU32_post; in getPostIndexedLoadStoreOpcode()
1447 case ARM::MVE_VSTRB16: in getPostIndexedLoadStoreOpcode()
1448 return ARM::MVE_VSTRB16_post; in getPostIndexedLoadStoreOpcode()
1449 case ARM::MVE_VSTRB32: in getPostIndexedLoadStoreOpcode()
1450 return ARM::MVE_VSTRB32_post; in getPostIndexedLoadStoreOpcode()
1451 case ARM::MVE_VSTRH32: in getPostIndexedLoadStoreOpcode()
1452 return ARM::MVE_VSTRH32_post; in getPostIndexedLoadStoreOpcode()
1453 case ARM::MVE_VSTRBU8: in getPostIndexedLoadStoreOpcode()
1454 return ARM::MVE_VSTRBU8_post; in getPostIndexedLoadStoreOpcode()
1455 case ARM::MVE_VSTRHU16: in getPostIndexedLoadStoreOpcode()
1456 return ARM::MVE_VSTRHU16_post; in getPostIndexedLoadStoreOpcode()
1457 case ARM::MVE_VSTRWU32: in getPostIndexedLoadStoreOpcode()
1458 return ARM::MVE_VSTRWU32_post; in getPostIndexedLoadStoreOpcode()
1476 bool isAM5 = (Opcode == ARM::VLDRD || Opcode == ARM::VLDRS || in MergeBaseUpdateLoadStore()
1477 Opcode == ARM::VSTRD || Opcode == ARM::VSTRS); in MergeBaseUpdateLoadStore()
1478 bool isAM2 = (Opcode == ARM::LDRi12 || Opcode == ARM::STRi12); in MergeBaseUpdateLoadStore()
1541 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) { in MergeBaseUpdateLoadStore()
1582 if (isAM2 && NewOpc == ARM::STR_POST_IMM) { in MergeBaseUpdateLoadStore()
1613 assert((Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8) && in MergeBaseUpdateLSDouble()
1637 NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_PRE : ARM::t2STRD_PRE; in MergeBaseUpdateLSDouble()
1642 NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_POST : ARM::t2STRD_POST; in MergeBaseUpdateLSDouble()
1651 if (NewOpc == ARM::t2LDRD_PRE || NewOpc == ARM::t2LDRD_POST) { in MergeBaseUpdateLSDouble()
1654 assert(NewOpc == ARM::t2STRD_PRE || NewOpc == ARM::t2STRD_POST); in MergeBaseUpdateLSDouble()
1678 case ARM::VLDRS: in isMemoryOp()
1679 case ARM::VSTRS: in isMemoryOp()
1680 case ARM::VLDRD: in isMemoryOp()
1681 case ARM::VSTRD: in isMemoryOp()
1682 case ARM::LDRi12: in isMemoryOp()
1683 case ARM::STRi12: in isMemoryOp()
1684 case ARM::tLDRi: in isMemoryOp()
1685 case ARM::tSTRi: in isMemoryOp()
1686 case ARM::tLDRspi: in isMemoryOp()
1687 case ARM::tSTRspi: in isMemoryOp()
1688 case ARM::t2LDRi8: in isMemoryOp()
1689 case ARM::t2LDRi12: in isMemoryOp()
1690 case ARM::t2STRi8: in isMemoryOp()
1691 case ARM::t2STRi12: in isMemoryOp()
1764 if (Opcode != ARM::LDRD && Opcode != ARM::STRD && Opcode != ARM::t2LDRDi8) in FixInvalidRegPairOp()
1777 (Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8) && STI->isCortexM3(); in FixInvalidRegPairOp()
1779 bool NonConsecutiveRegs = (Opcode == ARM::LDRD || Opcode == ARM::STRD) && in FixInvalidRegPairOp()
1785 bool isT2 = Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8; in FixInvalidRegPairOp()
1786 bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8; in FixInvalidRegPairOp()
1795 assert((isT2 || MI->getOperand(3).getReg() == ARM::NoRegister) && in FixInvalidRegPairOp()
1805 ? (isT2 ? ARM::t2LDMIA : ARM::LDMIA) in FixInvalidRegPairOp()
1806 : (isT2 ? ARM::t2STMIA : ARM::STMIA); in FixInvalidRegPairOp()
1829 ? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()
1830 : (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12); in FixInvalidRegPairOp()
1834 ? (isT2 ? (OffImm+4 < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()
1835 : (isT2 ? (OffImm+4 < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12); in FixInvalidRegPairOp()
1963 } else if (MBBI->getOpcode() == ARM::t2LDRDi8 || in LoadStoreMultipleOpti()
1964 MBBI->getOpcode() == ARM::t2STRDi8) { in LoadStoreMultipleOpti()
1999 if (Opcode == ARM::t2STRDi8 || Opcode == ARM::t2LDRDi8) in LoadStoreMultipleOpti()
2041 (MBBI->getOpcode() == ARM::BX_RET || in MergeReturnIntoLDM()
2042 MBBI->getOpcode() == ARM::tBX_RET || in MergeReturnIntoLDM()
2043 MBBI->getOpcode() == ARM::MOVPCLR)) { in MergeReturnIntoLDM()
2050 if (Opcode == ARM::LDMIA_UPD || Opcode == ARM::LDMDA_UPD || in MergeReturnIntoLDM()
2051 Opcode == ARM::LDMDB_UPD || Opcode == ARM::LDMIB_UPD || in MergeReturnIntoLDM()
2052 Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) { in MergeReturnIntoLDM()
2054 if (MO.getReg() != ARM::LR) in MergeReturnIntoLDM()
2056 unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET); in MergeReturnIntoLDM()
2057 assert(((isThumb2 && Opcode == ARM::t2LDMIA_UPD) || in MergeReturnIntoLDM()
2058 Opcode == ARM::LDMIA_UPD) && "Unsupported multiple load-return!"); in MergeReturnIntoLDM()
2060 MO.setReg(ARM::PC); in MergeReturnIntoLDM()
2069 if (Info.getReg() == ARM::LR) { in MergeReturnIntoLDM()
2083 MBBI->getOpcode() != ARM::tBX_RET) in CombineMovBx()
2088 if (Prev->getOpcode() != ARM::tMOVr || !Prev->definesRegister(ARM::LR)) in CombineMovBx()
2094 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(ARM::tBX)) in CombineMovBx()
2267 if (Opcode == ARM::LDRi12) { in CanFormLdStDWord()
2268 NewOpc = ARM::LDRD; in CanFormLdStDWord()
2269 } else if (Opcode == ARM::STRi12) { in CanFormLdStDWord()
2270 NewOpc = ARM::STRD; in CanFormLdStDWord()
2271 } else if (Opcode == ARM::t2LDRi8 || Opcode == ARM::t2LDRi12) { in CanFormLdStDWord()
2272 NewOpc = ARM::t2LDRDi8; in CanFormLdStDWord()
2275 } else if (Opcode == ARM::t2STRi8 || Opcode == ARM::t2STRi12) { in CanFormLdStDWord()
2276 NewOpc = ARM::t2STRDi8; in CanFormLdStDWord()
2596 case ARM::MVE_VLDRBS16: in getBaseOperandIndex()
2597 case ARM::MVE_VLDRBS32: in getBaseOperandIndex()
2598 case ARM::MVE_VLDRBU16: in getBaseOperandIndex()
2599 case ARM::MVE_VLDRBU32: in getBaseOperandIndex()
2600 case ARM::MVE_VLDRHS32: in getBaseOperandIndex()
2601 case ARM::MVE_VLDRHU32: in getBaseOperandIndex()
2602 case ARM::MVE_VLDRBU8: in getBaseOperandIndex()
2603 case ARM::MVE_VLDRHU16: in getBaseOperandIndex()
2604 case ARM::MVE_VLDRWU32: in getBaseOperandIndex()
2605 case ARM::MVE_VSTRB16: in getBaseOperandIndex()
2606 case ARM::MVE_VSTRB32: in getBaseOperandIndex()
2607 case ARM::MVE_VSTRH32: in getBaseOperandIndex()
2608 case ARM::MVE_VSTRBU8: in getBaseOperandIndex()
2609 case ARM::MVE_VSTRHU16: in getBaseOperandIndex()
2610 case ARM::MVE_VSTRWU32: in getBaseOperandIndex()
2611 case ARM::t2LDRHi8: in getBaseOperandIndex()
2612 case ARM::t2LDRHi12: in getBaseOperandIndex()
2613 case ARM::t2LDRSHi8: in getBaseOperandIndex()
2614 case ARM::t2LDRSHi12: in getBaseOperandIndex()
2615 case ARM::t2LDRBi8: in getBaseOperandIndex()
2616 case ARM::t2LDRBi12: in getBaseOperandIndex()
2617 case ARM::t2LDRSBi8: in getBaseOperandIndex()
2618 case ARM::t2LDRSBi12: in getBaseOperandIndex()
2619 case ARM::t2STRBi8: in getBaseOperandIndex()
2620 case ARM::t2STRBi12: in getBaseOperandIndex()
2621 case ARM::t2STRHi8: in getBaseOperandIndex()
2622 case ARM::t2STRHi12: in getBaseOperandIndex()
2624 case ARM::MVE_VLDRBS16_post: in getBaseOperandIndex()
2625 case ARM::MVE_VLDRBS32_post: in getBaseOperandIndex()
2626 case ARM::MVE_VLDRBU16_post: in getBaseOperandIndex()
2627 case ARM::MVE_VLDRBU32_post: in getBaseOperandIndex()
2628 case ARM::MVE_VLDRHS32_post: in getBaseOperandIndex()
2629 case ARM::MVE_VLDRHU32_post: in getBaseOperandIndex()
2630 case ARM::MVE_VLDRBU8_post: in getBaseOperandIndex()
2631 case ARM::MVE_VLDRHU16_post: in getBaseOperandIndex()
2632 case ARM::MVE_VLDRWU32_post: in getBaseOperandIndex()
2633 case ARM::MVE_VSTRB16_post: in getBaseOperandIndex()
2634 case ARM::MVE_VSTRB32_post: in getBaseOperandIndex()
2635 case ARM::MVE_VSTRH32_post: in getBaseOperandIndex()
2636 case ARM::MVE_VSTRBU8_post: in getBaseOperandIndex()
2637 case ARM::MVE_VSTRHU16_post: in getBaseOperandIndex()
2638 case ARM::MVE_VSTRWU32_post: in getBaseOperandIndex()
2639 case ARM::MVE_VLDRBS16_pre: in getBaseOperandIndex()
2640 case ARM::MVE_VLDRBS32_pre: in getBaseOperandIndex()
2641 case ARM::MVE_VLDRBU16_pre: in getBaseOperandIndex()
2642 case ARM::MVE_VLDRBU32_pre: in getBaseOperandIndex()
2643 case ARM::MVE_VLDRHS32_pre: in getBaseOperandIndex()
2644 case ARM::MVE_VLDRHU32_pre: in getBaseOperandIndex()
2645 case ARM::MVE_VLDRBU8_pre: in getBaseOperandIndex()
2646 case ARM::MVE_VLDRHU16_pre: in getBaseOperandIndex()
2647 case ARM::MVE_VLDRWU32_pre: in getBaseOperandIndex()
2648 case ARM::MVE_VSTRB16_pre: in getBaseOperandIndex()
2649 case ARM::MVE_VSTRB32_pre: in getBaseOperandIndex()
2650 case ARM::MVE_VSTRH32_pre: in getBaseOperandIndex()
2651 case ARM::MVE_VSTRBU8_pre: in getBaseOperandIndex()
2652 case ARM::MVE_VSTRHU16_pre: in getBaseOperandIndex()
2653 case ARM::MVE_VSTRWU32_pre: in getBaseOperandIndex()
2661 case ARM::MVE_VLDRBS16_post: in isPostIndex()
2662 case ARM::MVE_VLDRBS32_post: in isPostIndex()
2663 case ARM::MVE_VLDRBU16_post: in isPostIndex()
2664 case ARM::MVE_VLDRBU32_post: in isPostIndex()
2665 case ARM::MVE_VLDRHS32_post: in isPostIndex()
2666 case ARM::MVE_VLDRHU32_post: in isPostIndex()
2667 case ARM::MVE_VLDRBU8_post: in isPostIndex()
2668 case ARM::MVE_VLDRHU16_post: in isPostIndex()
2669 case ARM::MVE_VLDRWU32_post: in isPostIndex()
2670 case ARM::MVE_VSTRB16_post: in isPostIndex()
2671 case ARM::MVE_VSTRB32_post: in isPostIndex()
2672 case ARM::MVE_VSTRH32_post: in isPostIndex()
2673 case ARM::MVE_VSTRBU8_post: in isPostIndex()
2674 case ARM::MVE_VSTRHU16_post: in isPostIndex()
2675 case ARM::MVE_VSTRWU32_post: in isPostIndex()
2683 case ARM::MVE_VLDRBS16_pre: in isPreIndex()
2684 case ARM::MVE_VLDRBS32_pre: in isPreIndex()
2685 case ARM::MVE_VLDRBU16_pre: in isPreIndex()
2686 case ARM::MVE_VLDRBU32_pre: in isPreIndex()
2687 case ARM::MVE_VLDRHS32_pre: in isPreIndex()
2688 case ARM::MVE_VLDRHU32_pre: in isPreIndex()
2689 case ARM::MVE_VLDRBU8_pre: in isPreIndex()
2690 case ARM::MVE_VLDRHU16_pre: in isPreIndex()
2691 case ARM::MVE_VLDRWU32_pre: in isPreIndex()
2692 case ARM::MVE_VSTRB16_pre: in isPreIndex()
2693 case ARM::MVE_VSTRB32_pre: in isPreIndex()
2694 case ARM::MVE_VSTRH32_pre: in isPreIndex()
2695 case ARM::MVE_VSTRBU8_pre: in isPreIndex()
2696 case ARM::MVE_VSTRHU16_pre: in isPreIndex()
2697 case ARM::MVE_VSTRWU32_pre: in isPreIndex()
2747 case ARM::t2LDRHi12: in AdjustBaseAndOffset()
2748 ConvOpcode = ARM::t2LDRHi8; in AdjustBaseAndOffset()
2750 case ARM::t2LDRSHi12: in AdjustBaseAndOffset()
2751 ConvOpcode = ARM::t2LDRSHi8; in AdjustBaseAndOffset()
2753 case ARM::t2LDRBi12: in AdjustBaseAndOffset()
2754 ConvOpcode = ARM::t2LDRBi8; in AdjustBaseAndOffset()
2756 case ARM::t2LDRSBi12: in AdjustBaseAndOffset()
2757 ConvOpcode = ARM::t2LDRSBi8; in AdjustBaseAndOffset()
2759 case ARM::t2STRHi12: in AdjustBaseAndOffset()
2760 ConvOpcode = ARM::t2STRHi8; in AdjustBaseAndOffset()
2762 case ARM::t2STRBi12: in AdjustBaseAndOffset()
2763 ConvOpcode = ARM::t2STRBi8; in AdjustBaseAndOffset()
2893 if (Increment->definesRegister(ARM::CPSR) || in DistributeIncrements()