1102 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,  in AddDReg()  function in ARMBaseInstrInfo
1174           AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
1175           AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);  in storeRegToStackSlot()
1185           AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
1186           AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);  in storeRegToStackSlot()
1236           MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
1237           MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);  in storeRegToStackSlot()
1238           AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);  in storeRegToStackSlot()
1261           MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
1262           MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);  in storeRegToStackSlot()
1263           MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);  in storeRegToStackSlot()
1264                 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);  in storeRegToStackSlot()
1275         MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);  in storeRegToStackSlot()
1276         MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);  in storeRegToStackSlot()
1277         MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);  in storeRegToStackSlot()
1278         MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);  in storeRegToStackSlot()
1279         MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);  in storeRegToStackSlot()
1280         MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);  in storeRegToStackSlot()
1281         MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);  in storeRegToStackSlot()
1282               AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);  in storeRegToStackSlot()
1408         AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1409         AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1419         MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1420         MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1466         MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1467         MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1468         MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1489         MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1490         MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1491         MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1492         MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1505       MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1506       MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1507       MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1508       MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1509       MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1510       MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1511       MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
1512       MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()