Lines Matching refs:Val
97 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, in decodeBoolReg() argument
100 return addOperand(Inst, DAsm->decodeBoolReg(Val)); in decodeBoolReg()
838 unsigned Val) const { in createRegOperand()
840 if (Val >= RegCl.getNumRegs()) in createRegOperand()
841 return errOperand(Val, Twine(getRegClassName(RegClassID)) + in createRegOperand()
842 ": unknown register " + Twine(Val)); in createRegOperand()
843 return createRegOperand(RegCl.getRegister(Val)); in createRegOperand()
848 unsigned Val) const { in createSRegOperand()
878 if (Val % (1 << shift)) { in createSRegOperand()
880 << ": scalar reg isn't aligned " << Val; in createSRegOperand()
883 return createRegOperand(SRegClassID, Val >> shift); in createSRegOperand()
886 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { in decodeOperand_VS_32()
887 return decodeSrcOp(OPW32, Val); in decodeOperand_VS_32()
890 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { in decodeOperand_VS_64()
891 return decodeSrcOp(OPW64, Val); in decodeOperand_VS_64()
894 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { in decodeOperand_VS_128()
895 return decodeSrcOp(OPW128, Val); in decodeOperand_VS_128()
898 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { in decodeOperand_VSrc16()
899 return decodeSrcOp(OPW16, Val); in decodeOperand_VSrc16()
902 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { in decodeOperand_VSrcV216()
903 return decodeSrcOp(OPWV216, Val); in decodeOperand_VSrcV216()
906 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { in decodeOperand_VSrcV232()
907 return decodeSrcOp(OPWV232, Val); in decodeOperand_VSrcV232()
910 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { in decodeOperand_VGPR_32()
914 Val &= 255; in decodeOperand_VGPR_32()
916 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); in decodeOperand_VGPR_32()
919 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { in decodeOperand_VRegOrLds_32()
920 return decodeSrcOp(OPW32, Val); in decodeOperand_VRegOrLds_32()
923 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { in decodeOperand_AGPR_32()
924 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); in decodeOperand_AGPR_32()
927 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { in decodeOperand_AReg_64()
928 return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); in decodeOperand_AReg_64()
931 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { in decodeOperand_AReg_128()
932 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); in decodeOperand_AReg_128()
935 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { in decodeOperand_AReg_256()
936 return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); in decodeOperand_AReg_256()
939 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { in decodeOperand_AReg_512()
940 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); in decodeOperand_AReg_512()
943 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { in decodeOperand_AReg_1024()
944 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); in decodeOperand_AReg_1024()
947 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { in decodeOperand_AV_32()
948 return decodeSrcOp(OPW32, Val); in decodeOperand_AV_32()
951 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { in decodeOperand_AV_64()
952 return decodeSrcOp(OPW64, Val); in decodeOperand_AV_64()
955 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { in decodeOperand_VReg_64()
956 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); in decodeOperand_VReg_64()
959 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { in decodeOperand_VReg_96()
960 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); in decodeOperand_VReg_96()
963 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { in decodeOperand_VReg_128()
964 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); in decodeOperand_VReg_128()
967 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { in decodeOperand_VReg_256()
968 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); in decodeOperand_VReg_256()
971 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { in decodeOperand_VReg_512()
972 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); in decodeOperand_VReg_512()
975 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { in decodeOperand_VReg_1024()
976 return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); in decodeOperand_VReg_1024()
979 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { in decodeOperand_SReg_32()
983 return decodeSrcOp(OPW32, Val); in decodeOperand_SReg_32()
987 unsigned Val) const { in decodeOperand_SReg_32_XM0_XEXEC()
989 return decodeOperand_SReg_32(Val); in decodeOperand_SReg_32_XM0_XEXEC()
993 unsigned Val) const { in decodeOperand_SReg_32_XEXEC_HI()
995 return decodeOperand_SReg_32(Val); in decodeOperand_SReg_32_XEXEC_HI()
998 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { in decodeOperand_SRegOrLds_32()
1002 return decodeSrcOp(OPW32, Val); in decodeOperand_SRegOrLds_32()
1005 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { in decodeOperand_SReg_64()
1006 return decodeSrcOp(OPW64, Val); in decodeOperand_SReg_64()
1009 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { in decodeOperand_SReg_64_XEXEC()
1010 return decodeSrcOp(OPW64, Val); in decodeOperand_SReg_64_XEXEC()
1013 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { in decodeOperand_SReg_128()
1014 return decodeSrcOp(OPW128, Val); in decodeOperand_SReg_128()
1017 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { in decodeOperand_SReg_256()
1018 return decodeDstOp(OPW256, Val); in decodeOperand_SReg_256()
1021 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { in decodeOperand_SReg_512()
1022 return decodeDstOp(OPW512, Val); in decodeOperand_SReg_512()
1229 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { in getTTmpIdx()
1235 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; in getTTmpIdx()
1238 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const { in decodeSrcOp()
1241 assert(Val < 1024); // enum10 in decodeSrcOp()
1243 bool IsAGPR = Val & 512; in decodeSrcOp()
1244 Val &= 511; in decodeSrcOp()
1246 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { in decodeSrcOp()
1248 : getVgprClassId(Width), Val - VGPR_MIN); in decodeSrcOp()
1250 if (Val <= SGPR_MAX) { in decodeSrcOp()
1253 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); in decodeSrcOp()
1256 int TTmpIdx = getTTmpIdx(Val); in decodeSrcOp()
1261 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) in decodeSrcOp()
1262 return decodeIntImmed(Val); in decodeSrcOp()
1264 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) in decodeSrcOp()
1265 return decodeFPImmed(Width, Val); in decodeSrcOp()
1267 if (Val == LITERAL_CONST) in decodeSrcOp()
1274 return decodeSpecialReg32(Val); in decodeSrcOp()
1277 return decodeSpecialReg64(Val); in decodeSrcOp()
1283 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { in decodeDstOp()
1286 assert(Val < 128); in decodeDstOp()
1289 if (Val <= SGPR_MAX) { in decodeDstOp()
1292 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); in decodeDstOp()
1295 int TTmpIdx = getTTmpIdx(Val); in decodeDstOp()
1303 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { in decodeSpecialReg32()
1306 switch (Val) { in decodeSpecialReg32()
1332 return errOperand(Val, "unknown operand encoding " + Twine(Val)); in decodeSpecialReg32()
1335 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { in decodeSpecialReg64()
1338 switch (Val) { in decodeSpecialReg64()
1356 return errOperand(Val, "unknown operand encoding " + Twine(Val)); in decodeSpecialReg64()
1360 const unsigned Val) const { in decodeSDWASrc()
1368 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && in decodeSDWASrc()
1369 Val <= SDWA9EncValues::SRC_VGPR_MAX) { in decodeSDWASrc()
1371 Val - SDWA9EncValues::SRC_VGPR_MIN); in decodeSDWASrc()
1373 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && in decodeSDWASrc()
1374 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 in decodeSDWASrc()
1377 Val - SDWA9EncValues::SRC_SGPR_MIN); in decodeSDWASrc()
1379 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && in decodeSDWASrc()
1380 Val <= SDWA9EncValues::SRC_TTMP_MAX) { in decodeSDWASrc()
1382 Val - SDWA9EncValues::SRC_TTMP_MIN); in decodeSDWASrc()
1385 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; in decodeSDWASrc()
1395 return createRegOperand(getVgprClassId(Width), Val); in decodeSDWASrc()
1400 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { in decodeSDWASrc16()
1401 return decodeSDWASrc(OPW16, Val); in decodeSDWASrc16()
1404 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { in decodeSDWASrc32()
1405 return decodeSDWASrc(OPW32, Val); in decodeSDWASrc32()
1408 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { in decodeSDWAVopcDst()
1417 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { in decodeSDWAVopcDst()
1418 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; in decodeSDWAVopcDst()
1420 int TTmpIdx = getTTmpIdx(Val); in decodeSDWAVopcDst()
1424 } else if (Val > SGPR_MAX) { in decodeSDWAVopcDst()
1425 return IsWave64 ? decodeSpecialReg64(Val) in decodeSDWAVopcDst()
1426 : decodeSpecialReg32(Val); in decodeSDWAVopcDst()
1428 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); in decodeSDWAVopcDst()
1435 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { in decodeBoolReg()
1437 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); in decodeBoolReg()
1837 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { in tryAddingSymbolicOperand() argument
1838 return Val.Addr == static_cast<uint64_t>(Value) && in tryAddingSymbolicOperand()
1839 Val.Type == ELF::STT_NOTYPE; in tryAddingSymbolicOperand()