Lines Matching refs:SL
1400 SDLoc SL(Op); in LowerCONCAT_VECTORS() local
1401 SDValue Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(0)); in LowerCONCAT_VECTORS()
1402 SDValue Hi = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(1)); in LowerCONCAT_VECTORS()
1404 SDValue BV = DAG.getBuildVector(MVT::v2i32, SL, { Lo, Hi }); in LowerCONCAT_VECTORS()
1405 return DAG.getNode(ISD::BITCAST, SL, VT, BV); in LowerCONCAT_VECTORS()
1510 SDLoc SL(Op); in split64BitValue() local
1512 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in split64BitValue()
1514 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in split64BitValue()
1515 const SDValue One = DAG.getConstant(1, SL, MVT::i32); in split64BitValue()
1517 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in split64BitValue()
1518 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in split64BitValue()
1524 SDLoc SL(Op); in getLoHalf64() local
1526 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in getLoHalf64()
1527 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in getLoHalf64()
1528 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in getLoHalf64()
1532 SDLoc SL(Op); in getHiHalf64() local
1534 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in getHiHalf64()
1535 const SDValue One = DAG.getConstant(1, SL, MVT::i32); in getHiHalf64()
1536 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in getHiHalf64()
1577 SDLoc SL(Op); in SplitVectorLoad() local
1585 return DAG.getMergeValues(Ops, SL); in SplitVectorLoad()
1599 std::tie(Lo, Hi) = splitVector(Op, SL, LoVT, HiVT, DAG); in SplitVectorLoad()
1605 SDValue LoLoad = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT, in SplitVectorLoad()
1608 SDValue HiPtr = DAG.getObjectPtrOffset(SL, BasePtr, TypeSize::Fixed(Size)); in SplitVectorLoad()
1610 DAG.getExtLoad(Load->getExtensionType(), SL, HiVT, Load->getChain(), in SplitVectorLoad()
1617 Join = DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad); in SplitVectorLoad()
1619 Join = DAG.getNode(ISD::INSERT_SUBVECTOR, SL, VT, DAG.getUNDEF(VT), LoLoad, in SplitVectorLoad()
1620 DAG.getVectorIdxConstant(0, SL)); in SplitVectorLoad()
1622 HiVT.isVector() ? ISD::INSERT_SUBVECTOR : ISD::INSERT_VECTOR_ELT, SL, in SplitVectorLoad()
1624 DAG.getVectorIdxConstant(LoVT.getVectorNumElements(), SL)); in SplitVectorLoad()
1627 SDValue Ops[] = {Join, DAG.getNode(ISD::TokenFactor, SL, MVT::Other, in SplitVectorLoad()
1630 return DAG.getMergeValues(Ops, SL); in SplitVectorLoad()
1639 SDLoc SL(Op); in WidenOrSplitVectorLoad() local
1658 Load->getExtensionType(), SL, WideVT, Load->getChain(), BasePtr, SrcValue, in WidenOrSplitVectorLoad()
1661 {DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, VT, WideLoad, in WidenOrSplitVectorLoad()
1662 DAG.getVectorIdxConstant(0, SL)), in WidenOrSplitVectorLoad()
1664 SL); in WidenOrSplitVectorLoad()
1681 SDLoc SL(Op); in SplitVectorStore() local
1689 std::tie(Lo, Hi) = splitVector(Val, SL, LoVT, HiVT, DAG); in SplitVectorStore()
1691 SDValue HiPtr = DAG.getObjectPtrOffset(SL, BasePtr, LoMemVT.getStoreSize()); in SplitVectorStore()
1699 DAG.getTruncStore(Chain, SL, Lo, BasePtr, SrcValue, LoMemVT, BaseAlign, in SplitVectorStore()
1702 DAG.getTruncStore(Chain, SL, Hi, HiPtr, SrcValue.getWithOffset(Size), in SplitVectorStore()
1705 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore); in SplitVectorStore()
2154 SDLoc SL(Op); in LowerFREM() local
2160 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y, Flags); in LowerFREM()
2161 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, VT, Div, Flags); in LowerFREM()
2162 SDValue Neg = DAG.getNode(ISD::FNEG, SL, VT, Trunc, Flags); in LowerFREM()
2164 return DAG.getNode(ISD::FMA, SL, VT, Neg, Y, X, Flags); in LowerFREM()
2168 SDLoc SL(Op); in LowerFCEIL() local
2175 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFCEIL()
2177 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64); in LowerFCEIL()
2178 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64); in LowerFCEIL()
2183 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT); in LowerFCEIL()
2184 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE); in LowerFCEIL()
2185 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc); in LowerFCEIL()
2187 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero); in LowerFCEIL()
2189 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFCEIL()
2192 static SDValue extractF64Exponent(SDValue Hi, const SDLoc &SL, in extractF64Exponent() argument
2197 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32, in extractF64Exponent()
2199 DAG.getConstant(FractBits - 32, SL, MVT::i32), in extractF64Exponent()
2200 DAG.getConstant(ExpBits, SL, MVT::i32)); in extractF64Exponent()
2201 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart, in extractF64Exponent()
2202 DAG.getConstant(1023, SL, MVT::i32)); in extractF64Exponent()
2208 SDLoc SL(Op); in LowerFTRUNC() local
2213 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in LowerFTRUNC()
2214 const SDValue One = DAG.getConstant(1, SL, MVT::i32); in LowerFTRUNC()
2216 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src); in LowerFTRUNC()
2220 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One); in LowerFTRUNC()
2222 SDValue Exp = extractF64Exponent(Hi, SL, DAG); in LowerFTRUNC()
2227 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, SL, MVT::i32); in LowerFTRUNC()
2228 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask); in LowerFTRUNC()
2231 SDValue SignBit64 = DAG.getBuildVector(MVT::v2i32, SL, {Zero, SignBit}); in LowerFTRUNC()
2232 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64); in LowerFTRUNC()
2234 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src); in LowerFTRUNC()
2236 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, SL, MVT::i64); in LowerFTRUNC()
2238 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp); in LowerFTRUNC()
2239 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64); in LowerFTRUNC()
2240 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not); in LowerFTRUNC()
2245 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32); in LowerFTRUNC()
2247 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT); in LowerFTRUNC()
2248 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT); in LowerFTRUNC()
2250 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0); in LowerFTRUNC()
2251 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1); in LowerFTRUNC()
2253 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2); in LowerFTRUNC()
2257 SDLoc SL(Op); in LowerFRINT() local
2263 SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64); in LowerFRINT()
2264 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src); in LowerFRINT()
2268 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); in LowerFRINT()
2269 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); in LowerFRINT()
2271 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src); in LowerFRINT()
2274 SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64); in LowerFRINT()
2278 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT); in LowerFRINT()
2280 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2); in LowerFRINT()
2296 SDLoc SL(Op); in LowerFROUND() local
2300 SDValue T = DAG.getNode(ISD::FTRUNC, SL, VT, X); in LowerFROUND()
2304 SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T); in LowerFROUND()
2306 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff); in LowerFROUND()
2308 const SDValue Zero = DAG.getConstantFP(0.0, SL, VT); in LowerFROUND()
2309 const SDValue One = DAG.getConstantFP(1.0, SL, VT); in LowerFROUND()
2310 const SDValue Half = DAG.getConstantFP(0.5, SL, VT); in LowerFROUND()
2312 SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, VT, One, X); in LowerFROUND()
2317 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE); in LowerFROUND()
2319 SDValue Sel = DAG.getNode(ISD::SELECT, SL, VT, Cmp, SignOne, Zero); in LowerFROUND()
2321 return DAG.getNode(ISD::FADD, SL, VT, T, Sel); in LowerFROUND()
2325 SDLoc SL(Op); in LowerFFLOOR() local
2332 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFFLOOR()
2334 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64); in LowerFFLOOR()
2335 const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64); in LowerFFLOOR()
2340 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT); in LowerFFLOOR()
2341 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE); in LowerFFLOOR()
2342 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc); in LowerFFLOOR()
2344 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero); in LowerFFLOOR()
2346 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFFLOOR()
2353 SDLoc SL(Op); in LowerFLOG() local
2355 SDValue Log2Operand = DAG.getNode(ISD::FLOG2, SL, VT, Operand); in LowerFLOG()
2356 SDValue Log2BaseInvertedOperand = DAG.getConstantFP(Log2BaseInverted, SL, VT); in LowerFLOG()
2358 return DAG.getNode(ISD::FMUL, SL, VT, Log2Operand, Log2BaseInvertedOperand); in LowerFLOG()
2364 SDLoc SL(Op); in lowerFEXP() local
2367 const SDValue K = DAG.getConstantFP(numbers::log2e, SL, VT); in lowerFEXP()
2368 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Src, K, Op->getFlags()); in lowerFEXP()
2369 return DAG.getNode(ISD::FEXP2, SL, VT, Mul, Op->getFlags()); in lowerFEXP()
2381 SDLoc SL(Op); in LowerCTLZ_CTTZ() local
2398 return DAG.getNode(NewOpc, SL, MVT::i32, Src); in LowerCTLZ_CTTZ()
2400 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src); in LowerCTLZ_CTTZ()
2402 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in LowerCTLZ_CTTZ()
2403 const SDValue One = DAG.getConstant(1, SL, MVT::i32); in LowerCTLZ_CTTZ()
2405 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in LowerCTLZ_CTTZ()
2406 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in LowerCTLZ_CTTZ()
2412 SDValue Hi0orLo0 = DAG.getSetCC(SL, SetCCVT, HiOrLo, Zero, ISD::SETEQ); in LowerCTLZ_CTTZ()
2414 SDValue OprLo = DAG.getNode(ISDOpc, SL, MVT::i32, Lo); in LowerCTLZ_CTTZ()
2415 SDValue OprHi = DAG.getNode(ISDOpc, SL, MVT::i32, Hi); in LowerCTLZ_CTTZ()
2417 const SDValue Bits32 = DAG.getConstant(32, SL, MVT::i32); in LowerCTLZ_CTTZ()
2420 Add = DAG.getNode(ISD::ADD, SL, MVT::i32, OprLo, Bits32); in LowerCTLZ_CTTZ()
2422 NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0orLo0, Add, OprHi); in LowerCTLZ_CTTZ()
2424 Add = DAG.getNode(ISD::ADD, SL, MVT::i32, OprHi, Bits32); in LowerCTLZ_CTTZ()
2426 NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0orLo0, Add, OprLo); in LowerCTLZ_CTTZ()
2435 SDValue Lo0OrHi0 = DAG.getSetCC(SL, SetCCVT, LoOrHi, Zero, ISD::SETEQ); in LowerCTLZ_CTTZ()
2436 SDValue SrcIsZero = DAG.getNode(ISD::AND, SL, SetCCVT, Lo0OrHi0, Hi0orLo0); in LowerCTLZ_CTTZ()
2443 const SDValue Bits32 = DAG.getConstant(64, SL, MVT::i32); in LowerCTLZ_CTTZ()
2447 NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, in LowerCTLZ_CTTZ()
2451 return DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i64, NewOpr); in LowerCTLZ_CTTZ()
2475 SDLoc SL(Op); in LowerINT_TO_FP32() local
2481 const SDValue SignBit = DAG.getConstant(63, SL, MVT::i64); in LowerINT_TO_FP32()
2482 S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit); in LowerINT_TO_FP32()
2484 SDValue LPlusS = DAG.getNode(ISD::ADD, SL, MVT::i64, L, S); in LowerINT_TO_FP32()
2485 L = DAG.getNode(ISD::XOR, SL, MVT::i64, LPlusS, S); in LowerINT_TO_FP32()
2492 SDValue ZeroI32 = DAG.getConstant(0, SL, MVT::i32); in LowerINT_TO_FP32()
2493 SDValue ZeroI64 = DAG.getConstant(0, SL, MVT::i64); in LowerINT_TO_FP32()
2494 SDValue LZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i64, L); in LowerINT_TO_FP32()
2495 LZ = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LZ); in LowerINT_TO_FP32()
2497 SDValue K = DAG.getConstant(127U + 63U, SL, MVT::i32); in LowerINT_TO_FP32()
2498 SDValue E = DAG.getSelect(SL, MVT::i32, in LowerINT_TO_FP32()
2499 DAG.getSetCC(SL, SetCCVT, L, ZeroI64, ISD::SETNE), in LowerINT_TO_FP32()
2500 DAG.getNode(ISD::SUB, SL, MVT::i32, K, LZ), in LowerINT_TO_FP32()
2503 SDValue U = DAG.getNode(ISD::AND, SL, MVT::i64, in LowerINT_TO_FP32()
2504 DAG.getNode(ISD::SHL, SL, MVT::i64, L, LZ), in LowerINT_TO_FP32()
2505 DAG.getConstant((-1ULL) >> 1, SL, MVT::i64)); in LowerINT_TO_FP32()
2507 SDValue T = DAG.getNode(ISD::AND, SL, MVT::i64, U, in LowerINT_TO_FP32()
2508 DAG.getConstant(0xffffffffffULL, SL, MVT::i64)); in LowerINT_TO_FP32()
2510 SDValue UShl = DAG.getNode(ISD::SRL, SL, MVT::i64, in LowerINT_TO_FP32()
2511 U, DAG.getConstant(40, SL, MVT::i64)); in LowerINT_TO_FP32()
2513 SDValue V = DAG.getNode(ISD::OR, SL, MVT::i32, in LowerINT_TO_FP32()
2514 DAG.getNode(ISD::SHL, SL, MVT::i32, E, DAG.getConstant(23, SL, MVT::i32)), in LowerINT_TO_FP32()
2515 DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, UShl)); in LowerINT_TO_FP32()
2517 SDValue C = DAG.getConstant(0x8000000000ULL, SL, MVT::i64); in LowerINT_TO_FP32()
2518 SDValue RCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETUGT); in LowerINT_TO_FP32()
2519 SDValue TCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETEQ); in LowerINT_TO_FP32()
2521 SDValue One = DAG.getConstant(1, SL, MVT::i32); in LowerINT_TO_FP32()
2523 SDValue VTrunc1 = DAG.getNode(ISD::AND, SL, MVT::i32, V, One); in LowerINT_TO_FP32()
2525 SDValue R = DAG.getSelect(SL, MVT::i32, in LowerINT_TO_FP32()
2528 DAG.getSelect(SL, MVT::i32, TCmp, VTrunc1, ZeroI32)); in LowerINT_TO_FP32()
2529 R = DAG.getNode(ISD::ADD, SL, MVT::i32, V, R); in LowerINT_TO_FP32()
2530 R = DAG.getNode(ISD::BITCAST, SL, MVT::f32, R); in LowerINT_TO_FP32()
2535 SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R); in LowerINT_TO_FP32()
2536 return DAG.getSelect(SL, MVT::f32, DAG.getSExtOrTrunc(S, SL, SetCCVT), RNeg, R); in LowerINT_TO_FP32()
2541 SDLoc SL(Op); in LowerINT_TO_FP64() local
2544 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src); in LowerINT_TO_FP64()
2546 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, in LowerINT_TO_FP64()
2547 DAG.getConstant(0, SL, MVT::i32)); in LowerINT_TO_FP64()
2548 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, in LowerINT_TO_FP64()
2549 DAG.getConstant(1, SL, MVT::i32)); in LowerINT_TO_FP64()
2552 SL, MVT::f64, Hi); in LowerINT_TO_FP64()
2554 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo); in LowerINT_TO_FP64()
2556 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi, in LowerINT_TO_FP64()
2557 DAG.getConstant(32, SL, MVT::i32)); in LowerINT_TO_FP64()
2559 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo); in LowerINT_TO_FP64()
2641 SDLoc SL(Op); in LowerFP_TO_INT64() local
2657 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, SrcVT, Src); in LowerFP_TO_INT64()
2665 Sign = DAG.getNode(ISD::SRA, SL, MVT::i32, in LowerFP_TO_INT64()
2666 DAG.getNode(ISD::BITCAST, SL, MVT::i32, Trunc), in LowerFP_TO_INT64()
2667 DAG.getConstant(31, SL, MVT::i32)); in LowerFP_TO_INT64()
2668 Trunc = DAG.getNode(ISD::FABS, SL, SrcVT, Trunc); in LowerFP_TO_INT64()
2674 SL, SrcVT); in LowerFP_TO_INT64()
2676 SL, SrcVT); in LowerFP_TO_INT64()
2678 K0 = DAG.getConstantFP(BitsToFloat(UINT32_C(/*2^-32*/ 0x2f800000)), SL, in LowerFP_TO_INT64()
2680 K1 = DAG.getConstantFP(BitsToFloat(UINT32_C(/*-2^32*/ 0xcf800000)), SL, in LowerFP_TO_INT64()
2684 SDValue Mul = DAG.getNode(ISD::FMUL, SL, SrcVT, Trunc, K0); in LowerFP_TO_INT64()
2686 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, SrcVT, Mul); in LowerFP_TO_INT64()
2688 SDValue Fma = DAG.getNode(ISD::FMA, SL, SrcVT, FloorMul, K1, Trunc); in LowerFP_TO_INT64()
2692 SL, MVT::i32, FloorMul); in LowerFP_TO_INT64()
2693 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma); in LowerFP_TO_INT64()
2695 SDValue Result = DAG.getNode(ISD::BITCAST, SL, MVT::i64, in LowerFP_TO_INT64()
2696 DAG.getBuildVector(MVT::v2i32, SL, {Lo, Hi})); in LowerFP_TO_INT64()
2701 Sign = DAG.getNode(ISD::BITCAST, SL, MVT::i64, in LowerFP_TO_INT64()
2702 DAG.getBuildVector(MVT::v2i32, SL, {Sign, Sign})); in LowerFP_TO_INT64()
2705 DAG.getNode(ISD::SUB, SL, MVT::i64, in LowerFP_TO_INT64()
2706 DAG.getNode(ISD::XOR, SL, MVT::i64, Result, Sign), Sign); in LowerFP_TO_INT64()
2974 SDLoc SL(N); in performLoadCombine() local
3009 = DAG.getLoad(NewVT, SL, LN->getChain(), in performLoadCombine()
3012 SDValue BC = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad); in performLoadCombine()
3031 SDLoc SL(N); in performStoreCombine() local
3063 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NewVT, Val); in performStoreCombine()
3065 SDValue CastBack = DAG.getNode(ISD::BITCAST, SL, VT, CastVal); in performStoreCombine()
3069 return DAG.getStore(SN->getChain(), SL, CastVal, in performStoreCombine()
3086 SDLoc SL(N); in performAssertSZExtCombine() local
3091 SDValue NewInReg = DAG.getNode(N->getOpcode(), SL, SrcVT, Src, N1); in performAssertSZExtCombine()
3092 return DAG.getNode(ISD::TRUNCATE, SL, N->getValueType(0), NewInReg); in performAssertSZExtCombine()
3124 DAGCombinerInfo &DCI, const SDLoc &SL, in splitBinaryBitConstantOpImpl() argument
3131 SDValue LoRHS = DAG.getConstant(ValLo, SL, MVT::i32); in splitBinaryBitConstantOpImpl()
3132 SDValue HiRHS = DAG.getConstant(ValHi, SL, MVT::i32); in splitBinaryBitConstantOpImpl()
3134 SDValue LoAnd = DAG.getNode(Opc, SL, MVT::i32, Lo, LoRHS); in splitBinaryBitConstantOpImpl()
3135 SDValue HiAnd = DAG.getNode(Opc, SL, MVT::i32, Hi, HiRHS); in splitBinaryBitConstantOpImpl()
3142 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {LoAnd, HiAnd}); in splitBinaryBitConstantOpImpl()
3143 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec); in splitBinaryBitConstantOpImpl()
3159 SDLoc SL(N); in performShlCombine() local
3174 SDValue Vec = DAG.getBuildVector(MVT::v2i16, SL, in performShlCombine()
3175 { DAG.getConstant(0, SL, MVT::i16), LHS->getOperand(0) }); in performShlCombine()
3176 return DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec); in performShlCombine()
3187 SDValue Shl = DAG.getNode(ISD::SHL, SL, XVT, X, SDValue(RHS, 0)); in performShlCombine()
3188 return DAG.getZExtOrTrunc(Shl, SL, VT); in performShlCombine()
3203 SDValue ShiftAmt = DAG.getConstant(RHSVal - 32, SL, MVT::i32); in performShlCombine()
3205 SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS); in performShlCombine()
3206 SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt); in performShlCombine()
3208 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in performShlCombine()
3210 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {Zero, NewShift}); in performShlCombine()
3211 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec); in performShlCombine()
3224 SDLoc SL(N); in performSraCombine() local
3230 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine()
3231 DAG.getConstant(31, SL, MVT::i32)); in performSraCombine()
3233 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {Hi, NewShift}); in performSraCombine()
3234 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec); in performSraCombine()
3240 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine()
3241 DAG.getConstant(31, SL, MVT::i32)); in performSraCombine()
3242 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, NewShift}); in performSraCombine()
3243 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec); in performSraCombine()
3259 SDLoc SL(N); in performSrlCombine() local
3268 ISD::AND, SL, VT, in performSrlCombine()
3269 DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(0), N->getOperand(1)), in performSrlCombine()
3270 DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(1), N->getOperand(1))); in performSrlCombine()
3284 SDValue One = DAG.getConstant(1, SL, MVT::i32); in performSrlCombine()
3285 SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in performSrlCombine()
3287 SDValue VecOp = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, LHS); in performSrlCombine()
3288 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecOp, One); in performSrlCombine()
3290 SDValue NewConst = DAG.getConstant(ShiftAmt - 32, SL, MVT::i32); in performSrlCombine()
3291 SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst); in performSrlCombine()
3293 SDValue BuildPair = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, Zero}); in performSrlCombine()
3295 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildPair); in performSrlCombine()
3300 SDLoc SL(N); in performTruncateCombine() local
3313 Elt0 = DAG.getNode(ISD::BITCAST, SL, in performTruncateCombine()
3317 return DAG.getNode(ISD::TRUNCATE, SL, VT, Elt0); in performTruncateCombine()
3334 SrcElt = DAG.getNode(ISD::BITCAST, SL, in performTruncateCombine()
3338 return DAG.getNode(ISD::TRUNCATE, SL, VT, SrcElt); in performTruncateCombine()
3364 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MidVT, in performTruncateCombine()
3369 Amt = DAG.getZExtOrTrunc(Amt, SL, NewShiftVT); in performTruncateCombine()
3373 SDValue ShrunkShift = DAG.getNode(Src.getOpcode(), SL, MidVT, in performTruncateCombine()
3375 return DAG.getNode(ISD::TRUNCATE, SL, VT, ShrunkShift); in performTruncateCombine()
3387 static SDValue getMul24(SelectionDAG &DAG, const SDLoc &SL, in getMul24() argument
3391 return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1); in getMul24()
3397 SDValue MulLo = DAG.getNode(MulLoOpc, SL, MVT::i32, N0, N1); in getMul24()
3398 SDValue MulHi = DAG.getNode(MulHiOpc, SL, MVT::i32, N0, N1); in getMul24()
3400 return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64, MulLo, MulHi); in getMul24()
3556 SDValue AMDGPUTargetLowering::performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, in performCtlz_CttzCombine() argument
3574 return getFFBX_U32(DAG, CmpLHS, SL, Opc); in performCtlz_CttzCombine()
3585 return getFFBX_U32(DAG, CmpLHS, SL, Opc); in performCtlz_CttzCombine()
3593 const SDLoc &SL, in distributeOpThroughSelect() argument
3600 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT, Cond, in distributeOpThroughSelect()
3603 return DAG.getNode(Op, SL, VT, NewSelect); in distributeOpThroughSelect()
3636 SDLoc SL(N); in foldFreeOpFromSelect() local
3655 NewRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in foldFreeOpFromSelect()
3662 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT, in foldFreeOpFromSelect()
3665 return DAG.getNode(LHS.getOpcode(), SL, VT, NewSelect); in foldFreeOpFromSelect()
3698 SDLoc SL(N); in performSelectCombine() local
3702 SDValue NewCond = DAG.getSetCC(SL, Cond.getValueType(), LHS, RHS, NewCC); in performSelectCombine()
3703 return DAG.getNode(ISD::SELECT, SL, VT, NewCond, False, True); in performSelectCombine()
3785 SDLoc SL(N); in performFNegCombine() local
3796 LHS = DAG.getNode(ISD::FNEG, SL, VT, LHS); in performFNegCombine()
3801 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
3805 SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags()); in performFNegCombine()
3809 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
3824 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
3826 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, RHS, N0->getFlags()); in performFNegCombine()
3830 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
3849 MHS = DAG.getNode(ISD::FNEG, SL, VT, MHS); in performFNegCombine()
3852 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
3856 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, MHS, RHS); in performFNegCombine()
3860 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
3882 SDValue NegLHS = DAG.getNode(ISD::FNEG, SL, VT, LHS); in performFNegCombine()
3883 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
3886 SDValue Res = DAG.getNode(Opposite, SL, VT, NegLHS, NegRHS, N0->getFlags()); in performFNegCombine()
3890 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
3896 Ops[I] = DAG.getNode(ISD::FNEG, SL, VT, N0->getOperand(I), N0->getFlags()); in performFNegCombine()
3898 SDValue Res = DAG.getNode(AMDGPUISD::FMED3, SL, VT, Ops, N0->getFlags()); in performFNegCombine()
3903 SDValue Neg = DAG.getNode(ISD::FNEG, SL, VT, Res); in performFNegCombine()
3926 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0)); in performFNegCombine()
3934 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
3935 return DAG.getNode(Opc, SL, VT, Neg, N0->getFlags()); in performFNegCombine()
3942 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
3950 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
3951 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
3957 SDLoc SL(N); in performFNegCombine() local
3963 SDValue IntFNeg = DAG.getNode(ISD::XOR, SL, SrcVT, Src, in performFNegCombine()
3964 DAG.getConstant(0x8000, SL, SrcVT)); in performFNegCombine()
3965 return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFNeg); in performFNegCombine()
3983 SDLoc SL(N); in performFAbsCombine() local
3988 SDValue IntFAbs = DAG.getNode(ISD::AND, SL, SrcVT, Src, in performFAbsCombine()
3989 DAG.getConstant(0x7fff, SL, SrcVT)); in performFAbsCombine()
3990 return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFAbs); in performFAbsCombine()
4035 SDLoc SL(N); in PerformDAGCombine() local
4041 return DAG.getBuildVector(DestVT, SL, CastedElts); in PerformDAGCombine()
4055 SDLoc SL(N); in PerformDAGCombine() local
4057 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, in PerformDAGCombine()
4058 DAG.getConstant(Lo_32(CVal), SL, MVT::i32), in PerformDAGCombine()
4059 DAG.getConstant(Hi_32(CVal), SL, MVT::i32)); in PerformDAGCombine()
4060 return DAG.getNode(ISD::BITCAST, SL, DestVT, BV); in PerformDAGCombine()
4065 SDLoc SL(N); in PerformDAGCombine() local
4067 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, in PerformDAGCombine()
4068 DAG.getConstant(Lo_32(CVal), SL, MVT::i32), in PerformDAGCombine()
4069 DAG.getConstant(Hi_32(CVal), SL, MVT::i32)); in PerformDAGCombine()
4071 return DAG.getNode(ISD::BITCAST, SL, DestVT, Vec); in PerformDAGCombine()
4220 const SDLoc &SL, in CreateLiveInRegister() argument
4236 return DAG.getCopyFromReg(DAG.getEntryNode(), SL, VReg, VT); in CreateLiveInRegister()
4255 const SDLoc &SL, in loadStackInputValue() argument
4264 return DAG.getLoad(VT, SL, DAG.getEntryNode(), Ptr, SrcPtrInfo, Align(4), in loadStackInputValue()
4270 const SDLoc &SL, in storeStackInputValue() argument
4278 SDValue Ptr = DAG.getConstant(Offset, SL, MVT::i32); in storeStackInputValue()
4281 DAG.getCopyFromReg(Chain, SL, Info->getStackPtrOffsetReg(), MVT::i32); in storeStackInputValue()
4282 Ptr = DAG.getNode(ISD::ADD, SL, MVT::i32, SP, Ptr); in storeStackInputValue()
4283 SDValue Store = DAG.getStore(Chain, SL, ArgVal, Ptr, DstInfo, Align(4), in storeStackInputValue()
4290 EVT VT, const SDLoc &SL, in loadInputValue() argument
4295 CreateLiveInRegister(DAG, RC, Arg.getRegister(), VT, SL) : in loadInputValue()
4296 loadStackInputValue(DAG, VT, SL, Arg.getStackOffset()); in loadInputValue()
4303 V = DAG.getNode(ISD::SRL, SL, VT, V, in loadInputValue()
4304 DAG.getShiftAmountConstant(Shift, VT, SL)); in loadInputValue()
4305 return DAG.getNode(ISD::AND, SL, VT, V, in loadInputValue()
4306 DAG.getConstant(Mask >> Shift, SL, VT)); in loadInputValue()