397 #define BCase(X) IO.bitSetCase(Value, #X, ELF::X)  in bitset()  macro
401     BCase(EF_ARM_SOFT_FLOAT);  in bitset()
402     BCase(EF_ARM_VFP_FLOAT);  in bitset()
411     BCase(EF_MIPS_NOREORDER);  in bitset()
412     BCase(EF_MIPS_PIC);  in bitset()
413     BCase(EF_MIPS_CPIC);  in bitset()
414     BCase(EF_MIPS_ABI2);  in bitset()
415     BCase(EF_MIPS_32BITMODE);  in bitset()
416     BCase(EF_MIPS_FP64);  in bitset()
417     BCase(EF_MIPS_NAN2008);  in bitset()
418     BCase(EF_MIPS_MICROMIPS);  in bitset()
419     BCase(EF_MIPS_ARCH_ASE_M16);  in bitset()
420     BCase(EF_MIPS_ARCH_ASE_MDMX);  in bitset()
456     BCase(EF_HEXAGON_MACH_V2);  in bitset()
457     BCase(EF_HEXAGON_MACH_V3);  in bitset()
458     BCase(EF_HEXAGON_MACH_V4);  in bitset()
459     BCase(EF_HEXAGON_MACH_V5);  in bitset()
460     BCase(EF_HEXAGON_MACH_V55);  in bitset()
461     BCase(EF_HEXAGON_MACH_V60);  in bitset()
462     BCase(EF_HEXAGON_MACH_V62);  in bitset()
463     BCase(EF_HEXAGON_MACH_V65);  in bitset()
464     BCase(EF_HEXAGON_MACH_V66);  in bitset()
465     BCase(EF_HEXAGON_MACH_V67);  in bitset()
466     BCase(EF_HEXAGON_MACH_V67T);  in bitset()
467     BCase(EF_HEXAGON_MACH_V68);  in bitset()
468     BCase(EF_HEXAGON_ISA_V2);  in bitset()
469     BCase(EF_HEXAGON_ISA_V3);  in bitset()
470     BCase(EF_HEXAGON_ISA_V4);  in bitset()
471     BCase(EF_HEXAGON_ISA_V5);  in bitset()
472     BCase(EF_HEXAGON_ISA_V55);  in bitset()
473     BCase(EF_HEXAGON_ISA_V60);  in bitset()
474     BCase(EF_HEXAGON_ISA_V62);  in bitset()
475     BCase(EF_HEXAGON_ISA_V65);  in bitset()
476     BCase(EF_HEXAGON_ISA_V66);  in bitset()
477     BCase(EF_HEXAGON_ISA_V67);  in bitset()
478     BCase(EF_HEXAGON_ISA_V68);  in bitset()
499     BCase(EF_AVR_LINKRELAX_PREPARED);  in bitset()
502     BCase(EF_RISCV_RVC);  in bitset()
507     BCase(EF_RISCV_RVE);  in bitset()
564       BCase(EF_AMDGPU_FEATURE_XNACK_V3);  in bitset()
565       BCase(EF_AMDGPU_FEATURE_SRAMECC_V3);  in bitset()
590 #undef BCase  in bitset()
668 #define BCase(X) IO.bitSetCase(Value, #X, ELF::X)  in bitset()  macro
669   BCase(PF_X);  in bitset()
670   BCase(PF_W);  in bitset()
671   BCase(PF_R);  in bitset()
677 #define BCase(X) IO.bitSetCase(Value, #X, ELF::X)  in bitset()  macro
678   BCase(SHF_WRITE);  in bitset()
679   BCase(SHF_ALLOC);  in bitset()
680   BCase(SHF_EXCLUDE);  in bitset()
681   BCase(SHF_EXECINSTR);  in bitset()
682   BCase(SHF_MERGE);  in bitset()
683   BCase(SHF_STRINGS);  in bitset()
684   BCase(SHF_INFO_LINK);  in bitset()
685   BCase(SHF_LINK_ORDER);  in bitset()
686   BCase(SHF_OS_NONCONFORMING);  in bitset()
687   BCase(SHF_GROUP);  in bitset()
688   BCase(SHF_TLS);  in bitset()
689   BCase(SHF_COMPRESSED);  in bitset()
690   BCase(SHF_GNU_RETAIN);  in bitset()
693     BCase(SHF_ARM_PURECODE);  in bitset()
696     BCase(SHF_HEX_GPREL);  in bitset()
699     BCase(SHF_MIPS_NODUPES);  in bitset()
700     BCase(SHF_MIPS_NAMES);  in bitset()
701     BCase(SHF_MIPS_LOCAL);  in bitset()
702     BCase(SHF_MIPS_NOSTRIP);  in bitset()
703     BCase(SHF_MIPS_GPREL);  in bitset()
704     BCase(SHF_MIPS_MERGE);  in bitset()
705     BCase(SHF_MIPS_ADDR);  in bitset()
706     BCase(SHF_MIPS_STRING);  in bitset()
709     BCase(SHF_X86_64_LARGE);  in bitset()
715 #undef BCase  in bitset()
970 #define BCase(X) IO.bitSetCase(Value, #X, Mips::AFL_ASE_##X)  in bitset()  macro
971   BCase(DSP);  in bitset()
972   BCase(DSPR2);  in bitset()
973   BCase(EVA);  in bitset()
974   BCase(MCU);  in bitset()
975   BCase(MDMX);  in bitset()
976   BCase(MIPS3D);  in bitset()
977   BCase(MT);  in bitset()
978   BCase(SMARTMIPS);  in bitset()
979   BCase(VIRT);  in bitset()
980   BCase(MSA);  in bitset()
981   BCase(MIPS16);  in bitset()
982   BCase(MICROMIPS);  in bitset()
983   BCase(XPA);  in bitset()
984   BCase(CRC);  in bitset()
985   BCase(GINV);  in bitset()
986 #undef BCase  in bitset()
991 #define BCase(X) IO.bitSetCase(Value, #X, Mips::AFL_FLAGS1_##X)  in bitset()  macro
992   BCase(ODDSPREG);  in bitset()
993 #undef BCase  in bitset()