Lines Matching refs:MONum
216 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
224 void report(const char *msg, const MachineOperand *MO, unsigned MONum,
242 void checkLiveness(const MachineOperand *MO, unsigned MONum);
243 void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
247 void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
496 unsigned MONum, LLT MOVRegType) { in report() argument
499 errs() << "- operand " << MONum << ": "; in report()
1802 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) { in visitMachineOperand() argument
1807 NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0; in visitMachineOperand()
1810 if (MONum < NumDefs) { in visitMachineOperand()
1811 const MCOperandInfo &MCOI = MCID.OpInfo[MONum]; in visitMachineOperand()
1813 report("Explicit definition must be a register", MO, MONum); in visitMachineOperand()
1815 report("Explicit definition marked as use", MO, MONum); in visitMachineOperand()
1817 report("Explicit definition marked as implicit", MO, MONum); in visitMachineOperand()
1818 } else if (MONum < MCID.getNumOperands()) { in visitMachineOperand()
1819 const MCOperandInfo &MCOI = MCID.OpInfo[MONum]; in visitMachineOperand()
1822 bool IsOptional = MI->isVariadic() && MONum == MCID.getNumOperands() - 1; in visitMachineOperand()
1826 report("Explicit operand marked as def", MO, MONum); in visitMachineOperand()
1828 report("Explicit operand marked as implicit", MO, MONum); in visitMachineOperand()
1834 report("Expected a register operand.", MO, MONum); in visitMachineOperand()
1839 report("Expected a non-register operand.", MO, MONum); in visitMachineOperand()
1843 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO); in visitMachineOperand()
1846 report("Tied use must be a register", MO, MONum); in visitMachineOperand()
1848 report("Operand should be tied", MO, MONum); in visitMachineOperand()
1849 else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum)) in visitMachineOperand()
1850 report("Tied def doesn't match MCInstrDesc", MO, MONum); in visitMachineOperand()
1860 report("Explicit operand should not be tied", MO, MONum); in visitMachineOperand()
1864 report("Extra explicit operand on non-variadic instruction", MO, MONum); in visitMachineOperand()
1873 checkLiveness(MO, MONum); in visitMachineOperand()
1877 unsigned OtherIdx = MI->findTiedOperandIdx(MONum); in visitMachineOperand()
1880 report("Must be tied to a register", MO, MONum); in visitMachineOperand()
1882 report("Missing tie flags on tied operand", MO, MONum); in visitMachineOperand()
1883 if (MI->findTiedOperandIdx(OtherIdx) != MONum) in visitMachineOperand()
1884 report("Inconsistent tie links", MO, MONum); in visitMachineOperand()
1885 if (MONum < MCID.getNumDefs()) { in visitMachineOperand()
1889 MO, MONum); in visitMachineOperand()
1892 report("Explicit def should be tied to implicit use", MO, MONum); in visitMachineOperand()
1907 MO->isUse() && MI->isRegTiedToDefOperand(MONum, &DefIdx) && in visitMachineOperand()
1909 report("Two-address instruction operands must be identical", MO, MONum); in visitMachineOperand()
1916 report("Illegal subregister index for physical register", MO, MONum); in visitMachineOperand()
1919 if (MONum < MCID.getNumOperands()) { in visitMachineOperand()
1921 TII->getRegClass(MCID, MONum, TRI, *MF)) { in visitMachineOperand()
1923 report("Illegal physical register for instruction", MO, MONum); in visitMachineOperand()
1931 report("isRenamable set on reserved register", MO, MONum); in visitMachineOperand()
1936 report("Use-reg is not IsDebug in a DBG_VALUE", MO, MONum); in visitMachineOperand()
1952 report("Generic virtual register use cannot be undef", MO, MONum); in visitMachineOperand()
1957 MO, MONum); in visitMachineOperand()
1965 MONum); in visitMachineOperand()
1975 MO, MONum); in visitMachineOperand()
1983 MONum); in visitMachineOperand()
1991 MONum); in visitMachineOperand()
1999 MONum < MCID.getNumOperands() && in visitMachineOperand()
2000 TII->getRegClass(MCID, MONum, TRI, *MF)) { in visitMachineOperand()
2002 MONum); in visitMachineOperand()
2005 TII->getRegClass(MCID, MONum, TRI, *MF)) in visitMachineOperand()
2016 report("Invalid subregister index for virtual register", MO, MONum); in visitMachineOperand()
2022 report("Invalid register class for subregister index", MO, MONum); in visitMachineOperand()
2028 if (MONum < MCID.getNumOperands()) { in visitMachineOperand()
2030 TII->getRegClass(MCID, MONum, TRI, *MF)) { in visitMachineOperand()
2035 report("No largest legal super class exists.", MO, MONum); in visitMachineOperand()
2040 report("No matching super-reg register class.", MO, MONum); in visitMachineOperand()
2045 report("Illegal virtual register for instruction", MO, MONum); in visitMachineOperand()
2062 report("PHI operand is not in the CFG", MO, MONum); in visitMachineOperand()
2096 report("Instruction loads from dead spill slot", MO, MONum); in visitMachineOperand()
2100 report("Instruction stores to dead spill slot", MO, MONum); in visitMachineOperand()
2112 unsigned MONum, SlotIndex UseIdx, in checkLivenessAtUse() argument
2120 report("No live segment at use", MO, MONum); in checkLivenessAtUse()
2126 report("Live range continues after kill flag", MO, MONum); in checkLivenessAtUse()
2136 unsigned MONum, SlotIndex DefIdx, in checkLivenessAtDef() argument
2144 report("Inconsistent valno->def", MO, MONum); in checkLivenessAtDef()
2153 report("No live segment at def", MO, MONum); in checkLivenessAtDef()
2172 report("Live range continues after dead def flag", MO, MONum); in checkLivenessAtDef()
2182 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) { in checkLiveness() argument
2195 report("Kill missing from LiveVariables", MO, MONum); in checkLiveness()
2208 checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units); in checkLiveness()
2216 checkLivenessAtUse(MO, MONum, UseIdx, LI, Reg); in checkLiveness()
2227 checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask); in checkLiveness()
2234 report("No live subrange at use", MO, MONum); in checkLiveness()
2240 report("Virtual register has no live interval", MO, MONum); in checkLiveness()
2277 report("Using an undefined physical register", MO, MONum); in checkLiveness()
2279 report("Reading virtual register without a def", MO, MONum); in checkLiveness()
2286 report("Using a killed virtual register", MO, MONum); in checkLiveness()
2304 report("Multiple virtual register defs in SSA form", MO, MONum); in checkLiveness()
2314 checkLivenessAtDef(MO, MONum, DefIdx, LI, Reg); in checkLiveness()
2324 checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg, true, SR.LaneMask); in checkLiveness()
2328 report("Virtual register has no Live interval", MO, MONum); in checkLiveness()