Lines Matching defs:val
54 #define VXGE_HAL_G3FBCT_CONFIG0_RD_CMD_LATENCY_RPATH(val) vBIT(val, 5, 3) argument
55 #define VXGE_HAL_G3FBCT_CONFIG0_RD_CMD_LATENCY(val) vBIT(val, 13, 3) argument
56 #define VXGE_HAL_G3FBCT_CONFIG0_REFRESH_PER(val) vBIT(val, 16, 16) argument
57 #define VXGE_HAL_G3FBCT_CONFIG0_TRC(val) vBIT(val, 35, 5) argument
58 #define VXGE_HAL_G3FBCT_CONFIG0_TRRD(val) vBIT(val, 44, 4) argument
59 #define VXGE_HAL_G3FBCT_CONFIG0_TFAW(val) vBIT(val, 50, 6) argument
60 #define VXGE_HAL_G3FBCT_CONFIG0_RD_FIFO_THR(val) vBIT(val, 58, 6) argument
62 #define VXGE_HAL_G3FBCT_CONFIG1_BIC_THR(val) vBIT(val, 3, 5) argument
65 #define VXGE_HAL_G3FBCT_CONFIG1_RD_SAMPLING(val) vBIT(val, 29, 3) argument
67 #define VXGE_HAL_G3FBCT_CONFIG1_BIC_HI_THR(val) vBIT(val, 43, 5) argument
68 #define VXGE_HAL_G3FBCT_CONFIG1_BIC_MODE(val) vBIT(val, 54, 2) argument
69 #define VXGE_HAL_G3FBCT_CONFIG1_ECC_ENABLE(val) vBIT(val, 57, 7) argument
71 #define VXGE_HAL_G3FBCT_CONFIG2_DEV_USE_ENABLE(val) vBIT(val, 6, 2) argument
72 #define VXGE_HAL_G3FBCT_CONFIG2_DEV_USE_VALUE(val) vBIT(val, 9, 7) argument
73 #define VXGE_HAL_G3FBCT_CONFIG2_ARBITER_CTRL(val) vBIT(val, 22, 2) argument
76 #define VXGE_HAL_G3FBCT_CONFIG2_LAST_CADD(val) vBIT(val, 43, 13) argument
78 #define VXGE_HAL_G3FBCT_INIT0_MRS_BAD(val) vBIT(val, 5, 3) argument
79 #define VXGE_HAL_G3FBCT_INIT0_MRS_WL(val) vBIT(val, 13, 3) argument
82 #define VXGE_HAL_G3FBCT_INIT0_MRS_CL(val) vBIT(val, 44, 4) argument
84 #define VXGE_HAL_G3FBCT_INIT0_MRS_BL(val) vBIT(val, 62, 2) argument
86 #define VXGE_HAL_G3FBCT_INIT1_EMRS_BAD(val) vBIT(val, 5, 3) argument
91 #define VXGE_HAL_G3FBCT_INIT1_EMRS_TWR(val) vBIT(val, 53, 3) argument
92 #define VXGE_HAL_G3FBCT_INIT1_EMRS_DQ_TER(val) vBIT(val, 62, 2) argument
94 #define VXGE_HAL_G3FBCT_INIT2_EMRS_DR_STR(val) vBIT(val, 6, 2) argument
96 #define VXGE_HAL_G3FBCT_INIT2_POWER_UP_DELAY(val) vBIT(val, 16, 24) argument
97 #define VXGE_HAL_G3FBCT_INIT2_ACTIVE_CMD_DELAY(val) vBIT(val, 40, 24) argument
99 #define VXGE_HAL_G3FBCT_INIT3_TRP_DELAY(val) vBIT(val, 0, 8) argument
100 #define VXGE_HAL_G3FBCT_INIT3_TMRD_DELAY(val) vBIT(val, 8, 8) argument
101 #define VXGE_HAL_G3FBCT_INIT3_TWR2PRE_DELAY(val) vBIT(val, 16, 8) argument
102 #define VXGE_HAL_G3FBCT_INIT3_TRD2PRE_DELAY(val) vBIT(val, 24, 8) argument
103 #define VXGE_HAL_G3FBCT_INIT3_TRCDR_DELAY(val) vBIT(val, 32, 8) argument
104 #define VXGE_HAL_G3FBCT_INIT3_TRCDW_DELAY(val) vBIT(val, 40, 8) argument
105 #define VXGE_HAL_G3FBCT_INIT3_TWR2RD_DELAY(val) vBIT(val, 48, 8) argument
106 #define VXGE_HAL_G3FBCT_INIT3_TRD2WR_DELAY(val) vBIT(val, 56, 8) argument
108 #define VXGE_HAL_G3FBCT_INIT4_TRFC_DELAY(val) vBIT(val, 0, 8) argument
109 #define VXGE_HAL_G3FBCT_INIT4_REFRESH_BURSTS(val) vBIT(val, 12, 4) argument
111 #define VXGE_HAL_G3FBCT_INIT4_VENDOR_ID(val) vBIT(val, 32, 8) argument
112 #define VXGE_HAL_G3FBCT_INIT4_OOO_DEPTH(val) vBIT(val, 42, 6) argument
116 #define VXGE_HAL_G3FBCT_INIT5_TRAS_DELAY(val) vBIT(val, 3, 5) argument
117 #define VXGE_HAL_G3FBCT_INIT5_TVID_DELAY(val) vBIT(val, 8, 8) argument
118 #define VXGE_HAL_G3FBCT_INIT5_TWR_APRE2CMD(val) vBIT(val, 16, 8) argument
119 #define VXGE_HAL_G3FBCT_INIT5_TRD_APRE2CMD(val) vBIT(val, 24, 8) argument
120 #define VXGE_HAL_G3FBCT_INIT5_TWR_APRE2CMD_CON(val) vBIT(val, 32, 8) argument
121 #define VXGE_HAL_G3FBCT_INIT5_GDDR3_DLL_DELAY(val) vBIT(val, 40, 24) argument
123 #define VXGE_HAL_G3FBCT_DLL_TRAINING1_DLL_TRA_DATA00(val) vBIT(val, 0, 64) argument
125 #define VXGE_HAL_G3FBCT_DLL_TRAINING2_DLL_TRA_DATA01(val) vBIT(val, 0, 64) argument
127 #define VXGE_HAL_G3FBCT_DLL_TRAINING3_DLL_TRA_DATA10(val) vBIT(val, 0, 64) argument
129 #define VXGE_HAL_G3FBCT_DLL_TRAINING4_DLL_TRA_DATA11(val) vBIT(val, 0, 64) argument
131 #define VXGE_HAL_G3FBCT_DLL_TRAINING6_DLL_TRA_DATA20(val) vBIT(val, 0, 64) argument
133 #define VXGE_HAL_G3FBCT_DLL_TRAINING7_DLL_TRA_DATA21(val) vBIT(val, 0, 64) argument
135 #define VXGE_HAL_G3FBCT_DLL_TRAINING8_DLL_TRA_DATA30(val) vBIT(val, 0, 64) argument
137 #define VXGE_HAL_G3FBCT_DLL_TRAINING9_DLL_TRA_DATA31(val) vBIT(val, 0, 64) argument
139 #define VXGE_HAL_G3FBCT_DLL_TRAINING5_DLL_TRA_RADD(val) vBIT(val, 2, 14) argument
140 #define VXGE_HAL_G3FBCT_DLL_TRAINING5_DLL_TRA_CADD0(val) vBIT(val, 21, 11) argument
141 #define VXGE_HAL_G3FBCT_DLL_TRAINING5_DLL_TRA_CADD1(val) vBIT(val, 37, 11) argument
143 #define VXGE_HAL_G3FBCT_DLL_TRAINING10_DLL_TP_READS(val) vBIT(val, 4, 4) argument
144 #define VXGE_HAL_G3FBCT_DLL_TRAINING10_DLL_SAMPLES(val) vBIT(val, 8, 8) argument
145 #define VXGE_HAL_G3FBCT_DLL_TRAINING10_TRA_LOOPS(val) vBIT(val, 18, 14) argument
146 #define VXGE_HAL_G3FBCT_DLL_TRAINING10_TRA_PASS_CNT(val) vBIT(val, 33, 7) argument
147 #define VXGE_HAL_G3FBCT_DLL_TRAINING10_TRA_STEP(val) vBIT(val, 41, 7) argument
149 #define VXGE_HAL_G3FBCT_DLL_TRAINING11_ICTRL_DLL_TRA_CNT(val) vBIT(val, 0, 48) argument
150 #define VXGE_HAL_G3FBCT_DLL_TRAINING11_ICTRL_DLL_TRA_DIS(val) vBIT(val, 54, 2) argument
152 #define VXGE_HAL_G3FBCT_INIT6_TWR_APRE2RD_DELAY(val) vBIT(val, 4, 4) argument
153 #define VXGE_HAL_G3FBCT_INIT6_TWR_APRE2WR_DELAY(val) vBIT(val, 12, 4) argument
154 #define VXGE_HAL_G3FBCT_INIT6_TWR_APRE2PRE_DELAY(val) vBIT(val, 20, 4) argument
155 #define VXGE_HAL_G3FBCT_INIT6_TWR_APRE2ACT_DELAY(val) vBIT(val, 28, 4) argument
156 #define VXGE_HAL_G3FBCT_INIT6_TRD_APRE2RD_DELAY(val) vBIT(val, 36, 4) argument
157 #define VXGE_HAL_G3FBCT_INIT6_TRD_APRE2WR_DELAY(val) vBIT(val, 44, 4) argument
158 #define VXGE_HAL_G3FBCT_INIT6_TRD_APRE2PRE_DELAY(val) vBIT(val, 52, 4) argument
159 #define VXGE_HAL_G3FBCT_INIT6_TRD_APRE2ACT_DELAY(val) vBIT(val, 60, 4) argument
161 #define VXGE_HAL_G3FBCT_TEST0_TEST_START_RADD(val) vBIT(val, 2, 14) argument
162 #define VXGE_HAL_G3FBCT_TEST0_TEST_END_RADD(val) vBIT(val, 18, 14) argument
163 #define VXGE_HAL_G3FBCT_TEST0_TEST_START_CADD(val) vBIT(val, 37, 11) argument
164 #define VXGE_HAL_G3FBCT_TEST0_TEST_END_CADD(val) vBIT(val, 53, 11) argument
166 #define VXGE_HAL_G3FBCT_TEST01_TEST_BANK(val) vBIT(val, 0, 8) argument
167 #define VXGE_HAL_G3FBCT_TEST01_TEST_CTRL(val) vBIT(val, 12, 4) argument
171 #define VXGE_HAL_G3FBCT_TEST01_ECC_DEC_TEST_FAIL_CNTR(val) vBIT(val, 40, 16) argument
174 #define VXGE_HAL_G3FBCT_TEST1_TX_TEST_DATA(val) vBIT(val, 0, 64) argument
176 #define VXGE_HAL_G3FBCT_TEST2_TX_TEST_DATA(val) vBIT(val, 0, 64) argument
178 #define VXGE_HAL_G3FBCT_TEST11_TX_TEST_DATA1(val) vBIT(val, 0, 64) argument
180 #define VXGE_HAL_G3FBCT_TEST21_TX_TEST_DATA1(val) vBIT(val, 0, 64) argument
182 #define VXGE_HAL_G3FBCT_TEST3_ECC_DEC_RX_TEST_DATA(val) vBIT(val, 0, 64) argument
184 #define VXGE_HAL_G3FBCT_TEST4_ECC_DEC_RX_TEST_DATA(val) vBIT(val, 0, 64) argument
186 #define VXGE_HAL_G3FBCT_TEST31_ECC_DEC_RX_TEST_DATA1(val) vBIT(val, 0, 64) argument
188 #define VXGE_HAL_G3FBCT_TEST41_ECC_DEC_RX_TEST_DATA1(val) vBIT(val, 0, 64) argument
190 #define VXGE_HAL_G3FBCT_TEST5_ECC_DEC_RX_FAILED_TEST_DATA(val) vBIT(val, 0, 64) argument
192 #define VXGE_HAL_G3FBCT_TEST6_ECC_DEC_RX_FAILED_TEST_DATA(val) vBIT(val, 0, 64) argument
194 #define VXGE_HAL_G3FBCT_TEST51_ECC_DEC_RX_FAILED_TEST_DATA1(val)\ argument
197 #define VXGE_HAL_G3FBCT_TEST61_ECC_DEC_RX_FAILED_TEST_DATA1(val)\ argument
200 #define VXGE_HAL_G3FBCT_TEST7_ECC_DEC_TEST_FAILED_RADD(val) vBIT(val, 0, 14) argument
201 #define VXGE_HAL_G3FBCT_TEST7_ECC_DEC_TEST_FAILED_CADD(val) vBIT(val, 19, 11) argument
202 #define VXGE_HAL_G3FBCT_TEST7_ECC_DEC_TEST_FAILED_BANK(val) vBIT(val, 32, 8) argument
204 #define VXGE_HAL_G3FBCT_TEST71_ECC_DEC_TEST_FAILED_RADD1(val) vBIT(val, 0, 14) argument
205 #define VXGE_HAL_G3FBCT_TEST71_ECC_DEC_TEST_FAILED_CADD1(val) vBIT(val, 19, 11) argument
206 #define VXGE_HAL_G3FBCT_TEST71_ECC_DEC_TEST_FAILED_BANK1(val) vBIT(val, 32, 8) argument
210 #define VXGE_HAL_G3FBCT_LOOP_BACK_TDATA(val) vBIT(val, 0, 32) argument
214 #define VXGE_HAL_G3FBCT_LOOP_BACK_RDLL_IDLE_VAL(val) vBIT(val, 56, 8) argument
216 #define VXGE_HAL_G3FBCT_LOOP_BACK1_RDLL_START_VAL(val) vBIT(val, 1, 7) argument
217 #define VXGE_HAL_G3FBCT_LOOP_BACK1_RDLL_END_VAL(val) vBIT(val, 9, 7) argument
218 #define VXGE_HAL_G3FBCT_LOOP_BACK1_WDLL_IDLE_VAL(val) vBIT(val, 16, 8) argument
219 #define VXGE_HAL_G3FBCT_LOOP_BACK1_WDLL_START_VAL(val) vBIT(val, 25, 7) argument
220 #define VXGE_HAL_G3FBCT_LOOP_BACK1_WDLL_END_VAL(val) vBIT(val, 33, 7) argument
221 #define VXGE_HAL_G3FBCT_LOOP_BACK1_STEPS(val) vBIT(val, 45, 3) argument
222 #define VXGE_HAL_G3FBCT_LOOP_BACK1_RDLL_MIN_FILTER(val) vBIT(val, 49, 7) argument
223 #define VXGE_HAL_G3FBCT_LOOP_BACK1_RDLL_MAX_FILTER(val) vBIT(val, 57, 7) argument
225 #define VXGE_HAL_G3FBCT_LOOP_BACK2_WDLL_MIN_FILTER(val) vBIT(val, 1, 7) argument
226 #define VXGE_HAL_G3FBCT_LOOP_BACK2_WDLL_MAX_FILTER(val) vBIT(val, 9, 7) argument
228 #define VXGE_HAL_G3FBCT_LOOP_BACK3_LBCTRL_CM_RDLL_RESULT(val) vBIT(val, 0, 8) argument
229 #define VXGE_HAL_G3FBCT_LOOP_BACK3_LBCTRL_CM_WDLL_RESULT(val) vBIT(val, 8, 8) argument
230 #define VXGE_HAL_G3FBCT_LOOP_BACK3_LBCTRL_CM_RDLL_MON_RESULT(val)\ argument
233 #define VXGE_HAL_G3FBCT_LOOP_BACK4_LBCTRL_IO_PASS_FAILN(val) vBIT(val, 0, 32) argument
235 #define VXGE_HAL_G3FBCT_LOOP_BACK5_RDLL_START_IO_VAL(val) vBIT(val, 1, 7) argument
236 #define VXGE_HAL_G3FBCT_LOOP_BACK5_RDLL_END_IO_VAL(val) vBIT(val, 9, 7) argument
240 #define VXGE_HAL_G3FBCT_LOOP_BACK_RDLL_LBCTRL_MIN_VAL(val) vBIT(val, 1, 7) argument
241 #define VXGE_HAL_G3FBCT_LOOP_BACK_RDLL_LBCTRL_MAX_VAL(val) vBIT(val, 9, 7) argument
242 #define VXGE_HAL_G3FBCT_LOOP_BACK_RDLL_LBCTRL_MON_MIN_VAL(val) vBIT(val, 17, 7) argument
243 #define VXGE_HAL_G3FBCT_LOOP_BACK_RDLL_LBCTRL_MON_MAX_VAL(val) vBIT(val, 25, 7) argument
245 #define VXGE_HAL_G3FBCT_LOOP_BACK_WDLL_LBCTRL_MIN_VAL(val) vBIT(val, 1, 7) argument
246 #define VXGE_HAL_G3FBCT_LOOP_BACK_WDLL_LBCTRL_MAX_VAL(val) vBIT(val, 9, 7) argument
248 #define VXGE_HAL_G3FBCT_TRAN_WRD_CNT_CTRL_PIPE_WR(val) vBIT(val, 0, 32) argument
249 #define VXGE_HAL_G3FBCT_TRAN_WRD_CNT_CTRL_PIPE_RD(val) vBIT(val, 32, 32) argument
251 #define VXGE_HAL_G3FBCT_TRAN_AP_CNT_CTRL_PIPE_ACT(val) vBIT(val, 0, 16) argument
252 #define VXGE_HAL_G3FBCT_TRAN_AP_CNT_CTRL_PIPE_PRE(val) vBIT(val, 16, 16) argument
257 #define VXGE_HAL_G3FBCT_G3BIST_BTCTRL_STATUS_MAIN(val) vBIT(val, 21, 3) argument
258 #define VXGE_HAL_G3FBCT_G3BIST_BTCTRL_STATUS_ICTRL(val) vBIT(val, 29, 3) argument
385 #define VXGE_HAL_RC_CFG_RXD_ERR_MASK(val) vBIT(val, 0, 4) argument
397 #define VXGE_HAL_RXD_CFG_1BM_QW_SIZE(val) vBIT(val, 5, 3) argument
398 #define VXGE_HAL_RXD_CFG_1BM_QW2WRITE(val) vBIT(val, 8, 8) argument
399 #define VXGE_HAL_RXD_CFG_1BM_HCW_QWOFF(val) vBIT(val, 21, 3) argument
400 #define VXGE_HAL_RXD_CFG_1BM_RTH_VAL_QWOFF(val) vBIT(val, 29, 3) argument
401 #define VXGE_HAL_RXD_CFG_1BM_RTH_VAL_W0OFF(val) vBIT(val, 38, 2) argument
402 #define VXGE_HAL_RXD_CFG_1BM_RTH_VAL_W1OFF(val) vBIT(val, 46, 2) argument
403 #define VXGE_HAL_RXD_CFG_1BM_HEAD_OWN_QWOFF(val) vBIT(val, 53, 3) argument
404 #define VXGE_HAL_RXD_CFG_1BM_HEAD_OWN_BOFF(val) vBIT(val, 61, 3) argument
406 #define VXGE_HAL_RXD_CFG1_1BM_BUFF1_SIZE_QWOFF(val) vBIT(val, 5, 3) argument
407 #define VXGE_HAL_RXD_CFG1_1BM_TRSF_CODE_QWOFF(val) vBIT(val, 45, 3) argument
408 #define VXGE_HAL_RXD_CFG1_1BM_TRSF_CODE_BOFF(val) vBIT(val, 53, 3) argument
409 #define VXGE_HAL_RXD_CFG1_1BM_RTH_BUCKET_DATA_QWOF(val) vBIT(val, 61, 3) argument
411 #define VXGE_HAL_RXD_CFG2_1BM_RTH_BUCKET_DATA_BOFF(val) vBIT(val, 5, 3) argument
412 #define VXGE_HAL_RXD_CFG2_1BM_BUFF1_SIZE_WOFF(val) vBIT(val, 14, 2) argument
413 #define VXGE_HAL_RXD_CFG2_1BM_FRM_INFO_QWOFF(val) vBIT(val, 53, 3) argument
414 #define VXGE_HAL_RXD_CFG2_1BM_FRM_INFO_BOFF(val) vBIT(val, 61, 3) argument
416 #define VXGE_HAL_RXD_CFG3_1BM_BUFF1_PTR_QWOFF(val) vBIT(val, 5, 3) argument
417 #define VXGE_HAL_RXD_CFG3_1BM_TAIL_OWN_QWOFF(val) vBIT(val, 45, 3) argument
418 #define VXGE_HAL_RXD_CFG3_1BM_TAIL_OWN_BOFF(val) vBIT(val, 53, 3) argument
419 #define VXGE_HAL_RXD_CFG3_1BM_HEAD_OWN_BIT_IDX(val) vBIT(val, 57, 3) argument
420 #define VXGE_HAL_RXD_CFG3_1BM_TAIL_OWN_BIT_IDX(val) vBIT(val, 61, 3) argument
422 #define VXGE_HAL_RXD_CFG4_1BM_L3C_QWOFF(val) vBIT(val, 5, 3) argument
423 #define VXGE_HAL_RXD_CFG4_1BM_L3C_WOFF(val) vBIT(val, 14, 2) argument
424 #define VXGE_HAL_RXD_CFG4_1BM_L4C_QWOFF(val) vBIT(val, 21, 3) argument
425 #define VXGE_HAL_RXD_CFG4_1BM_L4C_WOFF(val) vBIT(val, 30, 2) argument
426 #define VXGE_HAL_RXD_CFG4_1BM_VTAG_QWOFF(val) vBIT(val, 37, 3) argument
427 #define VXGE_HAL_RXD_CFG4_1BM_VTAG_WOFF(val) vBIT(val, 46, 2) argument
428 #define VXGE_HAL_RXD_CFG4_1BM_RTH_INFO_QWOFF(val) vBIT(val, 53, 3) argument
429 #define VXGE_HAL_RXD_CFG4_1BM_RTH_INFO_BOFF(val) vBIT(val, 61, 3) argument
431 #define VXGE_HAL_RXD_CFG_3BM_QW_SIZE(val) vBIT(val, 5, 3) argument
432 #define VXGE_HAL_RXD_CFG_3BM_QW2WRITE(val) vBIT(val, 8, 8) argument
433 #define VXGE_HAL_RXD_CFG_3BM_HCW_QWOFF(val) vBIT(val, 21, 3) argument
434 #define VXGE_HAL_RXD_CFG_3BM_RTH_VAL_QWOFF(val) vBIT(val, 29, 3) argument
435 #define VXGE_HAL_RXD_CFG_3BM_RTH_VAL_W0OFF(val) vBIT(val, 38, 2) argument
436 #define VXGE_HAL_RXD_CFG_3BM_RTH_VAL_W1OFF(val) vBIT(val, 46, 2) argument
437 #define VXGE_HAL_RXD_CFG_3BM_HEAD_OWN_QWOFF(val) vBIT(val, 53, 3) argument
438 #define VXGE_HAL_RXD_CFG_3BM_HEAD_OWN_BOFF(val) vBIT(val, 61, 3) argument
440 #define VXGE_HAL_RXD_CFG1_3BM_BUFF1_SIZE_QWOFF(val) vBIT(val, 5, 3) argument
441 #define VXGE_HAL_RXD_CFG1_3BM_BUFF2_SIZE_QWOFF(val) vBIT(val, 13, 3) argument
442 #define VXGE_HAL_RXD_CFG1_3BM_BUFF3_SIZE_QWOFF(val) vBIT(val, 21, 3) argument
443 #define VXGE_HAL_RXD_CFG1_3BM_TRSF_CODE_QWOFF(val) vBIT(val, 45, 3) argument
444 #define VXGE_HAL_RXD_CFG1_3BM_TRSF_CODE_BOFF(val) vBIT(val, 53, 3) argument
445 #define VXGE_HAL_RXD_CFG1_3BM_RTH_BUCKET_DATA_QWOF(val) vBIT(val, 61, 3) argument
447 #define VXGE_HAL_RXD_CFG2_3BM_RTH_BUCKET_DATA_BOFF(val) vBIT(val, 5, 3) argument
448 #define VXGE_HAL_RXD_CFG2_3BM_BUFF1_SIZE_WOFF(val) vBIT(val, 14, 2) argument
449 #define VXGE_HAL_RXD_CFG2_3BM_BUFF2_SIZE_WOFF(val) vBIT(val, 22, 2) argument
450 #define VXGE_HAL_RXD_CFG2_3BM_BUFF3_SIZE_WOFF(val) vBIT(val, 30, 2) argument
451 #define VXGE_HAL_RXD_CFG2_3BM_FRM_INFO_QWOFF(val) vBIT(val, 53, 3) argument
452 #define VXGE_HAL_RXD_CFG2_3BM_FRM_INFO_BOFF(val) vBIT(val, 61, 3) argument
454 #define VXGE_HAL_RXD_CFG3_3BM_BUFF1_PTR_QWOFF(val) vBIT(val, 5, 3) argument
455 #define VXGE_HAL_RXD_CFG3_3BM_BUFF2_PTR_QWOFF(val) vBIT(val, 13, 3) argument
456 #define VXGE_HAL_RXD_CFG3_3BM_BUFF3_PTR_QWOFF(val) vBIT(val, 21, 3) argument
457 #define VXGE_HAL_RXD_CFG3_3BM_TAIL_OWN_QWOFF(val) vBIT(val, 45, 3) argument
458 #define VXGE_HAL_RXD_CFG3_3BM_TAIL_OWN_BOFF(val) vBIT(val, 53, 3) argument
459 #define VXGE_HAL_RXD_CFG3_3BM_HEAD_OWN_BIT_IDX(val) vBIT(val, 57, 3) argument
460 #define VXGE_HAL_RXD_CFG3_3BM_TAIL_OWN_BIT_IDX(val) vBIT(val, 61, 3) argument
462 #define VXGE_HAL_RXD_CFG4_3BM_L3C_QWOFF(val) vBIT(val, 5, 3) argument
463 #define VXGE_HAL_RXD_CFG4_3BM_L3C_WOFF(val) vBIT(val, 14, 2) argument
464 #define VXGE_HAL_RXD_CFG4_3BM_L4C_QWOFF(val) vBIT(val, 21, 3) argument
465 #define VXGE_HAL_RXD_CFG4_3BM_L4C_WOFF(val) vBIT(val, 30, 2) argument
466 #define VXGE_HAL_RXD_CFG4_3BM_VTAG_QWOFF(val) vBIT(val, 37, 3) argument
467 #define VXGE_HAL_RXD_CFG4_3BM_VTAG_WOFF(val) vBIT(val, 46, 2) argument
468 #define VXGE_HAL_RXD_CFG4_3BM_RTH_INFO_QWOFF(val) vBIT(val, 53, 3) argument
469 #define VXGE_HAL_RXD_CFG4_3BM_RTH_INFO_BOFF(val) vBIT(val, 61, 3) argument
471 #define VXGE_HAL_RXD_CFG_5BM_QW_SIZE(val) vBIT(val, 5, 3) argument
472 #define VXGE_HAL_RXD_CFG_5BM_QW2WRITE(val) vBIT(val, 8, 8) argument
473 #define VXGE_HAL_RXD_CFG_5BM_HCW_QWOFF(val) vBIT(val, 21, 3) argument
474 #define VXGE_HAL_RXD_CFG_5BM_RTH_VAL_QWOFF(val) vBIT(val, 29, 3) argument
475 #define VXGE_HAL_RXD_CFG_5BM_RTH_VAL_W0OFF(val) vBIT(val, 38, 2) argument
476 #define VXGE_HAL_RXD_CFG_5BM_RTH_VAL_W1OFF(val) vBIT(val, 46, 2) argument
477 #define VXGE_HAL_RXD_CFG_5BM_HEAD_OWN_QWOFF(val) vBIT(val, 53, 3) argument
478 #define VXGE_HAL_RXD_CFG_5BM_HEAD_OWN_BOFF(val) vBIT(val, 61, 3) argument
480 #define VXGE_HAL_RXD_CFG1_5BM_BUFF1_SIZE_QWOFF(val) vBIT(val, 5, 3) argument
481 #define VXGE_HAL_RXD_CFG1_5BM_BUFF2_SIZE_QWOFF(val) vBIT(val, 13, 3) argument
482 #define VXGE_HAL_RXD_CFG1_5BM_BUFF3_SIZE_QWOFF(val) vBIT(val, 21, 3) argument
483 #define VXGE_HAL_RXD_CFG1_5BM_BUFF4_SIZE_QWOFF(val) vBIT(val, 29, 3) argument
484 #define VXGE_HAL_RXD_CFG1_5BM_BUFF5_SIZE_QWOFF(val) vBIT(val, 37, 3) argument
485 #define VXGE_HAL_RXD_CFG1_5BM_TRSF_CODE_QWOFF(val) vBIT(val, 45, 3) argument
486 #define VXGE_HAL_RXD_CFG1_5BM_TRSF_CODE_BOFF(val) vBIT(val, 53, 3) argument
487 #define VXGE_HAL_RXD_CFG1_5BM_RTH_BUCKET_DATA_QWOF(val) vBIT(val, 61, 3) argument
489 #define VXGE_HAL_RXD_CFG2_5BM_RTH_BUCKET_DATA_BOFF(val) vBIT(val, 5, 3) argument
490 #define VXGE_HAL_RXD_CFG2_5BM_BUFF1_SIZE_WOFF(val) vBIT(val, 14, 2) argument
491 #define VXGE_HAL_RXD_CFG2_5BM_BUFF2_SIZE_WOFF(val) vBIT(val, 22, 2) argument
492 #define VXGE_HAL_RXD_CFG2_5BM_BUFF3_SIZE_WOFF(val) vBIT(val, 30, 2) argument
493 #define VXGE_HAL_RXD_CFG2_5BM_BUFF4_SIZE_WOFF(val) vBIT(val, 38, 2) argument
494 #define VXGE_HAL_RXD_CFG2_5BM_BUFF5_SIZE_WOFF(val) vBIT(val, 46, 2) argument
495 #define VXGE_HAL_RXD_CFG2_5BM_FRM_INFO_QWOFF(val) vBIT(val, 53, 3) argument
496 #define VXGE_HAL_RXD_CFG2_5BM_FRM_INFO_BOFF(val) vBIT(val, 61, 3) argument
498 #define VXGE_HAL_RXD_CFG3_5BM_BUFF1_PTR_QWOFF(val) vBIT(val, 5, 3) argument
499 #define VXGE_HAL_RXD_CFG3_5BM_BUFF2_PTR_QWOFF(val) vBIT(val, 13, 3) argument
500 #define VXGE_HAL_RXD_CFG3_5BM_BUFF3_PTR_QWOFF(val) vBIT(val, 21, 3) argument
501 #define VXGE_HAL_RXD_CFG3_5BM_BUFF4_PTR_QWOFF(val) vBIT(val, 29, 3) argument
502 #define VXGE_HAL_RXD_CFG3_5BM_BUFF5_PTR_QWOFF(val) vBIT(val, 37, 3) argument
503 #define VXGE_HAL_RXD_CFG3_5BM_TAIL_OWN_QWOFF(val) vBIT(val, 45, 3) argument
504 #define VXGE_HAL_RXD_CFG3_5BM_TAIL_OWN_BOFF(val) vBIT(val, 53, 3) argument
505 #define VXGE_HAL_RXD_CFG3_5BM_HEAD_OWN_BIT_IDX(val) vBIT(val, 57, 3) argument
506 #define VXGE_HAL_RXD_CFG3_5BM_TAIL_OWN_BIT_IDX(val) vBIT(val, 61, 3) argument
508 #define VXGE_HAL_RXD_CFG4_5BM_L3C_QWOFF(val) vBIT(val, 5, 3) argument
509 #define VXGE_HAL_RXD_CFG4_5BM_L3C_WOFF(val) vBIT(val, 14, 2) argument
510 #define VXGE_HAL_RXD_CFG4_5BM_L4C_QWOFF(val) vBIT(val, 21, 3) argument
511 #define VXGE_HAL_RXD_CFG4_5BM_L4C_WOFF(val) vBIT(val, 30, 2) argument
512 #define VXGE_HAL_RXD_CFG4_5BM_VTAG_QWOFF(val) vBIT(val, 37, 3) argument
513 #define VXGE_HAL_RXD_CFG4_5BM_VTAG_WOFF(val) vBIT(val, 46, 2) argument
514 #define VXGE_HAL_RXD_CFG4_5BM_RTH_INFO_QWOFF(val) vBIT(val, 53, 3) argument
515 #define VXGE_HAL_RXD_CFG4_5BM_RTH_INFO_BOFF(val) vBIT(val, 61, 3) argument
517 #define VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_0(val) vBIT(val, 3, 5) argument
518 #define VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_1(val) vBIT(val, 11, 5) argument
519 #define VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_2(val) vBIT(val, 19, 5) argument
520 #define VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_3(val) vBIT(val, 27, 5) argument
521 #define VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_4(val) vBIT(val, 35, 5) argument
522 #define VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_5(val) vBIT(val, 43, 5) argument
523 #define VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_6(val) vBIT(val, 51, 5) argument
524 #define VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_7(val) vBIT(val, 59, 5) argument
526 #define VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_8(val) vBIT(val, 3, 5) argument
527 #define VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_9(val) vBIT(val, 11, 5) argument
528 #define VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_10(val) vBIT(val, 19, 5) argument
529 #define VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_11(val) vBIT(val, 27, 5) argument
530 #define VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_12(val) vBIT(val, 35, 5) argument
531 #define VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_13(val) vBIT(val, 43, 5) argument
532 #define VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_14(val) vBIT(val, 51, 5) argument
533 #define VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_15(val) vBIT(val, 59, 5) argument
535 #define VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_16(val) vBIT(val, 3, 5) argument
536 #define VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_17(val) vBIT(val, 11, 5) argument
537 #define VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_18(val) vBIT(val, 19, 5) argument
538 #define VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_19(val) vBIT(val, 27, 5) argument
539 #define VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_20(val) vBIT(val, 35, 5) argument
540 #define VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_21(val) vBIT(val, 43, 5) argument
541 #define VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_22(val) vBIT(val, 51, 5) argument
542 #define VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_23(val) vBIT(val, 59, 5) argument
544 #define VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_24(val) vBIT(val, 3, 5) argument
545 #define VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_25(val) vBIT(val, 11, 5) argument
546 #define VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_26(val) vBIT(val, 19, 5) argument
547 #define VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_27(val) vBIT(val, 27, 5) argument
548 #define VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_28(val) vBIT(val, 35, 5) argument
549 #define VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_29(val) vBIT(val, 43, 5) argument
550 #define VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_30(val) vBIT(val, 51, 5) argument
551 #define VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_31(val) vBIT(val, 59, 5) argument
553 #define VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_32(val) vBIT(val, 3, 5) argument
554 #define VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_33(val) vBIT(val, 11, 5) argument
555 #define VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_34(val) vBIT(val, 19, 5) argument
556 #define VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_35(val) vBIT(val, 27, 5) argument
557 #define VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_36(val) vBIT(val, 35, 5) argument
558 #define VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_37(val) vBIT(val, 43, 5) argument
559 #define VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_38(val) vBIT(val, 51, 5) argument
560 #define VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_39(val) vBIT(val, 59, 5) argument
562 #define VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_40(val) vBIT(val, 3, 5) argument
563 #define VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_41(val) vBIT(val, 11, 5) argument
564 #define VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_42(val) vBIT(val, 19, 5) argument
565 #define VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_43(val) vBIT(val, 27, 5) argument
566 #define VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_44(val) vBIT(val, 35, 5) argument
567 #define VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_45(val) vBIT(val, 43, 5) argument
568 #define VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_46(val) vBIT(val, 51, 5) argument
569 #define VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_47(val) vBIT(val, 59, 5) argument
571 #define VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_48(val) vBIT(val, 3, 5) argument
572 #define VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_49(val) vBIT(val, 11, 5) argument
573 #define VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_50(val) vBIT(val, 19, 5) argument
574 #define VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_51(val) vBIT(val, 27, 5) argument
575 #define VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_52(val) vBIT(val, 35, 5) argument
576 #define VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_53(val) vBIT(val, 43, 5) argument
577 #define VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_54(val) vBIT(val, 51, 5) argument
578 #define VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_55(val) vBIT(val, 59, 5) argument
580 #define VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_56(val) vBIT(val, 3, 5) argument
581 #define VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_57(val) vBIT(val, 11, 5) argument
582 #define VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_58(val) vBIT(val, 19, 5) argument
583 #define VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_59(val) vBIT(val, 27, 5) argument
584 #define VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_60(val) vBIT(val, 35, 5) argument
585 #define VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_61(val) vBIT(val, 43, 5) argument
586 #define VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_62(val) vBIT(val, 51, 5) argument
587 #define VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_63(val) vBIT(val, 59, 5) argument
589 #define VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_64(val) vBIT(val, 3, 5) argument
590 #define VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_65(val) vBIT(val, 11, 5) argument
591 #define VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_66(val) vBIT(val, 19, 5) argument
592 #define VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_67(val) vBIT(val, 27, 5) argument
593 #define VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_68(val) vBIT(val, 35, 5) argument
594 #define VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_69(val) vBIT(val, 43, 5) argument
595 #define VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_70(val) vBIT(val, 51, 5) argument
596 #define VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_71(val) vBIT(val, 59, 5) argument
598 #define VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_72(val) vBIT(val, 3, 5) argument
599 #define VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_73(val) vBIT(val, 11, 5) argument
600 #define VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_74(val) vBIT(val, 19, 5) argument
601 #define VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_75(val) vBIT(val, 27, 5) argument
602 #define VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_76(val) vBIT(val, 35, 5) argument
603 #define VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_77(val) vBIT(val, 43, 5) argument
604 #define VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_78(val) vBIT(val, 51, 5) argument
605 #define VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_79(val) vBIT(val, 59, 5) argument
607 #define VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_80(val) vBIT(val, 3, 5) argument
608 #define VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_81(val) vBIT(val, 11, 5) argument
609 #define VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_82(val) vBIT(val, 19, 5) argument
610 #define VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_83(val) vBIT(val, 27, 5) argument
611 #define VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_84(val) vBIT(val, 35, 5) argument
612 #define VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_85(val) vBIT(val, 43, 5) argument
613 #define VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_86(val) vBIT(val, 51, 5) argument
614 #define VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_87(val) vBIT(val, 59, 5) argument
616 #define VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_88(val) vBIT(val, 3, 5) argument
617 #define VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_89(val) vBIT(val, 11, 5) argument
618 #define VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_90(val) vBIT(val, 19, 5) argument
619 #define VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_91(val) vBIT(val, 27, 5) argument
620 #define VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_92(val) vBIT(val, 35, 5) argument
621 #define VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_93(val) vBIT(val, 43, 5) argument
622 #define VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_94(val) vBIT(val, 51, 5) argument
623 #define VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_95(val) vBIT(val, 59, 5) argument
625 #define VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_96(val) vBIT(val, 3, 5) argument
626 #define VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_97(val) vBIT(val, 11, 5) argument
627 #define VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_98(val) vBIT(val, 19, 5) argument
628 #define VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_99(val) vBIT(val, 27, 5) argument
629 #define VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_100(val) vBIT(val, 35, 5) argument
630 #define VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_101(val) vBIT(val, 43, 5) argument
631 #define VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_102(val) vBIT(val, 51, 5) argument
632 #define VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_103(val) vBIT(val, 59, 5) argument
634 #define VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_104(val) vBIT(val, 3, 5) argument
635 #define VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_105(val) vBIT(val, 11, 5) argument
636 #define VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_106(val) vBIT(val, 19, 5) argument
637 #define VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_107(val) vBIT(val, 27, 5) argument
638 #define VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_108(val) vBIT(val, 35, 5) argument
639 #define VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_109(val) vBIT(val, 43, 5) argument
640 #define VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_110(val) vBIT(val, 51, 5) argument
641 #define VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_111(val) vBIT(val, 59, 5) argument
643 #define VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_112(val) vBIT(val, 3, 5) argument
644 #define VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_113(val) vBIT(val, 11, 5) argument
645 #define VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_114(val) vBIT(val, 19, 5) argument
646 #define VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_115(val) vBIT(val, 27, 5) argument
647 #define VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_116(val) vBIT(val, 35, 5) argument
648 #define VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_117(val) vBIT(val, 43, 5) argument
649 #define VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_118(val) vBIT(val, 51, 5) argument
650 #define VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_119(val) vBIT(val, 59, 5) argument
652 #define VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_120(val) vBIT(val, 3, 5) argument
653 #define VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_121(val) vBIT(val, 11, 5) argument
654 #define VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_122(val) vBIT(val, 19, 5) argument
655 #define VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_123(val) vBIT(val, 27, 5) argument
656 #define VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_124(val) vBIT(val, 35, 5) argument
657 #define VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_125(val) vBIT(val, 43, 5) argument
658 #define VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_126(val) vBIT(val, 51, 5) argument
659 #define VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_127(val) vBIT(val, 59, 5) argument
661 #define VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_128(val) vBIT(val, 3, 5) argument
662 #define VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_129(val) vBIT(val, 11, 5) argument
663 #define VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_130(val) vBIT(val, 19, 5) argument
664 #define VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_131(val) vBIT(val, 27, 5) argument
665 #define VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_132(val) vBIT(val, 35, 5) argument
666 #define VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_133(val) vBIT(val, 43, 5) argument
667 #define VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_134(val) vBIT(val, 51, 5) argument
668 #define VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_135(val) vBIT(val, 59, 5) argument
670 #define VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_136(val) vBIT(val, 3, 5) argument
671 #define VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_137(val) vBIT(val, 11, 5) argument
672 #define VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_138(val) vBIT(val, 19, 5) argument
673 #define VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_139(val) vBIT(val, 27, 5) argument
674 #define VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_140(val) vBIT(val, 35, 5) argument
675 #define VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_141(val) vBIT(val, 43, 5) argument
676 #define VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_142(val) vBIT(val, 51, 5) argument
677 #define VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_143(val) vBIT(val, 59, 5) argument
679 #define VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_144(val) vBIT(val, 3, 5) argument
680 #define VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_145(val) vBIT(val, 11, 5) argument
681 #define VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_146(val) vBIT(val, 19, 5) argument
682 #define VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_147(val) vBIT(val, 27, 5) argument
683 #define VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_148(val) vBIT(val, 35, 5) argument
684 #define VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_149(val) vBIT(val, 43, 5) argument
685 #define VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_150(val) vBIT(val, 51, 5) argument
686 #define VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_151(val) vBIT(val, 59, 5) argument
688 #define VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_152(val) vBIT(val, 3, 5) argument
689 #define VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_153(val) vBIT(val, 11, 5) argument
690 #define VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_154(val) vBIT(val, 19, 5) argument
691 #define VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_155(val) vBIT(val, 27, 5) argument
692 #define VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_156(val) vBIT(val, 35, 5) argument
693 #define VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_157(val) vBIT(val, 43, 5) argument
694 #define VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_158(val) vBIT(val, 51, 5) argument
695 #define VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_159(val) vBIT(val, 59, 5) argument
697 #define VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_160(val) vBIT(val, 3, 5) argument
698 #define VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_161(val) vBIT(val, 11, 5) argument
699 #define VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_162(val) vBIT(val, 19, 5) argument
700 #define VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_163(val) vBIT(val, 27, 5) argument
701 #define VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_164(val) vBIT(val, 35, 5) argument
702 #define VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_165(val) vBIT(val, 43, 5) argument
703 #define VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_166(val) vBIT(val, 51, 5) argument
704 #define VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_167(val) vBIT(val, 59, 5) argument
706 #define VXGE_HAL_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_168(val) vBIT(val, 3, 5) argument
707 #define VXGE_HAL_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_169(val) vBIT(val, 11, 5) argument
708 #define VXGE_HAL_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_170(val) vBIT(val, 19, 5) argument
710 #define VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_0(val) vBIT(val, 3, 5) argument
711 #define VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_1(val) vBIT(val, 11, 5) argument
712 #define VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_2(val) vBIT(val, 19, 5) argument
713 #define VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_3(val) vBIT(val, 27, 5) argument
714 #define VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_4(val) vBIT(val, 35, 5) argument
715 #define VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_5(val) vBIT(val, 43, 5) argument
716 #define VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_6(val) vBIT(val, 51, 5) argument
717 #define VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_7(val) vBIT(val, 59, 5) argument
719 #define VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_8(val) vBIT(val, 3, 5) argument
720 #define VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_9(val) vBIT(val, 11, 5) argument
721 #define VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_10(val) vBIT(val, 19, 5) argument
722 #define VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_11(val) vBIT(val, 27, 5) argument
723 #define VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_12(val) vBIT(val, 35, 5) argument
724 #define VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_13(val) vBIT(val, 43, 5) argument
725 #define VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_14(val) vBIT(val, 51, 5) argument
726 #define VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_15(val) vBIT(val, 59, 5) argument
728 #define VXGE_HAL_RX_QUEUE_PRIORITY_2_RX_Q_NUMBER_16(val) vBIT(val, 3, 5) argument
732 #define VXGE_HAL_REPLICATION_QUEUE_PRIORITY_REPLICATION_QUEUE_PRIORITY(val)\ argument
745 #define VXGE_HAL_RX_MULTI_CAST_CTRL_NO_RXD_TIME_OUT_CNT(val) vBIT(val, 2, 30) argument
746 #define VXGE_HAL_RX_MULTI_CAST_CTRL_TIME_OUT_CNT(val) vBIT(val, 32, 32) argument
748 #define VXGE_HAL_WDE_PRM_CTRL_SPAV_THRESHOLD(val) vBIT(val, 2, 10) argument
749 #define VXGE_HAL_WDE_PRM_CTRL_SPLIT_THRESHOLD(val) vBIT(val, 18, 14) argument
752 #define VXGE_HAL_WDE_PRM_CTRL_FB_ROW_SIZE(val) vBIT(val, 46, 2) argument
754 #define VXGE_HAL_NOA_CTRL_FRM_PRTY_QUOTA(val) vBIT(val, 3, 5) argument
755 #define VXGE_HAL_NOA_CTRL_NON_FRM_PRTY_QUOTA(val) vBIT(val, 11, 5) argument
757 #define VXGE_HAL_NOA_CTRL_MAX_JOB_CNT_FOR_WDE0(val) vBIT(val, 37, 4) argument
758 #define VXGE_HAL_NOA_CTRL_MAX_JOB_CNT_FOR_WDE1(val) vBIT(val, 45, 4) argument
759 #define VXGE_HAL_NOA_CTRL_MAX_JOB_CNT_FOR_WDE2(val) vBIT(val, 53, 4) argument
760 #define VXGE_HAL_NOA_CTRL_MAX_JOB_CNT_FOR_WDE3(val) vBIT(val, 60, 4) argument
775 #define VXGE_HAL_RCQ_BYPQ_CFG_OVERFLOW_THRESHOLD(val) vBIT(val, 10, 22) argument
776 #define VXGE_HAL_RCQ_BYPQ_CFG_BYP_ON_THRESHOLD(val) vBIT(val, 39, 9) argument
777 #define VXGE_HAL_RCQ_BYPQ_CFG_BYP_OFF_THRESHOLD(val) vBIT(val, 55, 9) argument
826 #define VXGE_HAL_KDFC_VP_PARTITION_0_NUMBER_0(val) vBIT(val, 5, 3) argument
827 #define VXGE_HAL_KDFC_VP_PARTITION_0_LENGTH_0(val) vBIT(val, 17, 15) argument
828 #define VXGE_HAL_KDFC_VP_PARTITION_0_NUMBER_1(val) vBIT(val, 37, 3) argument
829 #define VXGE_HAL_KDFC_VP_PARTITION_0_LENGTH_1(val) vBIT(val, 49, 15) argument
831 #define VXGE_HAL_KDFC_VP_PARTITION_1_NUMBER_2(val) vBIT(val, 5, 3) argument
832 #define VXGE_HAL_KDFC_VP_PARTITION_1_LENGTH_2(val) vBIT(val, 17, 15) argument
833 #define VXGE_HAL_KDFC_VP_PARTITION_1_NUMBER_3(val) vBIT(val, 37, 3) argument
834 #define VXGE_HAL_KDFC_VP_PARTITION_1_LENGTH_3(val) vBIT(val, 49, 15) argument
836 #define VXGE_HAL_KDFC_VP_PARTITION_2_NUMBER_4(val) vBIT(val, 5, 3) argument
837 #define VXGE_HAL_KDFC_VP_PARTITION_2_LENGTH_4(val) vBIT(val, 17, 15) argument
838 #define VXGE_HAL_KDFC_VP_PARTITION_2_NUMBER_5(val) vBIT(val, 37, 3) argument
839 #define VXGE_HAL_KDFC_VP_PARTITION_2_LENGTH_5(val) vBIT(val, 49, 15) argument
841 #define VXGE_HAL_KDFC_VP_PARTITION_3_NUMBER_6(val) vBIT(val, 5, 3) argument
842 #define VXGE_HAL_KDFC_VP_PARTITION_3_LENGTH_6(val) vBIT(val, 17, 15) argument
843 #define VXGE_HAL_KDFC_VP_PARTITION_3_NUMBER_7(val) vBIT(val, 37, 3) argument
844 #define VXGE_HAL_KDFC_VP_PARTITION_3_LENGTH_7(val) vBIT(val, 49, 15) argument
846 #define VXGE_HAL_KDFC_VP_PARTITION_4_LENGTH_8(val) vBIT(val, 17, 15) argument
847 #define VXGE_HAL_KDFC_VP_PARTITION_4_LENGTH_9(val) vBIT(val, 49, 15) argument
849 #define VXGE_HAL_KDFC_VP_PARTITION_5_LENGTH_10(val) vBIT(val, 17, 15) argument
850 #define VXGE_HAL_KDFC_VP_PARTITION_5_LENGTH_11(val) vBIT(val, 49, 15) argument
852 #define VXGE_HAL_KDFC_VP_PARTITION_6_LENGTH_12(val) vBIT(val, 17, 15) argument
853 #define VXGE_HAL_KDFC_VP_PARTITION_6_LENGTH_13(val) vBIT(val, 49, 15) argument
855 #define VXGE_HAL_KDFC_VP_PARTITION_7_LENGTH_14(val) vBIT(val, 17, 15) argument
856 #define VXGE_HAL_KDFC_VP_PARTITION_7_LENGTH_15(val) vBIT(val, 49, 15) argument
858 #define VXGE_HAL_KDFC_VP_PARTITION_8_LENGTH_16(val) vBIT(val, 17, 15) argument
860 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_0(val) vBIT(val, 3, 5) argument
861 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_1(val) vBIT(val, 11, 5) argument
862 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_2(val) vBIT(val, 19, 5) argument
863 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_3(val) vBIT(val, 27, 5) argument
864 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_4(val) vBIT(val, 35, 5) argument
865 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_5(val) vBIT(val, 43, 5) argument
866 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_6(val) vBIT(val, 51, 5) argument
867 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_7(val) vBIT(val, 59, 5) argument
869 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_8(val) vBIT(val, 3, 5) argument
870 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_9(val) vBIT(val, 11, 5) argument
871 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_10(val) vBIT(val, 19, 5) argument
872 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_11(val) vBIT(val, 27, 5) argument
873 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_12(val) vBIT(val, 35, 5) argument
874 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_13(val) vBIT(val, 43, 5) argument
875 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_14(val) vBIT(val, 51, 5) argument
876 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_15(val) vBIT(val, 59, 5) argument
878 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_16(val) vBIT(val, 3, 5) argument
879 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_17(val) vBIT(val, 11, 5) argument
880 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_18(val) vBIT(val, 19, 5) argument
881 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_19(val) vBIT(val, 27, 5) argument
882 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_20(val) vBIT(val, 35, 5) argument
883 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_21(val) vBIT(val, 43, 5) argument
884 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_22(val) vBIT(val, 51, 5) argument
885 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_23(val) vBIT(val, 59, 5) argument
887 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_24(val) vBIT(val, 3, 5) argument
888 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_25(val) vBIT(val, 11, 5) argument
889 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_26(val) vBIT(val, 19, 5) argument
890 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_27(val) vBIT(val, 27, 5) argument
891 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_28(val) vBIT(val, 35, 5) argument
892 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_29(val) vBIT(val, 43, 5) argument
893 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_30(val) vBIT(val, 51, 5) argument
894 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_31(val) vBIT(val, 59, 5) argument
896 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_32(val) vBIT(val, 3, 5) argument
897 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_33(val) vBIT(val, 11, 5) argument
898 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_34(val) vBIT(val, 19, 5) argument
899 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_35(val) vBIT(val, 27, 5) argument
900 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_36(val) vBIT(val, 35, 5) argument
901 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_37(val) vBIT(val, 43, 5) argument
902 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_38(val) vBIT(val, 51, 5) argument
903 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_39(val) vBIT(val, 59, 5) argument
905 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_40(val) vBIT(val, 3, 5) argument
906 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_41(val) vBIT(val, 11, 5) argument
907 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_42(val) vBIT(val, 19, 5) argument
908 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_43(val) vBIT(val, 27, 5) argument
909 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_44(val) vBIT(val, 35, 5) argument
910 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_45(val) vBIT(val, 43, 5) argument
911 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_46(val) vBIT(val, 51, 5) argument
912 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_47(val) vBIT(val, 59, 5) argument
914 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_48(val) vBIT(val, 3, 5) argument
915 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_49(val) vBIT(val, 11, 5) argument
916 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_50(val) vBIT(val, 19, 5) argument
917 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_51(val) vBIT(val, 27, 5) argument
918 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_52(val) vBIT(val, 35, 5) argument
919 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_53(val) vBIT(val, 43, 5) argument
920 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_54(val) vBIT(val, 51, 5) argument
921 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_55(val) vBIT(val, 59, 5) argument
923 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_56(val) vBIT(val, 3, 5) argument
924 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_57(val) vBIT(val, 11, 5) argument
925 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_58(val) vBIT(val, 19, 5) argument
926 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_59(val) vBIT(val, 27, 5) argument
927 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_60(val) vBIT(val, 35, 5) argument
928 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_61(val) vBIT(val, 43, 5) argument
929 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_62(val) vBIT(val, 51, 5) argument
930 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_63(val) vBIT(val, 59, 5) argument
932 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_64(val) vBIT(val, 3, 5) argument
933 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_65(val) vBIT(val, 11, 5) argument
934 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_66(val) vBIT(val, 19, 5) argument
935 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_67(val) vBIT(val, 27, 5) argument
936 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_68(val) vBIT(val, 35, 5) argument
937 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_69(val) vBIT(val, 43, 5) argument
938 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_70(val) vBIT(val, 51, 5) argument
939 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_71(val) vBIT(val, 59, 5) argument
941 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_72(val) vBIT(val, 3, 5) argument
942 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_73(val) vBIT(val, 11, 5) argument
943 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_74(val) vBIT(val, 19, 5) argument
944 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_75(val) vBIT(val, 27, 5) argument
945 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_76(val) vBIT(val, 35, 5) argument
946 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_77(val) vBIT(val, 43, 5) argument
947 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_78(val) vBIT(val, 51, 5) argument
948 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_79(val) vBIT(val, 59, 5) argument
950 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_80(val) vBIT(val, 3, 5) argument
951 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_81(val) vBIT(val, 11, 5) argument
952 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_82(val) vBIT(val, 19, 5) argument
953 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_83(val) vBIT(val, 27, 5) argument
954 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_84(val) vBIT(val, 35, 5) argument
955 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_85(val) vBIT(val, 43, 5) argument
956 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_86(val) vBIT(val, 51, 5) argument
957 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_87(val) vBIT(val, 59, 5) argument
959 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_88(val) vBIT(val, 3, 5) argument
960 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_89(val) vBIT(val, 11, 5) argument
961 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_90(val) vBIT(val, 19, 5) argument
962 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_91(val) vBIT(val, 27, 5) argument
963 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_92(val) vBIT(val, 35, 5) argument
964 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_93(val) vBIT(val, 43, 5) argument
965 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_94(val) vBIT(val, 51, 5) argument
966 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_95(val) vBIT(val, 59, 5) argument
968 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_96(val) vBIT(val, 3, 5) argument
969 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_97(val) vBIT(val, 11, 5) argument
970 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_98(val) vBIT(val, 19, 5) argument
971 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_99(val) vBIT(val, 27, 5) argument
972 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_100(val) vBIT(val, 35, 5) argument
973 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_101(val) vBIT(val, 43, 5) argument
974 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_102(val) vBIT(val, 51, 5) argument
975 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_103(val) vBIT(val, 59, 5) argument
977 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_104(val) vBIT(val, 3, 5) argument
978 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_105(val) vBIT(val, 11, 5) argument
979 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_106(val) vBIT(val, 19, 5) argument
980 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_107(val) vBIT(val, 27, 5) argument
981 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_108(val) vBIT(val, 35, 5) argument
982 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_109(val) vBIT(val, 43, 5) argument
983 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_110(val) vBIT(val, 51, 5) argument
984 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_111(val) vBIT(val, 59, 5) argument
986 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_112(val) vBIT(val, 3, 5) argument
987 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_113(val) vBIT(val, 11, 5) argument
988 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_114(val) vBIT(val, 19, 5) argument
989 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_115(val) vBIT(val, 27, 5) argument
990 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_116(val) vBIT(val, 35, 5) argument
991 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_117(val) vBIT(val, 43, 5) argument
992 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_118(val) vBIT(val, 51, 5) argument
993 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_119(val) vBIT(val, 59, 5) argument
995 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_120(val) vBIT(val, 3, 5) argument
996 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_121(val) vBIT(val, 11, 5) argument
997 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_122(val) vBIT(val, 19, 5) argument
998 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_123(val) vBIT(val, 27, 5) argument
999 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_124(val) vBIT(val, 35, 5) argument
1000 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_125(val) vBIT(val, 43, 5) argument
1001 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_126(val) vBIT(val, 51, 5) argument
1002 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_127(val) vBIT(val, 59, 5) argument
1004 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_128(val) vBIT(val, 3, 5) argument
1005 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_129(val) vBIT(val, 11, 5) argument
1006 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_130(val) vBIT(val, 19, 5) argument
1007 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_131(val) vBIT(val, 27, 5) argument
1008 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_132(val) vBIT(val, 35, 5) argument
1009 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_133(val) vBIT(val, 43, 5) argument
1010 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_134(val) vBIT(val, 51, 5) argument
1011 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_135(val) vBIT(val, 59, 5) argument
1013 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_136(val) vBIT(val, 3, 5) argument
1014 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_137(val) vBIT(val, 11, 5) argument
1015 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_138(val) vBIT(val, 19, 5) argument
1016 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_139(val) vBIT(val, 27, 5) argument
1017 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_140(val) vBIT(val, 35, 5) argument
1018 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_141(val) vBIT(val, 43, 5) argument
1019 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_142(val) vBIT(val, 51, 5) argument
1020 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_143(val) vBIT(val, 59, 5) argument
1022 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_144(val) vBIT(val, 3, 5) argument
1023 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_145(val) vBIT(val, 11, 5) argument
1024 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_146(val) vBIT(val, 19, 5) argument
1025 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_147(val) vBIT(val, 27, 5) argument
1026 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_148(val) vBIT(val, 35, 5) argument
1027 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_149(val) vBIT(val, 43, 5) argument
1028 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_150(val) vBIT(val, 51, 5) argument
1029 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_151(val) vBIT(val, 59, 5) argument
1031 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_19_NUMBER_152(val) vBIT(val, 3, 5) argument
1033 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_0(val) vBIT(val, 3, 5) argument
1034 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_1(val) vBIT(val, 11, 5) argument
1035 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_2(val) vBIT(val, 19, 5) argument
1036 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_3(val) vBIT(val, 27, 5) argument
1037 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_4(val) vBIT(val, 35, 5) argument
1038 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_5(val) vBIT(val, 43, 5) argument
1039 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_6(val) vBIT(val, 51, 5) argument
1040 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_7(val) vBIT(val, 59, 5) argument
1042 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_8(val) vBIT(val, 3, 5) argument
1043 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_9(val) vBIT(val, 11, 5) argument
1044 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_10(val) vBIT(val, 19, 5) argument
1045 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_11(val) vBIT(val, 27, 5) argument
1046 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_12(val) vBIT(val, 35, 5) argument
1047 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_13(val) vBIT(val, 43, 5) argument
1048 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_14(val) vBIT(val, 51, 5) argument
1049 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_15(val) vBIT(val, 59, 5) argument
1051 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_16(val) vBIT(val, 3, 5) argument
1052 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_17(val) vBIT(val, 11, 5) argument
1053 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_18(val) vBIT(val, 19, 5) argument
1054 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_19(val) vBIT(val, 27, 5) argument
1055 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_20(val) vBIT(val, 35, 5) argument
1056 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_21(val) vBIT(val, 43, 5) argument
1057 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_22(val) vBIT(val, 51, 5) argument
1058 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_23(val) vBIT(val, 59, 5) argument
1060 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_24(val) vBIT(val, 3, 5) argument
1061 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_25(val) vBIT(val, 11, 5) argument
1062 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_26(val) vBIT(val, 19, 5) argument
1063 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_27(val) vBIT(val, 27, 5) argument
1064 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_28(val) vBIT(val, 35, 5) argument
1065 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_29(val) vBIT(val, 43, 5) argument
1066 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_30(val) vBIT(val, 51, 5) argument
1067 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_31(val) vBIT(val, 59, 5) argument
1069 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_32(val) vBIT(val, 3, 5) argument
1070 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_33(val) vBIT(val, 11, 5) argument
1071 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_34(val) vBIT(val, 19, 5) argument
1072 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_35(val) vBIT(val, 27, 5) argument
1073 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_36(val) vBIT(val, 35, 5) argument
1074 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_37(val) vBIT(val, 43, 5) argument
1075 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_38(val) vBIT(val, 51, 5) argument
1076 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_39(val) vBIT(val, 59, 5) argument
1078 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_40(val) vBIT(val, 3, 5) argument
1079 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_41(val) vBIT(val, 11, 5) argument
1080 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_42(val) vBIT(val, 19, 5) argument
1081 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_43(val) vBIT(val, 27, 5) argument
1082 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_44(val) vBIT(val, 35, 5) argument
1083 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_45(val) vBIT(val, 43, 5) argument
1084 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_46(val) vBIT(val, 51, 5) argument
1085 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_47(val) vBIT(val, 59, 5) argument
1087 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_48(val) vBIT(val, 3, 5) argument
1088 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_49(val) vBIT(val, 11, 5) argument
1089 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_50(val) vBIT(val, 19, 5) argument
1090 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_51(val) vBIT(val, 27, 5) argument
1091 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_52(val) vBIT(val, 35, 5) argument
1092 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_53(val) vBIT(val, 43, 5) argument
1093 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_54(val) vBIT(val, 51, 5) argument
1094 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_55(val) vBIT(val, 59, 5) argument
1096 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_56(val) vBIT(val, 3, 5) argument
1097 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_57(val) vBIT(val, 11, 5) argument
1098 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_58(val) vBIT(val, 19, 5) argument
1099 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_59(val) vBIT(val, 27, 5) argument
1100 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_60(val) vBIT(val, 35, 5) argument
1101 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_61(val) vBIT(val, 43, 5) argument
1102 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_62(val) vBIT(val, 51, 5) argument
1103 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_63(val) vBIT(val, 59, 5) argument
1105 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_64(val) vBIT(val, 3, 5) argument
1106 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_65(val) vBIT(val, 11, 5) argument
1107 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_66(val) vBIT(val, 19, 5) argument
1108 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_67(val) vBIT(val, 27, 5) argument
1109 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_68(val) vBIT(val, 35, 5) argument
1110 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_69(val) vBIT(val, 43, 5) argument
1111 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_70(val) vBIT(val, 51, 5) argument
1112 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_71(val) vBIT(val, 59, 5) argument
1114 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_72(val) vBIT(val, 3, 5) argument
1115 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_73(val) vBIT(val, 11, 5) argument
1116 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_74(val) vBIT(val, 19, 5) argument
1117 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_75(val) vBIT(val, 27, 5) argument
1118 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_76(val) vBIT(val, 35, 5) argument
1119 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_77(val) vBIT(val, 43, 5) argument
1120 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_78(val) vBIT(val, 51, 5) argument
1121 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_79(val) vBIT(val, 59, 5) argument
1123 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_80(val) vBIT(val, 3, 5) argument
1124 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_81(val) vBIT(val, 11, 5) argument
1125 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_82(val) vBIT(val, 19, 5) argument
1126 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_83(val) vBIT(val, 27, 5) argument
1127 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_84(val) vBIT(val, 35, 5) argument
1128 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_85(val) vBIT(val, 43, 5) argument
1129 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_86(val) vBIT(val, 51, 5) argument
1130 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_87(val) vBIT(val, 59, 5) argument
1132 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_88(val) vBIT(val, 3, 5) argument
1133 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_89(val) vBIT(val, 11, 5) argument
1134 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_90(val) vBIT(val, 19, 5) argument
1135 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_91(val) vBIT(val, 27, 5) argument
1136 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_92(val) vBIT(val, 35, 5) argument
1137 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_93(val) vBIT(val, 43, 5) argument
1138 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_94(val) vBIT(val, 51, 5) argument
1139 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_95(val) vBIT(val, 59, 5) argument
1141 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_96(val) vBIT(val, 3, 5) argument
1142 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_97(val) vBIT(val, 11, 5) argument
1143 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_98(val) vBIT(val, 19, 5) argument
1144 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_99(val) vBIT(val, 27, 5) argument
1145 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_100(val) vBIT(val, 35, 5) argument
1146 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_101(val) vBIT(val, 43, 5) argument
1147 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_102(val) vBIT(val, 51, 5) argument
1148 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_103(val) vBIT(val, 59, 5) argument
1150 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_104(val) vBIT(val, 3, 5) argument
1151 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_105(val) vBIT(val, 11, 5) argument
1152 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_106(val) vBIT(val, 19, 5) argument
1153 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_107(val) vBIT(val, 27, 5) argument
1154 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_108(val) vBIT(val, 35, 5) argument
1155 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_109(val) vBIT(val, 43, 5) argument
1156 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_110(val) vBIT(val, 51, 5) argument
1157 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_111(val) vBIT(val, 59, 5) argument
1159 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_112(val) vBIT(val, 3, 5) argument
1160 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_113(val) vBIT(val, 11, 5) argument
1161 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_114(val) vBIT(val, 19, 5) argument
1162 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_115(val) vBIT(val, 27, 5) argument
1163 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_116(val) vBIT(val, 35, 5) argument
1164 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_117(val) vBIT(val, 43, 5) argument
1165 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_118(val) vBIT(val, 51, 5) argument
1166 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_119(val) vBIT(val, 59, 5) argument
1168 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_120(val) vBIT(val, 3, 5) argument
1169 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_121(val) vBIT(val, 11, 5) argument
1170 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_122(val) vBIT(val, 19, 5) argument
1171 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_123(val) vBIT(val, 27, 5) argument
1172 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_124(val) vBIT(val, 35, 5) argument
1173 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_125(val) vBIT(val, 43, 5) argument
1174 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_126(val) vBIT(val, 51, 5) argument
1175 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_127(val) vBIT(val, 59, 5) argument
1177 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_128(val) vBIT(val, 3, 5) argument
1178 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_129(val) vBIT(val, 11, 5) argument
1179 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_130(val) vBIT(val, 19, 5) argument
1180 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_131(val) vBIT(val, 27, 5) argument
1181 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_132(val) vBIT(val, 35, 5) argument
1182 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_133(val) vBIT(val, 43, 5) argument
1183 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_134(val) vBIT(val, 51, 5) argument
1184 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_135(val) vBIT(val, 59, 5) argument
1186 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_136(val) vBIT(val, 3, 5) argument
1187 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_137(val) vBIT(val, 11, 5) argument
1188 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_138(val) vBIT(val, 19, 5) argument
1189 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_139(val) vBIT(val, 27, 5) argument
1190 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_140(val) vBIT(val, 35, 5) argument
1191 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_141(val) vBIT(val, 43, 5) argument
1192 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_142(val) vBIT(val, 51, 5) argument
1193 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_143(val) vBIT(val, 59, 5) argument
1195 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_144(val) vBIT(val, 3, 5) argument
1196 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_145(val) vBIT(val, 11, 5) argument
1197 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_146(val) vBIT(val, 19, 5) argument
1198 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_147(val) vBIT(val, 27, 5) argument
1199 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_148(val) vBIT(val, 35, 5) argument
1200 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_149(val) vBIT(val, 43, 5) argument
1201 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_150(val) vBIT(val, 51, 5) argument
1202 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_151(val) vBIT(val, 59, 5) argument
1204 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_39_NUMBER_152(val) vBIT(val, 3, 5) argument
1206 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_0(val) vBIT(val, 3, 5) argument
1207 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_1(val) vBIT(val, 11, 5) argument
1208 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_2(val) vBIT(val, 19, 5) argument
1209 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_3(val) vBIT(val, 27, 5) argument
1210 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_4(val) vBIT(val, 35, 5) argument
1211 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_5(val) vBIT(val, 43, 5) argument
1212 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_6(val) vBIT(val, 51, 5) argument
1213 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_7(val) vBIT(val, 59, 5) argument
1215 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_8(val) vBIT(val, 3, 5) argument
1216 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_9(val) vBIT(val, 11, 5) argument
1217 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_10(val) vBIT(val, 19, 5) argument
1218 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_11(val) vBIT(val, 27, 5) argument
1219 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_12(val) vBIT(val, 35, 5) argument
1220 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_13(val) vBIT(val, 43, 5) argument
1221 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_14(val) vBIT(val, 51, 5) argument
1222 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_15(val) vBIT(val, 59, 5) argument
1224 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_16(val) vBIT(val, 3, 5) argument
1225 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_17(val) vBIT(val, 11, 5) argument
1226 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_18(val) vBIT(val, 19, 5) argument
1227 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_19(val) vBIT(val, 27, 5) argument
1228 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_20(val) vBIT(val, 35, 5) argument
1229 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_21(val) vBIT(val, 43, 5) argument
1230 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_22(val) vBIT(val, 51, 5) argument
1231 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_23(val) vBIT(val, 59, 5) argument
1233 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_24(val) vBIT(val, 3, 5) argument
1234 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_25(val) vBIT(val, 11, 5) argument
1235 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_26(val) vBIT(val, 19, 5) argument
1236 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_27(val) vBIT(val, 27, 5) argument
1237 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_28(val) vBIT(val, 35, 5) argument
1238 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_29(val) vBIT(val, 43, 5) argument
1239 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_30(val) vBIT(val, 51, 5) argument
1240 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_31(val) vBIT(val, 59, 5) argument
1242 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_32(val) vBIT(val, 3, 5) argument
1243 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_33(val) vBIT(val, 11, 5) argument
1244 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_34(val) vBIT(val, 19, 5) argument
1245 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_35(val) vBIT(val, 27, 5) argument
1246 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_36(val) vBIT(val, 35, 5) argument
1247 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_37(val) vBIT(val, 43, 5) argument
1248 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_38(val) vBIT(val, 51, 5) argument
1249 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_39(val) vBIT(val, 59, 5) argument
1251 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_40(val) vBIT(val, 3, 5) argument
1252 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_41(val) vBIT(val, 11, 5) argument
1253 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_42(val) vBIT(val, 19, 5) argument
1254 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_43(val) vBIT(val, 27, 5) argument
1255 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_44(val) vBIT(val, 35, 5) argument
1256 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_45(val) vBIT(val, 43, 5) argument
1257 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_46(val) vBIT(val, 51, 5) argument
1258 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_47(val) vBIT(val, 59, 5) argument
1260 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_48(val) vBIT(val, 3, 5) argument
1261 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_49(val) vBIT(val, 11, 5) argument
1262 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_50(val) vBIT(val, 19, 5) argument
1263 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_51(val) vBIT(val, 27, 5) argument
1264 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_52(val) vBIT(val, 35, 5) argument
1265 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_53(val) vBIT(val, 43, 5) argument
1266 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_54(val) vBIT(val, 51, 5) argument
1267 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_55(val) vBIT(val, 59, 5) argument
1269 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_56(val) vBIT(val, 3, 5) argument
1270 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_57(val) vBIT(val, 11, 5) argument
1271 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_58(val) vBIT(val, 19, 5) argument
1272 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_59(val) vBIT(val, 27, 5) argument
1273 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_60(val) vBIT(val, 35, 5) argument
1274 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_61(val) vBIT(val, 43, 5) argument
1275 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_62(val) vBIT(val, 51, 5) argument
1276 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_63(val) vBIT(val, 59, 5) argument
1278 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_64(val) vBIT(val, 3, 5) argument
1279 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_65(val) vBIT(val, 11, 5) argument
1280 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_66(val) vBIT(val, 19, 5) argument
1281 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_67(val) vBIT(val, 27, 5) argument
1282 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_68(val) vBIT(val, 35, 5) argument
1283 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_69(val) vBIT(val, 43, 5) argument
1284 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_70(val) vBIT(val, 51, 5) argument
1285 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_71(val) vBIT(val, 59, 5) argument
1287 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_72(val) vBIT(val, 3, 5) argument
1288 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_73(val) vBIT(val, 11, 5) argument
1289 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_74(val) vBIT(val, 19, 5) argument
1290 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_75(val) vBIT(val, 27, 5) argument
1291 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_76(val) vBIT(val, 35, 5) argument
1292 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_77(val) vBIT(val, 43, 5) argument
1293 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_78(val) vBIT(val, 51, 5) argument
1294 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_79(val) vBIT(val, 59, 5) argument
1296 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_80(val) vBIT(val, 3, 5) argument
1297 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_81(val) vBIT(val, 11, 5) argument
1298 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_82(val) vBIT(val, 19, 5) argument
1299 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_83(val) vBIT(val, 27, 5) argument
1300 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_84(val) vBIT(val, 35, 5) argument
1301 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_85(val) vBIT(val, 43, 5) argument
1302 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_86(val) vBIT(val, 51, 5) argument
1303 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_87(val) vBIT(val, 59, 5) argument
1305 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_88(val) vBIT(val, 3, 5) argument
1306 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_89(val) vBIT(val, 11, 5) argument
1307 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_90(val) vBIT(val, 19, 5) argument
1308 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_91(val) vBIT(val, 27, 5) argument
1309 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_92(val) vBIT(val, 35, 5) argument
1310 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_93(val) vBIT(val, 43, 5) argument
1311 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_94(val) vBIT(val, 51, 5) argument
1312 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_95(val) vBIT(val, 59, 5) argument
1314 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_96(val) vBIT(val, 3, 5) argument
1315 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_97(val) vBIT(val, 11, 5) argument
1316 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_98(val) vBIT(val, 19, 5) argument
1317 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_99(val) vBIT(val, 27, 5) argument
1318 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_100(val) vBIT(val, 35, 5) argument
1319 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_101(val) vBIT(val, 43, 5) argument
1320 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_102(val) vBIT(val, 51, 5) argument
1321 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_103(val) vBIT(val, 59, 5) argument
1323 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_104(val) vBIT(val, 3, 5) argument
1324 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_105(val) vBIT(val, 11, 5) argument
1325 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_106(val) vBIT(val, 19, 5) argument
1326 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_107(val) vBIT(val, 27, 5) argument
1327 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_108(val) vBIT(val, 35, 5) argument
1328 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_109(val) vBIT(val, 43, 5) argument
1329 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_110(val) vBIT(val, 51, 5) argument
1330 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_111(val) vBIT(val, 59, 5) argument
1332 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_112(val) vBIT(val, 3, 5) argument
1333 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_113(val) vBIT(val, 11, 5) argument
1334 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_114(val) vBIT(val, 19, 5) argument
1335 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_115(val) vBIT(val, 27, 5) argument
1336 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_116(val) vBIT(val, 35, 5) argument
1337 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_117(val) vBIT(val, 43, 5) argument
1338 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_118(val) vBIT(val, 51, 5) argument
1339 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_119(val) vBIT(val, 59, 5) argument
1341 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_120(val) vBIT(val, 3, 5) argument
1342 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_121(val) vBIT(val, 11, 5) argument
1343 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_122(val) vBIT(val, 19, 5) argument
1344 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_123(val) vBIT(val, 27, 5) argument
1345 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_124(val) vBIT(val, 35, 5) argument
1346 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_125(val) vBIT(val, 43, 5) argument
1347 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_126(val) vBIT(val, 51, 5) argument
1348 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_127(val) vBIT(val, 59, 5) argument
1350 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_128(val) vBIT(val, 3, 5) argument
1351 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_129(val) vBIT(val, 11, 5) argument
1352 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_130(val) vBIT(val, 19, 5) argument
1353 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_131(val) vBIT(val, 27, 5) argument
1354 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_132(val) vBIT(val, 35, 5) argument
1355 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_133(val) vBIT(val, 43, 5) argument
1356 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_134(val) vBIT(val, 51, 5) argument
1357 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_135(val) vBIT(val, 59, 5) argument
1359 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_136(val) vBIT(val, 3, 5) argument
1360 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_137(val) vBIT(val, 11, 5) argument
1361 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_138(val) vBIT(val, 19, 5) argument
1362 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_139(val) vBIT(val, 27, 5) argument
1363 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_140(val) vBIT(val, 35, 5) argument
1364 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_141(val) vBIT(val, 43, 5) argument
1365 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_142(val) vBIT(val, 51, 5) argument
1366 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_143(val) vBIT(val, 59, 5) argument
1368 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_144(val) vBIT(val, 3, 5) argument
1369 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_145(val) vBIT(val, 11, 5) argument
1370 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_146(val) vBIT(val, 19, 5) argument
1371 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_147(val) vBIT(val, 27, 5) argument
1372 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_148(val) vBIT(val, 35, 5) argument
1373 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_149(val) vBIT(val, 43, 5) argument
1374 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_150(val) vBIT(val, 51, 5) argument
1375 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_151(val) vBIT(val, 59, 5) argument
1377 #define VXGE_HAL_KDFC_W_ROUND_ROBIN_59_NUMBER_152(val) vBIT(val, 3, 5) argument
1379 #define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_0(val) vBIT(val, 6, 2) argument
1380 #define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_1(val) vBIT(val, 14, 2) argument
1381 #define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_2(val) vBIT(val, 22, 2) argument
1382 #define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_3(val) vBIT(val, 30, 2) argument
1383 #define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_4(val) vBIT(val, 38, 2) argument
1384 #define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_5(val) vBIT(val, 46, 2) argument
1385 #define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_6(val) vBIT(val, 54, 2) argument
1386 #define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_7(val) vBIT(val, 62, 2) argument
1388 #define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_1_NUMBER_8(val) vBIT(val, 6, 2) argument
1390 #define VXGE_HAL_KDFC_FIFO_0_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1392 #define VXGE_HAL_KDFC_FIFO_1_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1394 #define VXGE_HAL_KDFC_FIFO_2_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1396 #define VXGE_HAL_KDFC_FIFO_3_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1398 #define VXGE_HAL_KDFC_FIFO_4_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1400 #define VXGE_HAL_KDFC_FIFO_5_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1402 #define VXGE_HAL_KDFC_FIFO_6_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1404 #define VXGE_HAL_KDFC_FIFO_7_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1406 #define VXGE_HAL_KDFC_FIFO_8_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1408 #define VXGE_HAL_KDFC_FIFO_9_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1410 #define VXGE_HAL_KDFC_FIFO_10_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1412 #define VXGE_HAL_KDFC_FIFO_11_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1414 #define VXGE_HAL_KDFC_FIFO_12_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1416 #define VXGE_HAL_KDFC_FIFO_13_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1418 #define VXGE_HAL_KDFC_FIFO_14_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1420 #define VXGE_HAL_KDFC_FIFO_15_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1422 #define VXGE_HAL_KDFC_FIFO_16_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1424 #define VXGE_HAL_KDFC_FIFO_17_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1426 #define VXGE_HAL_KDFC_FIFO_18_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1428 #define VXGE_HAL_KDFC_FIFO_19_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1430 #define VXGE_HAL_KDFC_FIFO_20_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1432 #define VXGE_HAL_KDFC_FIFO_21_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1434 #define VXGE_HAL_KDFC_FIFO_22_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1436 #define VXGE_HAL_KDFC_FIFO_23_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1438 #define VXGE_HAL_KDFC_FIFO_24_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1440 #define VXGE_HAL_KDFC_FIFO_25_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1442 #define VXGE_HAL_KDFC_FIFO_26_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1444 #define VXGE_HAL_KDFC_FIFO_27_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1446 #define VXGE_HAL_KDFC_FIFO_28_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1448 #define VXGE_HAL_KDFC_FIFO_29_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1450 #define VXGE_HAL_KDFC_FIFO_30_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1452 #define VXGE_HAL_KDFC_FIFO_31_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1454 #define VXGE_HAL_KDFC_FIFO_32_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1456 #define VXGE_HAL_KDFC_FIFO_33_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1458 #define VXGE_HAL_KDFC_FIFO_34_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1460 #define VXGE_HAL_KDFC_FIFO_35_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1462 #define VXGE_HAL_KDFC_FIFO_36_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1464 #define VXGE_HAL_KDFC_FIFO_37_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1466 #define VXGE_HAL_KDFC_FIFO_38_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1468 #define VXGE_HAL_KDFC_FIFO_39_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1470 #define VXGE_HAL_KDFC_FIFO_40_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1472 #define VXGE_HAL_KDFC_FIFO_41_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1474 #define VXGE_HAL_KDFC_FIFO_42_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1476 #define VXGE_HAL_KDFC_FIFO_43_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1478 #define VXGE_HAL_KDFC_FIFO_44_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1480 #define VXGE_HAL_KDFC_FIFO_45_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1482 #define VXGE_HAL_KDFC_FIFO_46_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1484 #define VXGE_HAL_KDFC_FIFO_47_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1486 #define VXGE_HAL_KDFC_FIFO_48_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1488 #define VXGE_HAL_KDFC_FIFO_49_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1490 #define VXGE_HAL_KDFC_FIFO_50_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) argument
1492 #define VXGE_HAL_KDFC_KRNL_USR_CTRL_CODE(val) vBIT(val, 4, 4) argument
1495 #define VXGE_HAL_KDFC_PDA_MONITOR_FIFO_NO(val) vBIT(val, 10, 6) argument
1496 #define VXGE_HAL_KDFC_PDA_MONITOR_FIFO_ADD(val) vBIT(val, 17, 15) argument
1497 #define VXGE_HAL_KDFC_PDA_MONITOR_TYPE(val) vBIT(val, 32, 8) argument
1498 #define VXGE_HAL_KDFC_PDA_MONITOR_VP(val) vBIT(val, 43, 5) argument
1501 #define VXGE_HAL_KDFC_MP_MONITOR_FIFO_NO(val) vBIT(val, 10, 6) argument
1502 #define VXGE_HAL_KDFC_MP_MONITOR_FIFO_ADD(val) vBIT(val, 17, 15) argument
1503 #define VXGE_HAL_KDFC_MP_MONITOR_TYPE(val) vBIT(val, 32, 8) argument
1504 #define VXGE_HAL_KDFC_MP_MONITOR_VP(val) vBIT(val, 43, 5) argument
1507 #define VXGE_HAL_KDFC_PE_MONITOR_FIFO_NO(val) vBIT(val, 10, 6) argument
1508 #define VXGE_HAL_KDFC_PE_MONITOR_FIFO_ADD(val) vBIT(val, 17, 15) argument
1509 #define VXGE_HAL_KDFC_PE_MONITOR_TYPE(val) vBIT(val, 32, 8) argument
1510 #define VXGE_HAL_KDFC_PE_MONITOR_VP(val) vBIT(val, 43, 5) argument
1511 #define VXGE_HAL_KDFC_PE_MONITOR_IMM_DATA_CNT(val) vBIT(val, 48, 8) argument
1514 #define VXGE_HAL_KDFC_READ_CNTRL_KDFC_RDCTRL(val) vBIT(val, 14, 2) argument
1516 #define VXGE_HAL_KDFC_READ_CNTRL_KDFC_ADDR(val) vBIT(val, 49, 15) argument
1518 #define VXGE_HAL_KDFC_READ_DATA_READ_DATA(val) vBIT(val, 0, 64) argument
1522 #define VXGE_HAL_KDFC_MULTI_CYCLE_CTRL_MULTI_CYCLE_SEL(val) vBIT(val, 6, 2) argument
1545 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_SG_ERR(val)\ argument
1547 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_DB_ERR(val)\ argument
1549 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_SG_ERR(val)\ argument
1551 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_DB_ERR(val)\ argument
1553 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_SG_ERR(val)\ argument
1555 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_DB_ERR(val)\ argument
1557 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_SG_ERR(val)\ argument
1559 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_DB_ERR(val)\ argument
1561 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_SG_ERR(val)\ argument
1563 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_DB_ERR(val)\ argument
1573 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_SG_ERR(val)\ argument
1575 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_DB_ERR(val)\ argument
1577 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_SG_ERR(val)\ argument
1579 #define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_DB_ERR(val)\ argument
1614 #define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR0(val) vBIT(val, 0, 4) argument
1615 #define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR1(val) vBIT(val, 4, 4) argument
1616 #define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR2(val) vBIT(val, 8, 4) argument
1617 #define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR3(val) vBIT(val, 12, 4) argument
1618 #define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR0(val) vBIT(val, 16, 4) argument
1619 #define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR1(val) vBIT(val, 20, 4) argument
1620 #define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR2(val) vBIT(val, 24, 4) argument
1621 #define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR3(val) vBIT(val, 28, 4) argument
1633 #define VXGE_HAL_RXMAC_CFG0_PORT_MAX_PYLD_LEN(val) vBIT(val, 50, 14) argument
1641 #define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_ACCEL_SEND(val) vBIT(val, 9, 3) argument
1643 #define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME(val) vBIT(val, 20, 16) argument
1647 #define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT(val) vBIT(val, 48, 8) argument
1659 #define VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_UTILIZATION(val) vBIT(val, 1, 7) argument
1660 #define VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG(val) vBIT(val, 8, 4) argument
1661 #define VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_FRAC_UTIL(val) vBIT(val, 12, 4) argument
1662 #define VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_PKT_WEIGHT(val) vBIT(val, 16, 4) argument
1696 #define VXGE_HAL_RTS_MGR_CFG0_FLEX_L4PRTCL_VALUE(val) vBIT(val, 24, 8) argument
1708 #define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_ETYPE(val) vBIT(val, 5, 3) argument
1709 #define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_ICMP_TCPSYN(val) vBIT(val, 9, 3) argument
1710 #define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_L4PN(val) vBIT(val, 13, 3) argument
1711 #define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_RANGE_L4PN(val) vBIT(val, 17, 3) argument
1712 #define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_RTH_IT(val) vBIT(val, 21, 3) argument
1713 #define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_DS(val) vBIT(val, 25, 3) argument
1714 #define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_QOS(val) vBIT(val, 29, 3) argument
1715 #define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_ZL4PYLD(val) vBIT(val, 33, 3) argument
1716 #define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_L4PRTCL(val) vBIT(val, 37, 3) argument
1718 #define VXGE_HAL_RTS_MGR_DA_PAUSE_CFG_VPATH_VECTOR(val) vBIT(val, 0, 17) argument
1720 #define VXGE_HAL_RTS_MGR_DA_SLOW_PROTO_CFG_VPATH_VECTOR(val) vBIT(val, 0, 17) argument
1725 #define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL(val) vBIT(val, 8, 4) argument
1729 #define VXGE_HAL_RTS_MGR_STEER_CTRL_OFFSET(val) vBIT(val, 35, 13) argument
1732 #define VXGE_HAL_RTS_MGR_STEER_DATA0_DATA(val) vBIT(val, 0, 64) argument
1734 #define VXGE_HAL_RTS_MGR_STEER_DATA1_DATA(val) vBIT(val, 0, 64) argument
1736 #define VXGE_HAL_RTS_MGR_STEER_VPATH_VECTOR_VPATH_VECTOR(val) vBIT(val, 0, 17) argument
1740 #define VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_LANE_CHAR1(val) vBIT(val, 1, 3) argument
1742 #define VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_RXD_CHAR1(val) vBIT(val, 8, 8) argument
1743 #define VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_LANE_CHAR2(val) vBIT(val, 17, 3) argument
1745 #define VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_RXD_CHAR2(val) vBIT(val, 24, 8) argument
1747 #define VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_BEHAV_CHAR2_NUM_CHAR(val)\ argument
1751 #define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXD_LANE0(val) vBIT(val, 8, 8) argument
1753 #define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXD_LANE1(val) vBIT(val, 24, 8) argument
1755 #define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXD_LANE2(val) vBIT(val, 40, 8) argument
1757 #define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXD_LANE3(val) vBIT(val, 56, 8) argument
1760 #define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXD_LANE0(val) vBIT(val, 8, 8) argument
1762 #define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXD_LANE1(val) vBIT(val, 24, 8) argument
1764 #define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXD_LANE2(val) vBIT(val, 40, 8) argument
1766 #define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXD_LANE3(val) vBIT(val, 56, 8) argument
1769 #define VXGE_HAL_XMAC_STATS_RX_XGMII_BEHAV_COLUMN2_NUM_COL(val) vBIT(val, 8, 16) argument
1774 #define VXGE_HAL_DBG_STAT_RX_ANY_FRMS_PORT0_RX_ANY_FRMS(val) vBIT(val, 0, 8) argument
1775 #define VXGE_HAL_DBG_STAT_RX_ANY_FRMS_PORT1_RX_ANY_FRMS(val) vBIT(val, 8, 8) argument
1776 #define VXGE_HAL_DBG_STAT_RX_ANY_FRMS_PORT2_RX_ANY_FRMS(val) vBIT(val, 16, 8) argument
1780 #define VXGE_HAL_RXMAC_RED_RATE_VP_CRATE_THR0(val) vBIT(val, 0, 4) argument
1781 #define VXGE_HAL_RXMAC_RED_RATE_VP_CRATE_THR1(val) vBIT(val, 4, 4) argument
1782 #define VXGE_HAL_RXMAC_RED_RATE_VP_CRATE_THR2(val) vBIT(val, 8, 4) argument
1783 #define VXGE_HAL_RXMAC_RED_RATE_VP_CRATE_THR3(val) vBIT(val, 12, 4) argument
1784 #define VXGE_HAL_RXMAC_RED_RATE_VP_FRATE_THR0(val) vBIT(val, 16, 4) argument
1785 #define VXGE_HAL_RXMAC_RED_RATE_VP_FRATE_THR1(val) vBIT(val, 20, 4) argument
1786 #define VXGE_HAL_RXMAC_RED_RATE_VP_FRATE_THR2(val) vBIT(val, 24, 4) argument
1787 #define VXGE_HAL_RXMAC_RED_RATE_VP_FRATE_THR3(val) vBIT(val, 28, 4) argument
1823 #define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_SG_ERR(val)\ argument
1825 #define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_DB_ERR(val)\ argument
1827 #define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_SG_ERR(val)\ argument
1829 #define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_DB_ERR(val)\ argument
1831 #define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_SG_ERR(val)\ argument
1833 #define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_DB_ERR(val)\ argument
1835 #define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_SG_ERR(val)\ argument
1837 #define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_DB_ERR(val)\ argument
1839 #define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_SG_ERR(val)\ argument
1841 #define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_DB_ERR(val)\ argument
1884 #define VXGE_HAL_XGMAC_GEN_FW_MEMO_STATUS_XMACJ_EVENTS_PENDING(val)\ argument
1887 #define VXGE_HAL_XGMAC_GEN_FW_MEMO_MASK_MASK(val) vBIT(val, 0, 64) argument
1889 #define VXGE_HAL_XGMAC_GEN_FW_VPATH_TO_VSPORT_STATUS_XMACJ_EVENTS_PENDING(val)\ argument
1894 #define VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_LINK_UP(val) vBIT(val, 0, 4) argument
1895 #define VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_LINK_DOWN(val) vBIT(val, 4, 4) argument
1896 #define VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_PORT_UP(val) vBIT(val, 8, 4) argument
1897 #define VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_PORT_DOWN(val) vBIT(val, 12, 4) argument
1906 #define VXGE_HAL_XMAC_GEN_CFG_RATEMGMT_MAC_RATE_SEL(val) vBIT(val, 2, 2) argument
1909 #define VXGE_HAL_XMAC_GEN_CFG_PERIOD_NTWK_UP(val) vBIT(val, 28, 4) argument
1910 #define VXGE_HAL_XMAC_GEN_CFG_PERIOD_NTWK_DOWN(val) vBIT(val, 32, 4) argument
1913 #define VXGE_HAL_XMAC_TIMESTAMP_USE_LINK_ID(val) vBIT(val, 6, 2) argument
1914 #define VXGE_HAL_XMAC_TIMESTAMP_INTERVAL(val) vBIT(val, 12, 4) argument
1916 #define VXGE_HAL_XMAC_TIMESTAMP_XMACJ_ROLLOVER_CNT(val) vBIT(val, 32, 16) argument
1918 #define VXGE_HAL_XMAC_STATS_GEN_CFG_PRTAGGR_CUM_TIMER(val) vBIT(val, 4, 4) argument
1919 #define VXGE_HAL_XMAC_STATS_GEN_CFG_VPATH_CUM_TIMER(val) vBIT(val, 8, 4) argument
1922 #define VXGE_HAL_XMAC_STATS_SYS_CMD_OP(val) vBIT(val, 5, 3) argument
1924 #define VXGE_HAL_XMAC_STATS_SYS_CMD_LOC_SEL(val) vBIT(val, 27, 5) argument
1925 #define VXGE_HAL_XMAC_STATS_SYS_CMD_OFFSET_SEL(val) vBIT(val, 32, 8) argument
1927 #define VXGE_HAL_XMAC_STATS_SYS_DATA_XSMGR_DATA(val) vBIT(val, 0, 64) argument
1944 #define VXGE_HAL_XMAC_STATION_ADDR_PORT_MAC_ADDR(val) vBIT(val, 0, 48) argument
1953 #define VXGE_HAL_LAG_CFG_MODE(val) vBIT(val, 6, 2) argument
1959 #define VXGE_HAL_LAG_STATUS_XLCM_TIMER_VAL_COLD_FAILOVER(val) vBIT(val, 8, 8) argument
1966 #define VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_COLD_FAILOVER_TIMEOUT(val)\ argument
1976 #define VXGE_HAL_LAG_TIMER_CFG_1_FAST_PER(val) vBIT(val, 0, 16) argument
1977 #define VXGE_HAL_LAG_TIMER_CFG_1_SLOW_PER(val) vBIT(val, 16, 16) argument
1978 #define VXGE_HAL_LAG_TIMER_CFG_1_SHORT_TIMEOUT(val) vBIT(val, 32, 16) argument
1979 #define VXGE_HAL_LAG_TIMER_CFG_1_LONG_TIMEOUT(val) vBIT(val, 48, 16) argument
1981 #define VXGE_HAL_LAG_TIMER_CFG_2_CHURN_DET(val) vBIT(val, 0, 16) argument
1982 #define VXGE_HAL_LAG_TIMER_CFG_2_AGGR_WAIT(val) vBIT(val, 16, 16) argument
1983 #define VXGE_HAL_LAG_TIMER_CFG_2_SHORT_TIMER_SCALE(val) vBIT(val, 32, 16) argument
1984 #define VXGE_HAL_LAG_TIMER_CFG_2_LONG_TIMER_SCALE(val) vBIT(val, 48, 16) argument
1986 #define VXGE_HAL_LAG_SYS_ID_ADDR(val) vBIT(val, 0, 48) argument
1990 #define VXGE_HAL_LAG_SYS_CFG_SYS_PRI(val) vBIT(val, 0, 16) argument
1994 #define VXGE_HAL_LAG_AGGR_ADDR_CFG_ADDR(val) vBIT(val, 0, 48) argument
1998 #define VXGE_HAL_LAG_AGGR_ID_CFG_ID(val) vBIT(val, 0, 16) argument
2000 #define VXGE_HAL_LAG_AGGR_ADMIN_KEY_KEY(val) vBIT(val, 0, 16) argument
2002 #define VXGE_HAL_LAG_AGGR_ALT_ADMIN_KEY_KEY(val) vBIT(val, 0, 16) argument
2005 #define VXGE_HAL_LAG_AGGR_OPER_KEY_LAGC_KEY(val) vBIT(val, 0, 16) argument
2007 #define VXGE_HAL_LAG_AGGR_PARTNER_SYS_ID_LAGC_ADDR(val) vBIT(val, 0, 48) argument
2009 #define VXGE_HAL_LAG_AGGR_PARTNER_INFO_LAGC_SYS_PRI(val) vBIT(val, 0, 16) argument
2010 #define VXGE_HAL_LAG_AGGR_PARTNER_INFO_LAGC_OPER_KEY(val) vBIT(val, 16, 16) argument
2024 #define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_PORT_NUM(val) vBIT(val, 0, 16) argument
2025 #define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_PORT_PRI(val) vBIT(val, 16, 16) argument
2026 #define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_KEY_10G(val) vBIT(val, 32, 16) argument
2027 #define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_KEY_1G(val) vBIT(val, 48, 16) argument
2038 #define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_SYS_ID_ADDR(val) vBIT(val, 0, 48) argument
2040 #define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_SYS_PRI(val) vBIT(val, 0, 16) argument
2041 #define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_KEY(val) vBIT(val, 16, 16) argument
2042 #define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_PORT_NUM(val) vBIT(val, 32, 16) argument
2043 #define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_PORT_PRI(val) vBIT(val, 48, 16) argument
2054 #define VXGE_HAL_LAG_PORT_TO_AGGR_LAGC_AGGR_ID(val) vBIT(val, 0, 16) argument
2057 #define VXGE_HAL_LAG_PORT_ACTOR_OPER_KEY_LAGC_KEY(val) vBIT(val, 0, 16) argument
2068 #define VXGE_HAL_LAG_PORT_PARTNER_OPER_SYS_ID_LAGC_ADDR(val) vBIT(val, 0, 48) argument
2070 #define VXGE_HAL_LAG_PORT_PARTNER_OPER_INFO_LAGC_SYS_PRI(val) vBIT(val, 0, 16) argument
2071 #define VXGE_HAL_LAG_PORT_PARTNER_OPER_INFO_LAGC_KEY(val) vBIT(val, 16, 16) argument
2072 #define VXGE_HAL_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_NUM(val) vBIT(val, 32, 16) argument
2073 #define VXGE_HAL_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_PRI(val) vBIT(val, 48, 16) argument
2085 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_SELECTED(val) vBIT(val, 6, 2) argument
2097 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_RX_FSM_STATE(val) vBIT(val, 37, 3) argument
2098 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_MUX_FSM_STATE(val) vBIT(val, 41, 3) argument
2099 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_MUX_REASON(val) vBIT(val, 44, 4) argument
2102 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN_COUNT(val)\ argument
2104 #define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN_COUNT(val)\ argument
2110 #define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_TX_LACP(val) vBIT(val, 24, 8) argument
2111 #define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_SYNC_TRANSITION_COUNT(val)\ argument
2113 #define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_SYNC_TRANSITION_COUNT(val)\ argument
2115 #define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_CHANGE_COUNT(val)\ argument
2117 #define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_CHANGE_COUNT(val)\ argument
2122 #define VXGE_HAL_TRANSCEIVER_RESET_PORT_TCVR_RESET(val) vBIT(val, 0, 8) argument
2148 #define VXGE_HAL_ASIC_LED_CTRL1_PORT0_LINK_SOURCE(val) vBIT(val, 2, 2) argument
2149 #define VXGE_HAL_ASIC_LED_CTRL1_PORT0_10G_SOURCE(val) vBIT(val, 6, 2) argument
2150 #define VXGE_HAL_ASIC_LED_CTRL1_PORT1_LINK_SOURCE(val) vBIT(val, 10, 2) argument
2151 #define VXGE_HAL_ASIC_LED_CTRL1_PORT1_10G_SOURCE(val) vBIT(val, 14, 2) argument
2156 #define VXGE_HAL_ASIC_LED_CTRL1_PORT0_LINK_EXT_SEL(val) vBIT(val, 32, 4) argument
2157 #define VXGE_HAL_ASIC_LED_CTRL1_PORT0_10G_EXT_SEL(val) vBIT(val, 36, 4) argument
2158 #define VXGE_HAL_ASIC_LED_CTRL1_PORT1_LINK_EXT_SEL(val) vBIT(val, 40, 4) argument
2159 #define VXGE_HAL_ASIC_LED_CTRL1_PORT1_10G_EXT_SEL(val) vBIT(val, 44, 4) argument
2160 #define VXGE_HAL_ASIC_LED_CTRL1_PORT0_LINK_INT_SEL(val) vBIT(val, 48, 4) argument
2161 #define VXGE_HAL_ASIC_LED_CTRL1_PORT0_10G_INT_SEL(val) vBIT(val, 52, 4) argument
2162 #define VXGE_HAL_ASIC_LED_CTRL1_PORT1_LINK_INT_SEL(val) vBIT(val, 56, 4) argument
2163 #define VXGE_HAL_ASIC_LED_CTRL1_PORT1_10G_INT_SEL(val) vBIT(val, 60, 4) argument
2165 #define VXGE_HAL_ASIC_LED_DEBUG_SEL_XGMAC_SEL0(val) vBIT(val, 2, 6) argument
2166 #define VXGE_HAL_ASIC_LED_DEBUG_SEL_XGMAC_SEL1(val) vBIT(val, 10, 6) argument
2167 #define VXGE_HAL_ASIC_LED_DEBUG_SEL_XGMAC_SEL2(val) vBIT(val, 18, 6) argument
2168 #define VXGE_HAL_ASIC_LED_DEBUG_SEL_XGMAC_SEL3(val) vBIT(val, 26, 6) argument
2174 #define VXGE_HAL_USDC_UGRP_PRIORITY_0_NUMBER_0(val) vBIT(val, 3, 5) argument
2176 #define VXGE_HAL_USDC_UGRP_PRIORITY_1_NUMBER_1(val) vBIT(val, 3, 5) argument
2178 #define VXGE_HAL_USDC_UGRP_PRIORITY_2_NUMBER_2(val) vBIT(val, 3, 5) argument
2180 #define VXGE_HAL_USDC_UGRP_PRIORITY_3_NUMBER_3(val) vBIT(val, 3, 5) argument
2182 #define VXGE_HAL_USDC_UGRP_PRIORITY_4_NUMBER_4(val) vBIT(val, 3, 5) argument
2184 #define VXGE_HAL_USDC_UGRP_PRIORITY_5_NUMBER_5(val) vBIT(val, 3, 5) argument
2186 #define VXGE_HAL_USDC_UGRP_PRIORITY_6_NUMBER_6(val) vBIT(val, 3, 5) argument
2188 #define VXGE_HAL_USDC_UGRP_PRIORITY_7_NUMBER_7(val) vBIT(val, 3, 5) argument
2190 #define VXGE_HAL_USDC_UGRP_PRIORITY_8_NUMBER_8(val) vBIT(val, 3, 5) argument
2192 #define VXGE_HAL_USDC_UGRP_PRIORITY_9_NUMBER_9(val) vBIT(val, 3, 5) argument
2194 #define VXGE_HAL_USDC_UGRP_PRIORITY_10_NUMBER_10(val) vBIT(val, 3, 5) argument
2196 #define VXGE_HAL_USDC_UGRP_PRIORITY_11_NUMBER_11(val) vBIT(val, 3, 5) argument
2198 #define VXGE_HAL_USDC_UGRP_PRIORITY_12_NUMBER_12(val) vBIT(val, 3, 5) argument
2200 #define VXGE_HAL_USDC_UGRP_PRIORITY_13_NUMBER_13(val) vBIT(val, 3, 5) argument
2202 #define VXGE_HAL_USDC_UGRP_PRIORITY_14_NUMBER_14(val) vBIT(val, 3, 5) argument
2204 #define VXGE_HAL_USDC_UGRP_PRIORITY_15_NUMBER_15(val) vBIT(val, 3, 5) argument
2206 #define VXGE_HAL_USDC_UGRP_PRIORITY_16_NUMBER_16(val) vBIT(val, 3, 5) argument
2210 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_0(val) vBIT(val, 3, 5) argument
2211 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_1(val) vBIT(val, 11, 5) argument
2212 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_2(val) vBIT(val, 19, 5) argument
2213 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_3(val) vBIT(val, 27, 5) argument
2214 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_4(val) vBIT(val, 35, 5) argument
2215 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_5(val) vBIT(val, 43, 5) argument
2216 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_6(val) vBIT(val, 51, 5) argument
2217 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_7(val) vBIT(val, 59, 5) argument
2219 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_8(val) vBIT(val, 3, 5) argument
2220 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_9(val) vBIT(val, 11, 5) argument
2221 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_10(val) vBIT(val, 19, 5) argument
2222 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_11(val) vBIT(val, 27, 5) argument
2223 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_12(val) vBIT(val, 35, 5) argument
2224 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_13(val) vBIT(val, 43, 5) argument
2225 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_14(val) vBIT(val, 51, 5) argument
2226 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_15(val) vBIT(val, 59, 5) argument
2228 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_16(val) vBIT(val, 3, 5) argument
2229 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_17(val) vBIT(val, 11, 5) argument
2230 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_18(val) vBIT(val, 19, 5) argument
2231 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_19(val) vBIT(val, 27, 5) argument
2232 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_20(val) vBIT(val, 35, 5) argument
2233 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_21(val) vBIT(val, 43, 5) argument
2234 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_22(val) vBIT(val, 51, 5) argument
2235 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_23(val) vBIT(val, 59, 5) argument
2237 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_24(val) vBIT(val, 3, 5) argument
2238 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_25(val) vBIT(val, 11, 5) argument
2239 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_26(val) vBIT(val, 19, 5) argument
2240 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_27(val) vBIT(val, 27, 5) argument
2241 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_28(val) vBIT(val, 35, 5) argument
2242 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_29(val) vBIT(val, 43, 5) argument
2243 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_30(val) vBIT(val, 51, 5) argument
2244 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_31(val) vBIT(val, 59, 5) argument
2246 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_32(val) vBIT(val, 3, 5) argument
2247 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_33(val) vBIT(val, 11, 5) argument
2248 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_34(val) vBIT(val, 19, 5) argument
2249 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_35(val) vBIT(val, 27, 5) argument
2250 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_36(val) vBIT(val, 35, 5) argument
2251 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_37(val) vBIT(val, 43, 5) argument
2252 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_38(val) vBIT(val, 51, 5) argument
2253 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_39(val) vBIT(val, 59, 5) argument
2255 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_40(val) vBIT(val, 3, 5) argument
2256 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_41(val) vBIT(val, 11, 5) argument
2257 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_42(val) vBIT(val, 19, 5) argument
2258 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_43(val) vBIT(val, 27, 5) argument
2259 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_44(val) vBIT(val, 35, 5) argument
2260 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_45(val) vBIT(val, 43, 5) argument
2261 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_46(val) vBIT(val, 51, 5) argument
2262 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_47(val) vBIT(val, 59, 5) argument
2264 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_48(val) vBIT(val, 3, 5) argument
2265 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_49(val) vBIT(val, 11, 5) argument
2266 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_50(val) vBIT(val, 19, 5) argument
2267 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_51(val) vBIT(val, 27, 5) argument
2268 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_52(val) vBIT(val, 35, 5) argument
2269 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_53(val) vBIT(val, 43, 5) argument
2270 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_54(val) vBIT(val, 51, 5) argument
2271 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_55(val) vBIT(val, 59, 5) argument
2273 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_56(val) vBIT(val, 3, 5) argument
2274 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_57(val) vBIT(val, 11, 5) argument
2275 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_58(val) vBIT(val, 19, 5) argument
2276 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_59(val) vBIT(val, 27, 5) argument
2277 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_60(val) vBIT(val, 35, 5) argument
2278 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_61(val) vBIT(val, 43, 5) argument
2279 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_62(val) vBIT(val, 51, 5) argument
2280 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_63(val) vBIT(val, 59, 5) argument
2282 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_64(val) vBIT(val, 3, 5) argument
2283 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_65(val) vBIT(val, 11, 5) argument
2284 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_66(val) vBIT(val, 19, 5) argument
2285 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_67(val) vBIT(val, 27, 5) argument
2286 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_68(val) vBIT(val, 35, 5) argument
2287 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_69(val) vBIT(val, 43, 5) argument
2288 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_70(val) vBIT(val, 51, 5) argument
2289 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_71(val) vBIT(val, 59, 5) argument
2291 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_72(val) vBIT(val, 3, 5) argument
2292 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_73(val) vBIT(val, 11, 5) argument
2293 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_74(val) vBIT(val, 19, 5) argument
2294 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_75(val) vBIT(val, 27, 5) argument
2295 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_76(val) vBIT(val, 35, 5) argument
2296 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_77(val) vBIT(val, 43, 5) argument
2297 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_78(val) vBIT(val, 51, 5) argument
2298 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_79(val) vBIT(val, 59, 5) argument
2300 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_80(val) vBIT(val, 3, 5) argument
2301 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_81(val) vBIT(val, 11, 5) argument
2302 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_82(val) vBIT(val, 19, 5) argument
2303 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_83(val) vBIT(val, 27, 5) argument
2304 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_84(val) vBIT(val, 35, 5) argument
2305 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_85(val) vBIT(val, 43, 5) argument
2306 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_86(val) vBIT(val, 51, 5) argument
2307 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_87(val) vBIT(val, 59, 5) argument
2309 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_88(val) vBIT(val, 3, 5) argument
2310 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_89(val) vBIT(val, 11, 5) argument
2311 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_90(val) vBIT(val, 19, 5) argument
2312 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_91(val) vBIT(val, 27, 5) argument
2313 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_92(val) vBIT(val, 35, 5) argument
2314 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_93(val) vBIT(val, 43, 5) argument
2315 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_94(val) vBIT(val, 51, 5) argument
2316 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_95(val) vBIT(val, 59, 5) argument
2318 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_96(val) vBIT(val, 3, 5) argument
2319 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_97(val) vBIT(val, 11, 5) argument
2320 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_98(val) vBIT(val, 19, 5) argument
2321 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_99(val) vBIT(val, 27, 5) argument
2322 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_100(val) vBIT(val, 35, 5) argument
2323 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_101(val) vBIT(val, 43, 5) argument
2324 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_102(val) vBIT(val, 51, 5) argument
2325 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_103(val) vBIT(val, 59, 5) argument
2327 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_104(val) vBIT(val, 3, 5) argument
2328 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_105(val) vBIT(val, 11, 5) argument
2329 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_106(val) vBIT(val, 19, 5) argument
2330 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_107(val) vBIT(val, 27, 5) argument
2331 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_108(val) vBIT(val, 35, 5) argument
2332 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_109(val) vBIT(val, 43, 5) argument
2333 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_110(val) vBIT(val, 51, 5) argument
2334 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_111(val) vBIT(val, 59, 5) argument
2336 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_112(val) vBIT(val, 3, 5) argument
2337 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_113(val) vBIT(val, 11, 5) argument
2338 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_114(val) vBIT(val, 19, 5) argument
2339 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_115(val) vBIT(val, 27, 5) argument
2340 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_116(val) vBIT(val, 35, 5) argument
2341 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_117(val) vBIT(val, 43, 5) argument
2342 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_118(val) vBIT(val, 51, 5) argument
2343 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_119(val) vBIT(val, 59, 5) argument
2345 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_120(val) vBIT(val, 3, 5) argument
2346 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_121(val) vBIT(val, 11, 5) argument
2347 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_122(val) vBIT(val, 19, 5) argument
2348 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_123(val) vBIT(val, 27, 5) argument
2349 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_124(val) vBIT(val, 35, 5) argument
2350 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_125(val) vBIT(val, 43, 5) argument
2351 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_126(val) vBIT(val, 51, 5) argument
2352 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_127(val) vBIT(val, 59, 5) argument
2354 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_128(val) vBIT(val, 3, 5) argument
2355 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_129(val) vBIT(val, 11, 5) argument
2356 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_130(val) vBIT(val, 19, 5) argument
2357 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_131(val) vBIT(val, 27, 5) argument
2358 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_132(val) vBIT(val, 35, 5) argument
2359 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_133(val) vBIT(val, 43, 5) argument
2360 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_134(val) vBIT(val, 51, 5) argument
2361 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_135(val) vBIT(val, 59, 5) argument
2363 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_136(val) vBIT(val, 3, 5) argument
2364 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_137(val) vBIT(val, 11, 5) argument
2365 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_138(val) vBIT(val, 19, 5) argument
2366 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_139(val) vBIT(val, 27, 5) argument
2367 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_140(val) vBIT(val, 35, 5) argument
2368 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_141(val) vBIT(val, 43, 5) argument
2369 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_142(val) vBIT(val, 51, 5) argument
2370 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_143(val) vBIT(val, 59, 5) argument
2372 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_144(val) vBIT(val, 3, 5) argument
2373 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_145(val) vBIT(val, 11, 5) argument
2374 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_146(val) vBIT(val, 19, 5) argument
2375 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_147(val) vBIT(val, 27, 5) argument
2376 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_148(val) vBIT(val, 35, 5) argument
2377 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_149(val) vBIT(val, 43, 5) argument
2378 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_150(val) vBIT(val, 51, 5) argument
2379 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_151(val) vBIT(val, 59, 5) argument
2381 #define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_19_NUMBER_152(val) vBIT(val, 3, 5) argument
2383 #define VXGE_HAL_USDC_VPLANE_SGRP_OWN(val) vBIT(val, 0, 32) argument
2420 #define VXGE_HAL_USDC_CNTRL_MIN_VALUE(val) vBIT(val, 1, 7) argument
2423 #define VXGE_HAL_USDC_READ_CNTRL_USDC_RDCTRL(val) vBIT(val, 14, 2) argument
2425 #define VXGE_HAL_USDC_READ_CNTRL_USDC_ADDR(val) vBIT(val, 49, 15) argument
2427 #define VXGE_HAL_USDC_READ_DATA_READ_DATA(val) vBIT(val, 0, 64) argument
2431 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_0(val) vBIT(val, 3, 5) argument
2432 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_1(val) vBIT(val, 11, 5) argument
2433 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_2(val) vBIT(val, 19, 5) argument
2434 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_3(val) vBIT(val, 27, 5) argument
2435 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_4(val) vBIT(val, 35, 5) argument
2436 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_5(val) vBIT(val, 43, 5) argument
2437 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_6(val) vBIT(val, 51, 5) argument
2438 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_7(val) vBIT(val, 59, 5) argument
2440 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_8(val) vBIT(val, 3, 5) argument
2441 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_9(val) vBIT(val, 11, 5) argument
2442 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_10(val) vBIT(val, 19, 5) argument
2443 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_11(val) vBIT(val, 27, 5) argument
2444 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_12(val) vBIT(val, 35, 5) argument
2445 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_13(val) vBIT(val, 43, 5) argument
2446 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_14(val) vBIT(val, 51, 5) argument
2447 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_15(val) vBIT(val, 59, 5) argument
2449 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_16(val) vBIT(val, 3, 5) argument
2450 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_17(val) vBIT(val, 11, 5) argument
2451 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_18(val) vBIT(val, 19, 5) argument
2452 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_19(val) vBIT(val, 27, 5) argument
2453 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_20(val) vBIT(val, 35, 5) argument
2454 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_21(val) vBIT(val, 43, 5) argument
2455 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_22(val) vBIT(val, 51, 5) argument
2456 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_23(val) vBIT(val, 59, 5) argument
2458 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_24(val) vBIT(val, 3, 5) argument
2459 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_25(val) vBIT(val, 11, 5) argument
2460 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_26(val) vBIT(val, 19, 5) argument
2461 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_27(val) vBIT(val, 27, 5) argument
2462 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_28(val) vBIT(val, 35, 5) argument
2463 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_29(val) vBIT(val, 43, 5) argument
2464 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_30(val) vBIT(val, 51, 5) argument
2465 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_31(val) vBIT(val, 59, 5) argument
2467 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_32(val) vBIT(val, 3, 5) argument
2468 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_33(val) vBIT(val, 11, 5) argument
2469 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_34(val) vBIT(val, 19, 5) argument
2470 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_35(val) vBIT(val, 27, 5) argument
2471 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_36(val) vBIT(val, 35, 5) argument
2472 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_37(val) vBIT(val, 43, 5) argument
2473 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_38(val) vBIT(val, 51, 5) argument
2474 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_39(val) vBIT(val, 59, 5) argument
2476 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_40(val) vBIT(val, 3, 5) argument
2477 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_41(val) vBIT(val, 11, 5) argument
2478 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_42(val) vBIT(val, 19, 5) argument
2479 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_43(val) vBIT(val, 27, 5) argument
2480 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_44(val) vBIT(val, 35, 5) argument
2481 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_45(val) vBIT(val, 43, 5) argument
2482 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_46(val) vBIT(val, 51, 5) argument
2483 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_47(val) vBIT(val, 59, 5) argument
2485 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_48(val) vBIT(val, 3, 5) argument
2486 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_49(val) vBIT(val, 11, 5) argument
2487 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_50(val) vBIT(val, 19, 5) argument
2488 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_51(val) vBIT(val, 27, 5) argument
2489 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_52(val) vBIT(val, 35, 5) argument
2490 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_53(val) vBIT(val, 43, 5) argument
2491 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_54(val) vBIT(val, 51, 5) argument
2492 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_55(val) vBIT(val, 59, 5) argument
2494 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_56(val) vBIT(val, 3, 5) argument
2495 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_57(val) vBIT(val, 11, 5) argument
2496 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_58(val) vBIT(val, 19, 5) argument
2497 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_59(val) vBIT(val, 27, 5) argument
2498 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_60(val) vBIT(val, 35, 5) argument
2499 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_61(val) vBIT(val, 43, 5) argument
2500 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_62(val) vBIT(val, 51, 5) argument
2501 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_63(val) vBIT(val, 59, 5) argument
2503 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_64(val) vBIT(val, 3, 5) argument
2504 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_65(val) vBIT(val, 11, 5) argument
2505 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_66(val) vBIT(val, 19, 5) argument
2506 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_67(val) vBIT(val, 27, 5) argument
2507 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_68(val) vBIT(val, 35, 5) argument
2508 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_69(val) vBIT(val, 43, 5) argument
2509 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_70(val) vBIT(val, 51, 5) argument
2510 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_71(val) vBIT(val, 59, 5) argument
2512 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_72(val) vBIT(val, 3, 5) argument
2513 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_73(val) vBIT(val, 11, 5) argument
2514 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_74(val) vBIT(val, 19, 5) argument
2515 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_75(val) vBIT(val, 27, 5) argument
2516 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_76(val) vBIT(val, 35, 5) argument
2517 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_77(val) vBIT(val, 43, 5) argument
2518 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_78(val) vBIT(val, 51, 5) argument
2519 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_79(val) vBIT(val, 59, 5) argument
2521 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_80(val) vBIT(val, 3, 5) argument
2522 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_81(val) vBIT(val, 11, 5) argument
2523 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_82(val) vBIT(val, 19, 5) argument
2524 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_83(val) vBIT(val, 27, 5) argument
2525 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_84(val) vBIT(val, 35, 5) argument
2526 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_85(val) vBIT(val, 43, 5) argument
2527 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_86(val) vBIT(val, 51, 5) argument
2528 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_87(val) vBIT(val, 59, 5) argument
2530 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_88(val) vBIT(val, 3, 5) argument
2531 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_89(val) vBIT(val, 11, 5) argument
2532 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_90(val) vBIT(val, 19, 5) argument
2533 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_91(val) vBIT(val, 27, 5) argument
2534 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_92(val) vBIT(val, 35, 5) argument
2535 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_93(val) vBIT(val, 43, 5) argument
2536 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_94(val) vBIT(val, 51, 5) argument
2537 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_95(val) vBIT(val, 59, 5) argument
2539 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_96(val) vBIT(val, 3, 5) argument
2540 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_97(val) vBIT(val, 11, 5) argument
2541 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_98(val) vBIT(val, 19, 5) argument
2542 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_99(val) vBIT(val, 27, 5) argument
2543 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_100(val) vBIT(val, 35, 5) argument
2544 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_101(val) vBIT(val, 43, 5) argument
2545 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_102(val) vBIT(val, 51, 5) argument
2546 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_103(val) vBIT(val, 59, 5) argument
2548 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_104(val) vBIT(val, 3, 5) argument
2549 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_105(val) vBIT(val, 11, 5) argument
2550 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_106(val) vBIT(val, 19, 5) argument
2551 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_107(val) vBIT(val, 27, 5) argument
2552 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_108(val) vBIT(val, 35, 5) argument
2553 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_109(val) vBIT(val, 43, 5) argument
2554 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_110(val) vBIT(val, 51, 5) argument
2555 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_111(val) vBIT(val, 59, 5) argument
2557 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_112(val) vBIT(val, 3, 5) argument
2558 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_113(val) vBIT(val, 11, 5) argument
2559 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_114(val) vBIT(val, 19, 5) argument
2560 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_115(val) vBIT(val, 27, 5) argument
2561 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_116(val) vBIT(val, 35, 5) argument
2562 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_117(val) vBIT(val, 43, 5) argument
2563 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_118(val) vBIT(val, 51, 5) argument
2564 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_119(val) vBIT(val, 59, 5) argument
2566 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_120(val) vBIT(val, 3, 5) argument
2567 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_121(val) vBIT(val, 11, 5) argument
2568 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_122(val) vBIT(val, 19, 5) argument
2569 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_123(val) vBIT(val, 27, 5) argument
2570 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_124(val) vBIT(val, 35, 5) argument
2571 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_125(val) vBIT(val, 43, 5) argument
2572 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_126(val) vBIT(val, 51, 5) argument
2573 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_127(val) vBIT(val, 59, 5) argument
2575 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_128(val) vBIT(val, 3, 5) argument
2576 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_129(val) vBIT(val, 11, 5) argument
2577 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_130(val) vBIT(val, 19, 5) argument
2578 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_131(val) vBIT(val, 27, 5) argument
2579 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_132(val) vBIT(val, 35, 5) argument
2580 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_133(val) vBIT(val, 43, 5) argument
2581 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_134(val) vBIT(val, 51, 5) argument
2582 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_135(val) vBIT(val, 59, 5) argument
2584 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_136(val) vBIT(val, 3, 5) argument
2585 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_137(val) vBIT(val, 11, 5) argument
2586 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_138(val) vBIT(val, 19, 5) argument
2587 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_139(val) vBIT(val, 27, 5) argument
2588 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_140(val) vBIT(val, 35, 5) argument
2589 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_141(val) vBIT(val, 43, 5) argument
2590 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_142(val) vBIT(val, 51, 5) argument
2591 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_143(val) vBIT(val, 59, 5) argument
2593 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_144(val) vBIT(val, 3, 5) argument
2594 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_145(val) vBIT(val, 11, 5) argument
2595 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_146(val) vBIT(val, 19, 5) argument
2596 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_147(val) vBIT(val, 27, 5) argument
2597 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_148(val) vBIT(val, 35, 5) argument
2598 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_149(val) vBIT(val, 43, 5) argument
2599 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_150(val) vBIT(val, 51, 5) argument
2600 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_151(val) vBIT(val, 59, 5) argument
2602 #define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_19_NUMBER_152(val) vBIT(val, 3, 5) argument
2604 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_0(val) vBIT(val, 3, 5) argument
2605 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_1(val) vBIT(val, 11, 5) argument
2606 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_2(val) vBIT(val, 19, 5) argument
2607 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_3(val) vBIT(val, 27, 5) argument
2608 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_4(val) vBIT(val, 35, 5) argument
2609 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_5(val) vBIT(val, 43, 5) argument
2610 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_6(val) vBIT(val, 51, 5) argument
2611 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_7(val) vBIT(val, 59, 5) argument
2613 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_8(val) vBIT(val, 3, 5) argument
2614 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_9(val) vBIT(val, 11, 5) argument
2615 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_10(val) vBIT(val, 19, 5) argument
2616 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_11(val) vBIT(val, 27, 5) argument
2617 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_12(val) vBIT(val, 35, 5) argument
2618 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_13(val) vBIT(val, 43, 5) argument
2619 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_14(val) vBIT(val, 51, 5) argument
2620 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_15(val) vBIT(val, 59, 5) argument
2622 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_16(val) vBIT(val, 3, 5) argument
2623 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_17(val) vBIT(val, 11, 5) argument
2624 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_18(val) vBIT(val, 19, 5) argument
2625 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_19(val) vBIT(val, 27, 5) argument
2626 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_20(val) vBIT(val, 35, 5) argument
2627 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_21(val) vBIT(val, 43, 5) argument
2628 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_22(val) vBIT(val, 51, 5) argument
2629 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_23(val) vBIT(val, 59, 5) argument
2631 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_24(val) vBIT(val, 3, 5) argument
2632 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_25(val) vBIT(val, 11, 5) argument
2633 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_26(val) vBIT(val, 19, 5) argument
2634 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_27(val) vBIT(val, 27, 5) argument
2635 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_28(val) vBIT(val, 35, 5) argument
2636 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_29(val) vBIT(val, 43, 5) argument
2637 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_30(val) vBIT(val, 51, 5) argument
2638 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_31(val) vBIT(val, 59, 5) argument
2640 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_32(val) vBIT(val, 3, 5) argument
2641 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_33(val) vBIT(val, 11, 5) argument
2642 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_34(val) vBIT(val, 19, 5) argument
2643 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_35(val) vBIT(val, 27, 5) argument
2644 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_36(val) vBIT(val, 35, 5) argument
2645 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_37(val) vBIT(val, 43, 5) argument
2646 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_38(val) vBIT(val, 51, 5) argument
2647 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_39(val) vBIT(val, 59, 5) argument
2649 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_40(val) vBIT(val, 3, 5) argument
2650 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_41(val) vBIT(val, 11, 5) argument
2651 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_42(val) vBIT(val, 19, 5) argument
2652 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_43(val) vBIT(val, 27, 5) argument
2653 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_44(val) vBIT(val, 35, 5) argument
2654 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_45(val) vBIT(val, 43, 5) argument
2655 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_46(val) vBIT(val, 51, 5) argument
2656 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_47(val) vBIT(val, 59, 5) argument
2658 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_48(val) vBIT(val, 3, 5) argument
2659 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_49(val) vBIT(val, 11, 5) argument
2660 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_50(val) vBIT(val, 19, 5) argument
2661 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_51(val) vBIT(val, 27, 5) argument
2662 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_52(val) vBIT(val, 35, 5) argument
2663 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_53(val) vBIT(val, 43, 5) argument
2664 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_54(val) vBIT(val, 51, 5) argument
2665 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_55(val) vBIT(val, 59, 5) argument
2667 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_56(val) vBIT(val, 3, 5) argument
2668 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_57(val) vBIT(val, 11, 5) argument
2669 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_58(val) vBIT(val, 19, 5) argument
2670 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_59(val) vBIT(val, 27, 5) argument
2671 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_60(val) vBIT(val, 35, 5) argument
2672 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_61(val) vBIT(val, 43, 5) argument
2673 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_62(val) vBIT(val, 51, 5) argument
2674 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_63(val) vBIT(val, 59, 5) argument
2676 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_64(val) vBIT(val, 3, 5) argument
2677 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_65(val) vBIT(val, 11, 5) argument
2678 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_66(val) vBIT(val, 19, 5) argument
2679 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_67(val) vBIT(val, 27, 5) argument
2680 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_68(val) vBIT(val, 35, 5) argument
2681 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_69(val) vBIT(val, 43, 5) argument
2682 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_70(val) vBIT(val, 51, 5) argument
2683 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_71(val) vBIT(val, 59, 5) argument
2685 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_72(val) vBIT(val, 3, 5) argument
2686 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_73(val) vBIT(val, 11, 5) argument
2687 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_74(val) vBIT(val, 19, 5) argument
2688 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_75(val) vBIT(val, 27, 5) argument
2689 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_76(val) vBIT(val, 35, 5) argument
2690 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_77(val) vBIT(val, 43, 5) argument
2691 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_78(val) vBIT(val, 51, 5) argument
2692 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_79(val) vBIT(val, 59, 5) argument
2694 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_80(val) vBIT(val, 3, 5) argument
2695 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_81(val) vBIT(val, 11, 5) argument
2696 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_82(val) vBIT(val, 19, 5) argument
2697 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_83(val) vBIT(val, 27, 5) argument
2698 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_84(val) vBIT(val, 35, 5) argument
2699 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_85(val) vBIT(val, 43, 5) argument
2700 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_86(val) vBIT(val, 51, 5) argument
2701 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_87(val) vBIT(val, 59, 5) argument
2703 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_88(val) vBIT(val, 3, 5) argument
2704 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_89(val) vBIT(val, 11, 5) argument
2705 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_90(val) vBIT(val, 19, 5) argument
2706 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_91(val) vBIT(val, 27, 5) argument
2707 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_92(val) vBIT(val, 35, 5) argument
2708 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_93(val) vBIT(val, 43, 5) argument
2709 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_94(val) vBIT(val, 51, 5) argument
2710 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_95(val) vBIT(val, 59, 5) argument
2712 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_96(val) vBIT(val, 3, 5) argument
2713 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_97(val) vBIT(val, 11, 5) argument
2714 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_98(val) vBIT(val, 19, 5) argument
2715 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_99(val) vBIT(val, 27, 5) argument
2716 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_100(val) vBIT(val, 35, 5) argument
2717 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_101(val) vBIT(val, 43, 5) argument
2718 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_102(val) vBIT(val, 51, 5) argument
2719 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_103(val) vBIT(val, 59, 5) argument
2721 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_104(val) vBIT(val, 3, 5) argument
2722 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_105(val) vBIT(val, 11, 5) argument
2723 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_106(val) vBIT(val, 19, 5) argument
2724 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_107(val) vBIT(val, 27, 5) argument
2725 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_108(val) vBIT(val, 35, 5) argument
2726 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_109(val) vBIT(val, 43, 5) argument
2727 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_110(val) vBIT(val, 51, 5) argument
2728 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_111(val) vBIT(val, 59, 5) argument
2730 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_112(val) vBIT(val, 3, 5) argument
2731 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_113(val) vBIT(val, 11, 5) argument
2732 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_114(val) vBIT(val, 19, 5) argument
2733 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_115(val) vBIT(val, 27, 5) argument
2734 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_116(val) vBIT(val, 35, 5) argument
2735 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_117(val) vBIT(val, 43, 5) argument
2736 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_118(val) vBIT(val, 51, 5) argument
2737 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_119(val) vBIT(val, 59, 5) argument
2739 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_120(val) vBIT(val, 3, 5) argument
2740 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_121(val) vBIT(val, 11, 5) argument
2741 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_122(val) vBIT(val, 19, 5) argument
2742 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_123(val) vBIT(val, 27, 5) argument
2743 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_124(val) vBIT(val, 35, 5) argument
2744 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_125(val) vBIT(val, 43, 5) argument
2745 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_126(val) vBIT(val, 51, 5) argument
2746 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_127(val) vBIT(val, 59, 5) argument
2748 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_128(val) vBIT(val, 3, 5) argument
2749 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_129(val) vBIT(val, 11, 5) argument
2750 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_130(val) vBIT(val, 19, 5) argument
2751 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_131(val) vBIT(val, 27, 5) argument
2752 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_132(val) vBIT(val, 35, 5) argument
2753 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_133(val) vBIT(val, 43, 5) argument
2754 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_134(val) vBIT(val, 51, 5) argument
2755 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_135(val) vBIT(val, 59, 5) argument
2757 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_136(val) vBIT(val, 3, 5) argument
2758 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_137(val) vBIT(val, 11, 5) argument
2759 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_138(val) vBIT(val, 19, 5) argument
2760 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_139(val) vBIT(val, 27, 5) argument
2761 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_140(val) vBIT(val, 35, 5) argument
2762 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_141(val) vBIT(val, 43, 5) argument
2763 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_142(val) vBIT(val, 51, 5) argument
2764 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_143(val) vBIT(val, 59, 5) argument
2766 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_144(val) vBIT(val, 3, 5) argument
2767 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_145(val) vBIT(val, 11, 5) argument
2768 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_146(val) vBIT(val, 19, 5) argument
2769 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_147(val) vBIT(val, 27, 5) argument
2770 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_148(val) vBIT(val, 35, 5) argument
2771 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_149(val) vBIT(val, 43, 5) argument
2772 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_150(val) vBIT(val, 51, 5) argument
2773 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_151(val) vBIT(val, 59, 5) argument
2775 #define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_19_NUMBER_152(val) vBIT(val, 3, 5) argument
2820 #define VXGE_HAL_PDA_PDA_CONTROL_0_PCC_MAX(val) vBIT(val, 4, 4) argument
2821 #define VXGE_HAL_PDA_PDA_CONTROL_0_FE_MAX(val) vBIT(val, 13, 3) argument
2823 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_0(val) vBIT(val, 5, 3) argument
2824 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_1(val) vBIT(val, 13, 3) argument
2825 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_2(val) vBIT(val, 21, 3) argument
2826 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_3(val) vBIT(val, 29, 3) argument
2827 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_4(val) vBIT(val, 37, 3) argument
2828 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_5(val) vBIT(val, 45, 3) argument
2829 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_6(val) vBIT(val, 53, 3) argument
2830 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_7(val) vBIT(val, 61, 3) argument
2832 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_8(val) vBIT(val, 5, 3) argument
2833 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_9(val) vBIT(val, 13, 3) argument
2834 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_10(val) vBIT(val, 21, 3) argument
2835 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_11(val) vBIT(val, 29, 3) argument
2836 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_12(val) vBIT(val, 37, 3) argument
2837 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_13(val) vBIT(val, 45, 3) argument
2838 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_14(val) vBIT(val, 53, 3) argument
2839 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_15(val) vBIT(val, 61, 3) argument
2841 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_2_NUMBER_16(val) vBIT(val, 5, 3) argument
2842 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_2_NUMBER_17(val) vBIT(val, 13, 3) argument
2843 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_2_NUMBER_18(val) vBIT(val, 21, 3) argument
2844 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_2_NUMBER_19(val) vBIT(val, 29, 3) argument
2845 #define VXGE_HAL_PDA_PDA_SERVICE_STATE_2_NUMBER_20(val) vBIT(val, 37, 3) argument
2847 #define VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_CXP(val) vBIT(val, 5, 3) argument
2848 #define VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_H2L(val) vBIT(val, 13, 3) argument
2849 #define VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_KDFC(val) vBIT(val, 21, 3) argument
2850 #define VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_MP(val) vBIT(val, 29, 3) argument
2851 #define VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_PE(val) vBIT(val, 37, 3) argument
2852 #define VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_QCC(val) vBIT(val, 45, 3) argument
2863 #define VXGE_HAL_PCC_CONTROL_FE_ENABLE(val) vBIT(val, 6, 2) argument
2867 #define VXGE_HAL_PDA_STATUS1_PDA_WRAP_0_CTR(val) vBIT(val, 4, 4) argument
2868 #define VXGE_HAL_PDA_STATUS1_PDA_WRAP_1_CTR(val) vBIT(val, 12, 4) argument
2869 #define VXGE_HAL_PDA_STATUS1_PDA_WRAP_2_CTR(val) vBIT(val, 20, 4) argument
2870 #define VXGE_HAL_PDA_STATUS1_PDA_WRAP_3_CTR(val) vBIT(val, 28, 4) argument
2871 #define VXGE_HAL_PDA_STATUS1_PDA_WRAP_4_CTR(val) vBIT(val, 36, 4) argument
2872 #define VXGE_HAL_PDA_STATUS1_PDA_WRAP_5_CTR(val) vBIT(val, 44, 4) argument
2873 #define VXGE_HAL_PDA_STATUS1_PDA_WRAP_6_CTR(val) vBIT(val, 52, 4) argument
2874 #define VXGE_HAL_PDA_STATUS1_PDA_WRAP_7_CTR(val) vBIT(val, 60, 4) argument
2876 #define VXGE_HAL_RTDMA_BW_TIMER_TIMER_CTRL(val) vBIT(val, 12, 4) argument
2893 #define VXGE_HAL_G3CMCT_CONFIG0_RD_CMD_LATENCY_RPATH(val) vBIT(val, 5, 3) argument
2894 #define VXGE_HAL_G3CMCT_CONFIG0_RD_CMD_LATENCY(val) vBIT(val, 13, 3) argument
2895 #define VXGE_HAL_G3CMCT_CONFIG0_REFRESH_PER(val) vBIT(val, 16, 16) argument
2896 #define VXGE_HAL_G3CMCT_CONFIG0_TRC(val) vBIT(val, 35, 5) argument
2897 #define VXGE_HAL_G3CMCT_CONFIG0_TRRD(val) vBIT(val, 44, 4) argument
2898 #define VXGE_HAL_G3CMCT_CONFIG0_TFAW(val) vBIT(val, 50, 6) argument
2899 #define VXGE_HAL_G3CMCT_CONFIG0_RD_FIFO_THR(val) vBIT(val, 58, 6) argument
2901 #define VXGE_HAL_G3CMCT_CONFIG1_BIC_THR(val) vBIT(val, 3, 5) argument
2904 #define VXGE_HAL_G3CMCT_CONFIG1_RD_SAMPLING(val) vBIT(val, 29, 3) argument
2906 #define VXGE_HAL_G3CMCT_CONFIG1_BIC_HI_THR(val) vBIT(val, 43, 5) argument
2907 #define VXGE_HAL_G3CMCT_CONFIG1_BIC_MODE(val) vBIT(val, 54, 2) argument
2908 #define VXGE_HAL_G3CMCT_CONFIG1_ECC_ENABLE(val) vBIT(val, 57, 7) argument
2910 #define VXGE_HAL_G3CMCT_CONFIG2_DEV_USE_ENABLE(val) vBIT(val, 6, 2) argument
2911 #define VXGE_HAL_G3CMCT_CONFIG2_DEV_USE_VALUE(val) vBIT(val, 9, 7) argument
2912 #define VXGE_HAL_G3CMCT_CONFIG2_ARBITER_CTRL(val) vBIT(val, 22, 2) argument
2915 #define VXGE_HAL_G3CMCT_CONFIG2_LAST_CADD(val) vBIT(val, 43, 13) argument
2917 #define VXGE_HAL_G3CMCT_INIT0_MRS_BAD(val) vBIT(val, 5, 3) argument
2918 #define VXGE_HAL_G3CMCT_INIT0_MRS_WL(val) vBIT(val, 13, 3) argument
2921 #define VXGE_HAL_G3CMCT_INIT0_MRS_CL(val) vBIT(val, 44, 4) argument
2923 #define VXGE_HAL_G3CMCT_INIT0_MRS_BL(val) vBIT(val, 62, 2) argument
2925 #define VXGE_HAL_G3CMCT_INIT1_EMRS_BAD(val) vBIT(val, 5, 3) argument
2930 #define VXGE_HAL_G3CMCT_INIT1_EMRS_TWR(val) vBIT(val, 53, 3) argument
2931 #define VXGE_HAL_G3CMCT_INIT1_EMRS_DQ_TER(val) vBIT(val, 62, 2) argument
2933 #define VXGE_HAL_G3CMCT_INIT2_EMRS_DR_STR(val) vBIT(val, 6, 2) argument
2935 #define VXGE_HAL_G3CMCT_INIT2_POWER_UP_DELAY(val) vBIT(val, 16, 24) argument
2936 #define VXGE_HAL_G3CMCT_INIT2_ACTIVE_CMD_DELAY(val) vBIT(val, 40, 24) argument
2938 #define VXGE_HAL_G3CMCT_INIT3_TRP_DELAY(val) vBIT(val, 0, 8) argument
2939 #define VXGE_HAL_G3CMCT_INIT3_TMRD_DELAY(val) vBIT(val, 8, 8) argument
2940 #define VXGE_HAL_G3CMCT_INIT3_TWR2PRE_DELAY(val) vBIT(val, 16, 8) argument
2941 #define VXGE_HAL_G3CMCT_INIT3_TRD2PRE_DELAY(val) vBIT(val, 24, 8) argument
2942 #define VXGE_HAL_G3CMCT_INIT3_TRCDR_DELAY(val) vBIT(val, 32, 8) argument
2943 #define VXGE_HAL_G3CMCT_INIT3_TRCDW_DELAY(val) vBIT(val, 40, 8) argument
2944 #define VXGE_HAL_G3CMCT_INIT3_TWR2RD_DELAY(val) vBIT(val, 48, 8) argument
2945 #define VXGE_HAL_G3CMCT_INIT3_TRD2WR_DELAY(val) vBIT(val, 56, 8) argument
2947 #define VXGE_HAL_G3CMCT_INIT4_TRFC_DELAY(val) vBIT(val, 0, 8) argument
2948 #define VXGE_HAL_G3CMCT_INIT4_REFRESH_BURSTS(val) vBIT(val, 12, 4) argument
2950 #define VXGE_HAL_G3CMCT_INIT4_VENDOR_ID(val) vBIT(val, 32, 8) argument
2951 #define VXGE_HAL_G3CMCT_INIT4_OOO_DEPTH(val) vBIT(val, 42, 6) argument
2955 #define VXGE_HAL_G3CMCT_INIT5_TRAS_DELAY(val) vBIT(val, 3, 5) argument
2956 #define VXGE_HAL_G3CMCT_INIT5_TVID_DELAY(val) vBIT(val, 8, 8) argument
2957 #define VXGE_HAL_G3CMCT_INIT5_TWR_APRE2CMD(val) vBIT(val, 16, 8) argument
2958 #define VXGE_HAL_G3CMCT_INIT5_TRD_APRE2CMD(val) vBIT(val, 24, 8) argument
2959 #define VXGE_HAL_G3CMCT_INIT5_TWR_APRE2CMD_CON(val) vBIT(val, 32, 8) argument
2960 #define VXGE_HAL_G3CMCT_INIT5_GDDR3_DLL_DELAY(val) vBIT(val, 40, 24) argument
2962 #define VXGE_HAL_G3CMCT_DLL_TRAINING1_DLL_TRA_DATA00(val) vBIT(val, 0, 64) argument
2964 #define VXGE_HAL_G3CMCT_DLL_TRAINING2_DLL_TRA_DATA01(val) vBIT(val, 0, 64) argument
2966 #define VXGE_HAL_G3CMCT_DLL_TRAINING3_DLL_TRA_DATA10(val) vBIT(val, 0, 64) argument
2968 #define VXGE_HAL_G3CMCT_DLL_TRAINING4_DLL_TRA_DATA11(val) vBIT(val, 0, 64) argument
2970 #define VXGE_HAL_G3CMCT_DLL_TRAINING6_DLL_TRA_DATA20(val) vBIT(val, 0, 64) argument
2972 #define VXGE_HAL_G3CMCT_DLL_TRAINING7_DLL_TRA_DATA21(val) vBIT(val, 0, 64) argument
2974 #define VXGE_HAL_G3CMCT_DLL_TRAINING8_DLL_TRA_DATA30(val) vBIT(val, 0, 64) argument
2976 #define VXGE_HAL_G3CMCT_DLL_TRAINING9_DLL_TRA_DATA31(val) vBIT(val, 0, 64) argument
2978 #define VXGE_HAL_G3CMCT_DLL_TRAINING5_DLL_TRA_RADD(val) vBIT(val, 2, 14) argument
2979 #define VXGE_HAL_G3CMCT_DLL_TRAINING5_DLL_TRA_CADD0(val) vBIT(val, 21, 11) argument
2980 #define VXGE_HAL_G3CMCT_DLL_TRAINING5_DLL_TRA_CADD1(val) vBIT(val, 37, 11) argument
2982 #define VXGE_HAL_G3CMCT_DLL_TRAINING10_DLL_TP_READS(val) vBIT(val, 4, 4) argument
2983 #define VXGE_HAL_G3CMCT_DLL_TRAINING10_DLL_SAMPLES(val) vBIT(val, 8, 8) argument
2984 #define VXGE_HAL_G3CMCT_DLL_TRAINING10_TRA_LOOPS(val) vBIT(val, 18, 14) argument
2985 #define VXGE_HAL_G3CMCT_DLL_TRAINING10_TRA_PASS_CNT(val) vBIT(val, 33, 7) argument
2986 #define VXGE_HAL_G3CMCT_DLL_TRAINING10_TRA_STEP(val) vBIT(val, 41, 7) argument
2988 #define VXGE_HAL_G3CMCT_DLL_TRAINING11_ICTRL_DLL_TRA_CNT(val) vBIT(val, 0, 48) argument
2989 #define VXGE_HAL_G3CMCT_DLL_TRAINING11_ICTRL_DLL_TRA_DIS(val) vBIT(val, 54, 2) argument
2991 #define VXGE_HAL_G3CMCT_INIT6_TWR_APRE2RD_DELAY(val) vBIT(val, 4, 4) argument
2992 #define VXGE_HAL_G3CMCT_INIT6_TWR_APRE2WR_DELAY(val) vBIT(val, 12, 4) argument
2993 #define VXGE_HAL_G3CMCT_INIT6_TWR_APRE2PRE_DELAY(val) vBIT(val, 20, 4) argument
2994 #define VXGE_HAL_G3CMCT_INIT6_TWR_APRE2ACT_DELAY(val) vBIT(val, 28, 4) argument
2995 #define VXGE_HAL_G3CMCT_INIT6_TRD_APRE2RD_DELAY(val) vBIT(val, 36, 4) argument
2996 #define VXGE_HAL_G3CMCT_INIT6_TRD_APRE2WR_DELAY(val) vBIT(val, 44, 4) argument
2997 #define VXGE_HAL_G3CMCT_INIT6_TRD_APRE2PRE_DELAY(val) vBIT(val, 52, 4) argument
2998 #define VXGE_HAL_G3CMCT_INIT6_TRD_APRE2ACT_DELAY(val) vBIT(val, 60, 4) argument
3000 #define VXGE_HAL_G3CMCT_TEST0_TEST_START_RADD(val) vBIT(val, 2, 14) argument
3001 #define VXGE_HAL_G3CMCT_TEST0_TEST_END_RADD(val) vBIT(val, 18, 14) argument
3002 #define VXGE_HAL_G3CMCT_TEST0_TEST_START_CADD(val) vBIT(val, 37, 11) argument
3003 #define VXGE_HAL_G3CMCT_TEST0_TEST_END_CADD(val) vBIT(val, 53, 11) argument
3005 #define VXGE_HAL_G3CMCT_TEST01_TEST_BANK(val) vBIT(val, 0, 8) argument
3006 #define VXGE_HAL_G3CMCT_TEST01_TEST_CTRL(val) vBIT(val, 12, 4) argument
3010 #define VXGE_HAL_G3CMCT_TEST01_ECC_DEC_TEST_FAIL_CNTR(val) vBIT(val, 40, 16) argument
3013 #define VXGE_HAL_G3CMCT_TEST1_TX_TEST_DATA(val) vBIT(val, 0, 64) argument
3015 #define VXGE_HAL_G3CMCT_TEST2_TX_TEST_DATA(val) vBIT(val, 0, 64) argument
3017 #define VXGE_HAL_G3CMCT_TEST11_TX_TEST_DATA1(val) vBIT(val, 0, 64) argument
3019 #define VXGE_HAL_G3CMCT_TEST21_TX_TEST_DATA1(val) vBIT(val, 0, 64) argument
3021 #define VXGE_HAL_G3CMCT_TEST3_ECC_DEC_RX_TEST_DATA(val) vBIT(val, 0, 64) argument
3023 #define VXGE_HAL_G3CMCT_TEST4_ECC_DEC_RX_TEST_DATA(val) vBIT(val, 0, 64) argument
3025 #define VXGE_HAL_G3CMCT_TEST31_ECC_DEC_RX_TEST_DATA1(val) vBIT(val, 0, 64) argument
3027 #define VXGE_HAL_G3CMCT_TEST41_ECC_DEC_RX_TEST_DATA1(val) vBIT(val, 0, 64) argument
3029 #define VXGE_HAL_G3CMCT_TEST5_ECC_DEC_RX_FAILED_TEST_DATA(val) vBIT(val, 0, 64) argument
3031 #define VXGE_HAL_G3CMCT_TEST6_ECC_DEC_RX_FAILED_TEST_DATA(val) vBIT(val, 0, 64) argument
3033 #define VXGE_HAL_G3CMCT_TEST51_ECC_DEC_RX_FAILED_TEST_DATA1(val)\ argument
3036 #define VXGE_HAL_G3CMCT_TEST61_ECC_DEC_RX_FAILED_TEST_DATA1(val)\ argument
3039 #define VXGE_HAL_G3CMCT_TEST7_ECC_DEC_TEST_FAILED_RADD(val) vBIT(val, 0, 14) argument
3040 #define VXGE_HAL_G3CMCT_TEST7_ECC_DEC_TEST_FAILED_CADD(val) vBIT(val, 19, 11) argument
3041 #define VXGE_HAL_G3CMCT_TEST7_ECC_DEC_TEST_FAILED_BANK(val) vBIT(val, 32, 8) argument
3043 #define VXGE_HAL_G3CMCT_TEST71_ECC_DEC_TEST_FAILED_RADD1(val) vBIT(val, 0, 14) argument
3044 #define VXGE_HAL_G3CMCT_TEST71_ECC_DEC_TEST_FAILED_CADD1(val) vBIT(val, 19, 11) argument
3045 #define VXGE_HAL_G3CMCT_TEST71_ECC_DEC_TEST_FAILED_BANK1(val) vBIT(val, 32, 8) argument
3047 #define VXGE_HAL_G3CMCT_INIT41_VENDOR_ID_U(val) vBIT(val, 0, 8) argument
3050 #define VXGE_HAL_G3CMCT_TEST8_ECC_DEC_U_RX_TEST_DATA_U(val) vBIT(val, 0, 64) argument
3052 #define VXGE_HAL_G3CMCT_TEST9_ECC_DEC_U_RX_TEST_DATA_U(val) vBIT(val, 0, 64) argument
3054 #define VXGE_HAL_G3CMCT_TEST10_ECC_DEC_U_RX_TEST_DATA1_U(val) vBIT(val, 0, 64) argument
3056 #define VXGE_HAL_G3CMCT_TEST101_ECC_DEC_U_RX_TEST_DATA1_U(val) vBIT(val, 0, 64) argument
3058 #define VXGE_HAL_G3CMCT_TEST12_ECC_DEC_U_RX_FAILED_TEST_DATA_U(val)\ argument
3061 #define VXGE_HAL_G3CMCT_TEST13_ECC_DEC_U_RX_FAILED_TEST_DATA_U(val)\ argument
3064 #define VXGE_HAL_G3CMCT_TEST14_ECC_DEC_U_RX_FAILED_TEST_DATA1_U(val)\ argument
3067 #define VXGE_HAL_G3CMCT_TEST15_ECC_DEC_U_RX_FAILED_TEST_DATA1_U(val)\ argument
3070 #define VXGE_HAL_G3CMCT_TEST16_ECC_DEC_U_TEST_FAILED_RADD_U(val)\ argument
3072 #define VXGE_HAL_G3CMCT_TEST16_ECC_DEC_U_TEST_FAILED_CADD_U(val)\ argument
3074 #define VXGE_HAL_G3CMCT_TEST16_ECC_DEC_U_TEST_FAILED_BANK_U(val)\ argument
3077 #define VXGE_HAL_G3CMCT_TEST17_ECC_DEC_U_TEST_FAILED_RADD1_U(val)\ argument
3079 #define VXGE_HAL_G3CMCT_TEST17_ECC_DEC_U_TEST_FAILED_CADD1_U(val)\ argument
3081 #define VXGE_HAL_G3CMCT_TEST17_ECC_DEC_U_TEST_FAILED_BANK1_U(val)\ argument
3084 #define VXGE_HAL_G3CMCT_TEST18_ECC_DEC_U_TEST_FAIL_CNTR_U(val)\ argument
3087 #define VXGE_HAL_G3CMCT_LOOP_BACK_TDATA(val) vBIT(val, 0, 32) argument
3091 #define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_IDLE_VAL(val) vBIT(val, 56, 8) argument
3093 #define VXGE_HAL_G3CMCT_LOOP_BACK1_RDLL_START_VAL(val) vBIT(val, 1, 7) argument
3094 #define VXGE_HAL_G3CMCT_LOOP_BACK1_RDLL_END_VAL(val) vBIT(val, 9, 7) argument
3095 #define VXGE_HAL_G3CMCT_LOOP_BACK1_WDLL_IDLE_VAL(val) vBIT(val, 16, 8) argument
3096 #define VXGE_HAL_G3CMCT_LOOP_BACK1_WDLL_START_VAL(val) vBIT(val, 25, 7) argument
3097 #define VXGE_HAL_G3CMCT_LOOP_BACK1_WDLL_END_VAL(val) vBIT(val, 33, 7) argument
3098 #define VXGE_HAL_G3CMCT_LOOP_BACK1_STEPS(val) vBIT(val, 45, 3) argument
3099 #define VXGE_HAL_G3CMCT_LOOP_BACK1_RDLL_MIN_FILTER(val) vBIT(val, 49, 7) argument
3100 #define VXGE_HAL_G3CMCT_LOOP_BACK1_RDLL_MAX_FILTER(val) vBIT(val, 57, 7) argument
3102 #define VXGE_HAL_G3CMCT_LOOP_BACK2_WDLL_MIN_FILTER(val) vBIT(val, 1, 7) argument
3103 #define VXGE_HAL_G3CMCT_LOOP_BACK2_WDLL_MAX_FILTER(val) vBIT(val, 9, 7) argument
3105 #define VXGE_HAL_G3CMCT_LOOP_BACK3_LBCTRL_CMU_RDLL_RESULT(val) vBIT(val, 0, 8) argument
3106 #define VXGE_HAL_G3CMCT_LOOP_BACK3_LBCTRL_CMU_WDLL_RESULT(val) vBIT(val, 8, 8) argument
3107 #define VXGE_HAL_G3CMCT_LOOP_BACK3_LBCTRL_CML_RDLL_RESULT(val) vBIT(val, 16, 8) argument
3108 #define VXGE_HAL_G3CMCT_LOOP_BACK3_LBCTRL_CML_WDLL_RESULT(val) vBIT(val, 24, 8) argument
3109 #define VXGE_HAL_G3CMCT_LOOP_BACK3_LBCTRL_CMU_RDLL_MON_RESULT(val)\ argument
3111 #define VXGE_HAL_G3CMCT_LOOP_BACK3_LBCTRL_CML_RDLL_MON_RESULT(val)\ argument
3114 #define VXGE_HAL_G3CMCT_LOOP_BACK4_LBCTRL_IO_U_PASS_FAILN(val) vBIT(val, 0, 32) argument
3115 #define VXGE_HAL_G3CMCT_LOOP_BACK4_LBCTRL_IO_L_PASS_FAILN(val) vBIT(val, 32, 32) argument
3117 #define VXGE_HAL_G3CMCT_LOOP_BACK5_RDLL_START_IO_VAL(val) vBIT(val, 1, 7) argument
3118 #define VXGE_HAL_G3CMCT_LOOP_BACK5_RDLL_END_IO_VAL(val) vBIT(val, 9, 7) argument
3122 #define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_U_MIN_VAL(val) vBIT(val, 1, 7) argument
3123 #define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_U_MAX_VAL(val) vBIT(val, 9, 7) argument
3124 #define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_L_MIN_VAL(val) vBIT(val, 17, 7) argument
3125 #define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_L_MAX_VAL(val) vBIT(val, 25, 7) argument
3126 #define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_MON_U_MIN_VAL(val)\ argument
3128 #define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_MON_U_MAX_VAL(val)\ argument
3130 #define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_MON_L_MIN_VAL(val)\ argument
3132 #define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_MON_L_MAX_VAL(val)\ argument
3135 #define VXGE_HAL_G3CMCT_LOOP_BACK_WDLL_LBCTRL_U_MIN_VAL(val) vBIT(val, 1, 7) argument
3136 #define VXGE_HAL_G3CMCT_LOOP_BACK_WDLL_LBCTRL_U_MAX_VAL(val) vBIT(val, 9, 7) argument
3137 #define VXGE_HAL_G3CMCT_LOOP_BACK_WDLL_LBCTRL_L_MIN_VAL(val) vBIT(val, 17, 7) argument
3138 #define VXGE_HAL_G3CMCT_LOOP_BACK_WDLL_LBCTRL_L_MAX_VAL(val) vBIT(val, 25, 7) argument
3140 #define VXGE_HAL_G3CMCT_TRAN_WRD_CNT_CTRL_PIPE_WR(val) vBIT(val, 0, 32) argument
3141 #define VXGE_HAL_G3CMCT_TRAN_WRD_CNT_CTRL_PIPE_RD(val) vBIT(val, 32, 32) argument
3143 #define VXGE_HAL_G3CMCT_TRAN_AP_CNT_CTRL_PIPE_ACT(val) vBIT(val, 0, 16) argument
3144 #define VXGE_HAL_G3CMCT_TRAN_AP_CNT_CTRL_PIPE_PRE(val) vBIT(val, 16, 16) argument
3149 #define VXGE_HAL_G3CMCT_G3BIST_BTCTRL_STATUS_MAIN(val) vBIT(val, 21, 3) argument
3150 #define VXGE_HAL_G3CMCT_G3BIST_BTCTRL_STATUS_ICTRL(val) vBIT(val, 29, 3) argument
3181 #define VXGE_HAL_RX_THRESH_CFG_REPL_PAUSE_LOW_THR(val) vBIT(val, 0, 8) argument
3182 #define VXGE_HAL_RX_THRESH_CFG_REPL_PAUSE_HIGH_THR(val) vBIT(val, 8, 8) argument
3183 #define VXGE_HAL_RX_THRESH_CFG_REPL_RED_THR_0(val) vBIT(val, 16, 8) argument
3184 #define VXGE_HAL_RX_THRESH_CFG_REPL_RED_THR_1(val) vBIT(val, 24, 8) argument
3185 #define VXGE_HAL_RX_THRESH_CFG_REPL_RED_THR_2(val) vBIT(val, 32, 8) argument
3186 #define VXGE_HAL_RX_THRESH_CFG_REPL_RED_THR_3(val) vBIT(val, 40, 8) argument
3190 #define VXGE_HAL_DBG_REG1_0_INCTRL_QUEUE0_RX_NON_OFFLOAD_FRM_CNT(val)\ argument
3192 #define VXGE_HAL_DBG_REG1_0_INCTRL_QUEUE0_RX_OFFLOAD_FRM_CNT(val)\ argument
3194 #define VXGE_HAL_DBG_REG1_0_RP_QUEUE0_NON_OFFLOAD_XMFD_CNT(val)\ argument
3196 #define VXGE_HAL_DBG_REG1_0_RP_QUEUE0_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16) argument
3198 #define VXGE_HAL_DBG_REG1_1_INCTRL_QUEUE1_RX_NON_OFFLOAD_FRM_CNT(val)\ argument
3200 #define VXGE_HAL_DBG_REG1_1_INCTRL_QUEUE1_RX_OFFLOAD_FRM_CNT(val)\ argument
3202 #define VXGE_HAL_DBG_REG1_1_RP_QUEUE1_NON_OFFLOAD_XMFD_CNT(val)\ argument
3204 #define VXGE_HAL_DBG_REG1_1_RP_QUEUE1_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16) argument
3206 #define VXGE_HAL_DBG_REG1_2_INCTRL_QUEUE2_RX_NON_OFFLOAD_FRM_CNT(val)\ argument
3208 #define VXGE_HAL_DBG_REG1_2_INCTRL_QUEUE2_RX_OFFLOAD_FRM_CNT(val)\ argument
3210 #define VXGE_HAL_DBG_REG1_2_RP_QUEUE2_NON_OFFLOAD_XMFD_CNT(val)\ argument
3212 #define VXGE_HAL_DBG_REG1_2_RP_QUEUE2_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16) argument
3214 #define VXGE_HAL_DBG_REG1_3_INCTRL_QUEUE3_RX_NON_OFFLOAD_FRM_CNT(val)\ argument
3216 #define VXGE_HAL_DBG_REG1_3_INCTRL_QUEUE3_RX_OFFLOAD_FRM_CNT(val)\ argument
3218 #define VXGE_HAL_DBG_REG1_3_RP_QUEUE3_NON_OFFLOAD_XMFD_CNT(val)\ argument
3220 #define VXGE_HAL_DBG_REG1_3_RP_QUEUE3_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16) argument
3222 #define VXGE_HAL_DBG_REG1_4_INCTRL_QUEUE4_RX_NON_OFFLOAD_FRM_CNT(val)\ argument
3224 #define VXGE_HAL_DBG_REG1_4_INCTRL_QUEUE4_RX_OFFLOAD_FRM_CNT(val)\ argument
3226 #define VXGE_HAL_DBG_REG1_4_RP_QUEUE4_NON_OFFLOAD_XMFD_CNT(val)\ argument
3228 #define VXGE_HAL_DBG_REG1_4_RP_QUEUE4_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16) argument
3230 #define VXGE_HAL_DBG_REG1_5_INCTRL_QUEUE5_RX_NON_OFFLOAD_FRM_CNT(val)\ argument
3232 #define VXGE_HAL_DBG_REG1_5_INCTRL_QUEUE5_RX_OFFLOAD_FRM_CNT(val)\ argument
3234 #define VXGE_HAL_DBG_REG1_5_RP_QUEUE5_NON_OFFLOAD_XMFD_CNT(val)\ argument
3236 #define VXGE_HAL_DBG_REG1_5_RP_QUEUE5_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16) argument
3238 #define VXGE_HAL_DBG_REG1_6_INCTRL_QUEUE6_RX_NON_OFFLOAD_FRM_CNT(val)\ argument
3240 #define VXGE_HAL_DBG_REG1_6_INCTRL_QUEUE6_RX_OFFLOAD_FRM_CNT(val)\ argument
3242 #define VXGE_HAL_DBG_REG1_6_RP_QUEUE6_NON_OFFLOAD_XMFD_CNT(val)\ argument
3244 #define VXGE_HAL_DBG_REG1_6_RP_QUEUE6_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16) argument
3246 #define VXGE_HAL_DBG_REG1_7_INCTRL_QUEUE7_RX_NON_OFFLOAD_FRM_CNT(val)\ argument
3248 #define VXGE_HAL_DBG_REG1_7_INCTRL_QUEUE7_RX_OFFLOAD_FRM_CNT(val)\ argument
3250 #define VXGE_HAL_DBG_REG1_7_RP_QUEUE7_NON_OFFLOAD_XMFD_CNT(val)\ argument
3252 #define VXGE_HAL_DBG_REG1_7_RP_QUEUE7_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16) argument
3254 #define VXGE_HAL_DBG_REG2_XFMDCNT_XFMD_AVAILABLE(val) vBIT(val, 6, 18) argument
3255 #define VXGE_HAL_DBG_REG2_RP_FBMC_PTM_DATA_PHASES(val) vBIT(val, 24, 32) argument
3257 #define VXGE_HAL_DBG_REG3_XFMD_ADV_FBMC_RQA_QUEUE_STROBES(val) vBIT(val, 0, 16) argument
3258 #define VXGE_HAL_DBG_REG3_XFMD_ADV_FBMC_RQA_MC_STROBES(val) vBIT(val, 16, 16) argument
3259 #define VXGE_HAL_DBG_REG3_XFMD_ADV_RQA_FBMC_QUEUE_SELECT(val) vBIT(val, 32, 16) argument
3260 #define VXGE_HAL_DBG_REG3_XFMD_ADV_RQA_FBMC_MC_SELECT(val) vBIT(val, 48, 16) argument
3262 #define VXGE_HAL_DBG_REG4_RP_FBMC_ONE_HEADERS(val) vBIT(val, 0, 16) argument
3264 #define VXGE_HAL_DBG_REG5_INCTRL_TOTAL_ING_FRMS(val) vBIT(val, 0, 32) argument
3265 #define VXGE_HAL_DBG_REG5_RP_TOTAL_EGR_FRMS(val) vBIT(val, 32, 32) argument
3270 #define VXGE_HAL_RX_QUEUE_CFG_INGRESS_FIFO_THR(val) vBIT(val, 60, 4) argument
3272 #define VXGE_HAL_RX_QUEUE_SIZE_Q_SIZE(val) vBIT(val, 0, 24) argument
3273 #define VXGE_HAL_RX_QUEUE_SIZE_Q_LAST_ADD(val) vBIT(val, 24, 24) argument
3275 #define VXGE_HAL_RX_QUEUE_SIZE_Q15_SIZE(val) vBIT(val, 0, 24) argument
3276 #define VXGE_HAL_RX_QUEUE_SIZE_Q15_LAST_ADD(val) vBIT(val, 24, 24) argument
3278 #define VXGE_HAL_RX_QUEUE_SIZE_Q16_SIZE(val) vBIT(val, 0, 24) argument
3279 #define VXGE_HAL_RX_QUEUE_SIZE_Q16_LAST_ADD(val) vBIT(val, 24, 24) argument
3281 #define VXGE_HAL_RX_QUEUE_SIZE_Q17_SIZE(val) vBIT(val, 0, 24) argument
3282 #define VXGE_HAL_RX_QUEUE_SIZE_Q17_LAST_ADD(val) vBIT(val, 24, 24) argument
3286 #define VXGE_HAL_RX_QUEUE_START_Q0_QUEUE_BANKS(val) vBIT(val, 6, 2) argument
3287 #define VXGE_HAL_RX_QUEUE_START_Q0_SBANK(val) vBIT(val, 13, 3) argument
3288 #define VXGE_HAL_RX_QUEUE_START_Q0_SROW(val) vBIT(val, 18, 14) argument
3289 #define VXGE_HAL_RX_QUEUE_START_Q0_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) argument
3290 #define VXGE_HAL_RX_QUEUE_START_Q0_FDP_NONOFFLOAD_OUTST_FRMS(val)\ argument
3293 #define VXGE_HAL_RX_QUEUE_START_Q1_QUEUE_BANKS(val) vBIT(val, 6, 2) argument
3294 #define VXGE_HAL_RX_QUEUE_START_Q1_SBANK(val) vBIT(val, 13, 3) argument
3295 #define VXGE_HAL_RX_QUEUE_START_Q1_SROW(val) vBIT(val, 18, 14) argument
3296 #define VXGE_HAL_RX_QUEUE_START_Q1_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) argument
3297 #define VXGE_HAL_RX_QUEUE_START_Q1_FDP_NONOFFLOAD_OUTST_FRMS(val)\ argument
3300 #define VXGE_HAL_RX_QUEUE_START_Q2_QUEUE_BANKS(val) vBIT(val, 6, 2) argument
3301 #define VXGE_HAL_RX_QUEUE_START_Q2_SBANK(val) vBIT(val, 13, 3) argument
3302 #define VXGE_HAL_RX_QUEUE_START_Q2_SROW(val) vBIT(val, 18, 14) argument
3303 #define VXGE_HAL_RX_QUEUE_START_Q2_FDP_OFFLOAD_OUTST_FRMS(val)\ argument
3305 #define VXGE_HAL_RX_QUEUE_START_Q2_FDP_NONOFFLOAD_OUTST_FRMS(val)\ argument
3308 #define VXGE_HAL_RX_QUEUE_START_Q3_QUEUE_BANKS(val) vBIT(val, 6, 2) argument
3309 #define VXGE_HAL_RX_QUEUE_START_Q3_SBANK(val) vBIT(val, 13, 3) argument
3310 #define VXGE_HAL_RX_QUEUE_START_Q3_SROW(val) vBIT(val, 18, 14) argument
3311 #define VXGE_HAL_RX_QUEUE_START_Q3_FDP_OFFLOAD_OUTST_FRMS(val)\ argument
3313 #define VXGE_HAL_RX_QUEUE_START_Q3_FDP_NONOFFLOAD_OUTST_FRMS(val)\ argument
3316 #define VXGE_HAL_RX_QUEUE_START_Q4_QUEUE_BANKS(val) vBIT(val, 6, 2) argument
3317 #define VXGE_HAL_RX_QUEUE_START_Q4_SBANK(val) vBIT(val, 13, 3) argument
3318 #define VXGE_HAL_RX_QUEUE_START_Q4_SROW(val) vBIT(val, 18, 14) argument
3319 #define VXGE_HAL_RX_QUEUE_START_Q4_FDP_OFFLOAD_OUTST_FRMS(val)\ argument
3321 #define VXGE_HAL_RX_QUEUE_START_Q4_FDP_NONOFFLOAD_OUTST_FRMS(val)\ argument
3324 #define VXGE_HAL_RX_QUEUE_START_Q5_QUEUE_BANKS(val) vBIT(val, 6, 2) argument
3325 #define VXGE_HAL_RX_QUEUE_START_Q5_SBANK(val) vBIT(val, 13, 3) argument
3326 #define VXGE_HAL_RX_QUEUE_START_Q5_SROW(val) vBIT(val, 18, 14) argument
3327 #define VXGE_HAL_RX_QUEUE_START_Q5_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) argument
3328 #define VXGE_HAL_RX_QUEUE_START_Q5_FDP_NONOFFLOAD_OUTST_FRMS(val)\ argument
3331 #define VXGE_HAL_RX_QUEUE_START_Q6_QUEUE_BANKS(val) vBIT(val, 6, 2) argument
3332 #define VXGE_HAL_RX_QUEUE_START_Q6_SBANK(val) vBIT(val, 13, 3) argument
3333 #define VXGE_HAL_RX_QUEUE_START_Q6_SROW(val) vBIT(val, 18, 14) argument
3334 #define VXGE_HAL_RX_QUEUE_START_Q6_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) argument
3335 #define VXGE_HAL_RX_QUEUE_START_Q6_FDP_NONOFFLOAD_OUTST_FRMS(val)\ argument
3338 #define VXGE_HAL_RX_QUEUE_START_Q7_QUEUE_BANKS(val) vBIT(val, 6, 2) argument
3339 #define VXGE_HAL_RX_QUEUE_START_Q7_SBANK(val) vBIT(val, 13, 3) argument
3340 #define VXGE_HAL_RX_QUEUE_START_Q7_SROW(val) vBIT(val, 18, 14) argument
3341 #define VXGE_HAL_RX_QUEUE_START_Q7_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) argument
3342 #define VXGE_HAL_RX_QUEUE_START_Q7_FDP_NONOFFLOAD_OUTST_FRMS(val)\ argument
3345 #define VXGE_HAL_RX_QUEUE_START_Q8_QUEUE_BANKS(val) vBIT(val, 6, 2) argument
3346 #define VXGE_HAL_RX_QUEUE_START_Q8_SBANK(val) vBIT(val, 13, 3) argument
3347 #define VXGE_HAL_RX_QUEUE_START_Q8_SROW(val) vBIT(val, 18, 14) argument
3348 #define VXGE_HAL_RX_QUEUE_START_Q8_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) argument
3350 #define VXGE_HAL_RX_QUEUE_START_Q9_QUEUE_BANKS(val) vBIT(val, 6, 2) argument
3351 #define VXGE_HAL_RX_QUEUE_START_Q9_SBANK(val) vBIT(val, 13, 3) argument
3352 #define VXGE_HAL_RX_QUEUE_START_Q9_SROW(val) vBIT(val, 18, 14) argument
3353 #define VXGE_HAL_RX_QUEUE_START_Q9_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) argument
3355 #define VXGE_HAL_RX_QUEUE_START_Q10_QUEUE_BANKS(val) vBIT(val, 6, 2) argument
3356 #define VXGE_HAL_RX_QUEUE_START_Q10_SBANK(val) vBIT(val, 13, 3) argument
3357 #define VXGE_HAL_RX_QUEUE_START_Q10_SROW(val) vBIT(val, 18, 14) argument
3358 #define VXGE_HAL_RX_QUEUE_START_Q10_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) argument
3360 #define VXGE_HAL_RX_QUEUE_START_Q11_QUEUE_BANKS(val) vBIT(val, 6, 2) argument
3361 #define VXGE_HAL_RX_QUEUE_START_Q11_SBANK(val) vBIT(val, 13, 3) argument
3362 #define VXGE_HAL_RX_QUEUE_START_Q11_SROW(val) vBIT(val, 18, 14) argument
3363 #define VXGE_HAL_RX_QUEUE_START_Q11_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) argument
3365 #define VXGE_HAL_RX_QUEUE_START_Q12_QUEUE_BANKS(val) vBIT(val, 6, 2) argument
3366 #define VXGE_HAL_RX_QUEUE_START_Q12_SBANK(val) vBIT(val, 13, 3) argument
3367 #define VXGE_HAL_RX_QUEUE_START_Q12_SROW(val) vBIT(val, 18, 14) argument
3368 #define VXGE_HAL_RX_QUEUE_START_Q12_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) argument
3370 #define VXGE_HAL_RX_QUEUE_START_Q13_QUEUE_BANKS(val) vBIT(val, 6, 2) argument
3371 #define VXGE_HAL_RX_QUEUE_START_Q13_SBANK(val) vBIT(val, 13, 3) argument
3372 #define VXGE_HAL_RX_QUEUE_START_Q13_SROW(val) vBIT(val, 18, 14) argument
3373 #define VXGE_HAL_RX_QUEUE_START_Q13_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) argument
3375 #define VXGE_HAL_RX_QUEUE_START_Q14_QUEUE_BANKS(val) vBIT(val, 6, 2) argument
3376 #define VXGE_HAL_RX_QUEUE_START_Q14_SBANK(val) vBIT(val, 13, 3) argument
3377 #define VXGE_HAL_RX_QUEUE_START_Q14_SROW(val) vBIT(val, 18, 14) argument
3378 #define VXGE_HAL_RX_QUEUE_START_Q14_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) argument
3380 #define VXGE_HAL_RX_QUEUE_START_Q15_QUEUE_BANKS(val) vBIT(val, 6, 2) argument
3381 #define VXGE_HAL_RX_QUEUE_START_Q15_SBANK(val) vBIT(val, 13, 3) argument
3382 #define VXGE_HAL_RX_QUEUE_START_Q15_SROW(val) vBIT(val, 18, 14) argument
3383 #define VXGE_HAL_RX_QUEUE_START_Q15_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) argument
3385 #define VXGE_HAL_RX_QUEUE_START_Q16_QUEUE_BANKS(val) vBIT(val, 6, 2) argument
3386 #define VXGE_HAL_RX_QUEUE_START_Q16_SBANK(val) vBIT(val, 13, 3) argument
3387 #define VXGE_HAL_RX_QUEUE_START_Q16_SROW(val) vBIT(val, 18, 14) argument
3388 #define VXGE_HAL_RX_QUEUE_START_Q16_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) argument
3390 #define VXGE_HAL_RX_QUEUE_START_Q17_QUEUE_BANKS(val) vBIT(val, 6, 2) argument
3391 #define VXGE_HAL_RX_QUEUE_START_Q17_SBANK(val) vBIT(val, 13, 3) argument
3392 #define VXGE_HAL_RX_QUEUE_START_Q17_SROW(val) vBIT(val, 18, 14) argument
3394 #define VXGE_HAL_FM_DEFINITION_FM_SIZE(val) vBIT(val, 6, 2) argument
3395 #define VXGE_HAL_FM_DEFINITION_FM_COLUMNS(val) vBIT(val, 14, 2) argument
3396 #define VXGE_HAL_FM_DEFINITION_QUEUE_SPAV_MARGIN(val) vBIT(val, 16, 8) argument
3402 #define VXGE_HAL_TRAFFIC_CTRL_OFFLOAD_MAX_FRAMES(val) vBIT(val, 24, 8) argument
3403 #define VXGE_HAL_TRAFFIC_CTRL_NOFFLOAD_MAX_FRAMES(val) vBIT(val, 32, 8) argument
3404 #define VXGE_HAL_TRAFFIC_CTRL_MSP_MAX_FRAMES(val) vBIT(val, 40, 8) argument
3407 #define VXGE_HAL_XFMD_ARB_CTRL_EN_OFF(val) vBIT(val, 15, 17) argument
3408 #define VXGE_HAL_XFMD_ARB_CTRL_EN_NOFF(val) vBIT(val, 39, 17) argument
3410 #define VXGE_HAL_XFMD_ARB_CTRL1_PROMOTE_NOFF(val) vBIT(val, 6, 18) argument
3412 #define VXGE_HAL_RD_TRANC_CTRL_ARB(val) vBIT(val, 4, 4) argument
3414 #define VXGE_HAL_FM_ARB_CTRL(val) vBIT(val, 0, 8) argument
3415 #define VXGE_HAL_FM_ARB_TIMER(val) vBIT(val, 8, 8) argument
3416 #define VXGE_HAL_FM_ARB_EN_QHIST(val) vBIT(val, 16, 8) argument
3417 #define VXGE_HAL_FM_ARB_ACT_ARB_QHIST(val) vBIT(val, 28, 4) argument
3418 #define VXGE_HAL_FM_ARB_QHIST_CNT(val) vBIT(val, 32, 16) argument
3419 #define VXGE_HAL_FM_ARB_WR_DELAY_CNT(val) vBIT(val, 52, 4) argument
3420 #define VXGE_HAL_FM_ARB_WR_WINDOW_CNT(val) vBIT(val, 56, 8) argument
3422 #define VXGE_HAL_ARB_HP_CAL(val) vBIT(val, 0, 8) argument
3423 #define VXGE_HAL_ARB_XFMD_LAST_MASK(val) vBIT(val, 11, 5) argument
3424 #define VXGE_HAL_ARB_HP_XFMD_PRI(val) vBIT(val, 22, 2) argument
3426 #define VXGE_HAL_SETTINGS0_CTRL_FIFO_THR(val) vBIT(val, 4, 4) argument
3428 #define VXGE_HAL_FBMC_ECC_CFG_ENABLE(val) vBIT(val, 3, 5) argument
3500 #define VXGE_HAL_GSSCC_ERR_REG_SSCC_SSR_SG_ERR(val) vBIT(val, 6, 2) argument
3501 #define VXGE_HAL_GSSCC_ERR_REG_SSCC_TSR_SG_ERR(val) vBIT(val, 10, 6) argument
3503 #define VXGE_HAL_GSSCC_ERR_REG_SSCC_SSR_DB_ERR(val) vBIT(val, 38, 2) argument
3504 #define VXGE_HAL_GSSCC_ERR_REG_SSCC_TSR_DB_ERR(val) vBIT(val, 42, 6) argument
3510 #define VXGE_HAL_GSSC_ERR0_REG_SSCC_STATE_SG_ERR(val) vBIT(val, 0, 8) argument
3511 #define VXGE_HAL_GSSC_ERR0_REG_SSCC_CM_RESP_SG_ERR(val) vBIT(val, 12, 4) argument
3512 #define VXGE_HAL_GSSC_ERR0_REG_SSCC_SSR_RESP_SG_ERR(val) vBIT(val, 22, 2) argument
3513 #define VXGE_HAL_GSSC_ERR0_REG_SSCC_TSR_RESP_SG_ERR(val) vBIT(val, 26, 6) argument
3514 #define VXGE_HAL_GSSC_ERR0_REG_SSCC_STATE_DB_ERR(val) vBIT(val, 32, 8) argument
3515 #define VXGE_HAL_GSSC_ERR0_REG_SSCC_CM_RESP_DB_ERR(val) vBIT(val, 44, 4) argument
3516 #define VXGE_HAL_GSSC_ERR0_REG_SSCC_SSR_RESP_DB_ERR(val) vBIT(val, 54, 2) argument
3517 #define VXGE_HAL_GSSC_ERR0_REG_SSCC_TSR_RESP_DB_ERR(val) vBIT(val, 58, 6) argument
3544 #define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CACHE_PB_SG_ERR(val) vBIT(val, 0, 4) argument
3545 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CACHE_PB_SG_ERR(val) vBIT(val, 4, 4) argument
3546 #define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CACHE_PB_DB_ERR(val) vBIT(val, 8, 4) argument
3547 #define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CACHE_PB_DB_ERR(val) vBIT(val, 12, 4) argument
3589 #define VXGE_HAL_SSCC_CONFIG_HIT_SCHASH_INDEX_MSB(val) vBIT(val, 3, 5) argument
3590 #define VXGE_HAL_SSCC_CONFIG_HIT_SCHASH_INDEX_LSB(val) vBIT(val, 11, 5) argument
3591 #define VXGE_HAL_SSCC_CONFIG_TIMEOUT_VALUE(val) vBIT(val, 16, 16) argument
3593 #define VXGE_HAL_SSCC_CONFIG_ALRO_SCHASH_INDEX_MSB(val) vBIT(val, 43, 5) argument
3594 #define VXGE_HAL_SSCC_CONFIG_ALRO_SCHASH_INDEX_LSB(val) vBIT(val, 51, 5) argument
3597 #define VXGE_HAL_SSCC_MASK_0_IPV6_SA_TOP(val) vBIT(val, 0, 64) argument
3599 #define VXGE_HAL_SSCC_MASK_1_IPV6_SA_BOTTOM(val) vBIT(val, 0, 64) argument
3601 #define VXGE_HAL_SSCC_MASK_2_IPV6_DA_TOP(val) vBIT(val, 0, 64) argument
3603 #define VXGE_HAL_SSCC_MASK_3_IPV6_DA_BOTTOM(val) vBIT(val, 0, 64) argument
3605 #define VXGE_HAL_SSCC_MASK_4_IPV4_SA(val) vBIT(val, 0, 32) argument
3606 #define VXGE_HAL_SSCC_MASK_4_IPV4_DA(val) vBIT(val, 32, 32) argument
3608 #define VXGE_HAL_SSCC_MASK_5_TCP_SP(val) vBIT(val, 0, 16) argument
3609 #define VXGE_HAL_SSCC_MASK_5_TCP_DP(val) vBIT(val, 16, 16) argument
3610 #define VXGE_HAL_SSCC_MASK_5_VLANID(val) vBIT(val, 52, 12) argument
3639 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CACHE_PA_SG_ERR(val) vBIT(val, 0, 4) argument
3641 #define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CACHE_PA_DB_ERR(val) vBIT(val, 8, 4) argument
3678 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CACHE_PA_SG_ERR(val) vBIT(val, 0, 4) argument
3679 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPRPEDAT_SG_ERR(val) vBIT(val, 4, 4) argument
3688 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CACHE_PA_DB_ERR(val) vBIT(val, 16, 4) argument
3689 #define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPRPEDAT_DB_ERR(val) vBIT(val, 20, 4) argument
3733 #define VXGE_HAL_QCC_SRQ_CQRQ_POLL_TIMER(val) vBIT(val, 0, 32) argument
3734 #define VXGE_HAL_QCC_SRQ_CQRQ_MAX_EOL_POLLS(val) vBIT(val, 32, 8) argument
3737 #define VXGE_HAL_QCC_ERR_POLICY_CQM_CQE(val) vBIT(val, 4, 4) argument
3738 #define VXGE_HAL_QCC_ERR_POLICY_SQM_WQE(val) vBIT(val, 12, 4) argument
3739 #define VXGE_HAL_QCC_ERR_POLICY_SQM_SRQIR(val) vBIT(val, 22, 2) argument
3745 #define VXGE_HAL_QCC_CQM_CQRQ_ID_CQM_BAD_VPIN_CQRQ_ID(val) vBIT(val, 0, 16) argument
3746 #define VXGE_HAL_QCC_CQM_CQRQ_ID_CQM_BAD_CIN_CQRQ_ID(val) vBIT(val, 16, 16) argument
3747 #define VXGE_HAL_QCC_CQM_CQRQ_ID_CQM_MAX_CQE_GRP_CQRQ_ID(val) vBIT(val, 32, 16) argument
3748 #define VXGE_HAL_QCC_CQM_CQRQ_ID_CQM_CQM_CDR_CQRQ_ID(val) vBIT(val, 48, 16) argument
3750 #define VXGE_HAL_QCC_SQM_SRQ_ID_SQM_BAD_VPIN_SRQ_ID(val) vBIT(val, 0, 16) argument
3751 #define VXGE_HAL_QCC_SQM_SRQ_ID_SQM_BAD_SIN_SRQ_ID(val) vBIT(val, 16, 16) argument
3752 #define VXGE_HAL_QCC_SQM_SRQ_ID_SQM_MAX_WQE_GRP_SRQ_ID(val) vBIT(val, 32, 16) argument
3753 #define VXGE_HAL_QCC_SQM_SRQ_ID_SQM_SQM_WDR_SRQ_ID(val) vBIT(val, 48, 16) argument
3755 #define VXGE_HAL_QCC_CQM_FLM_ID_CQM_CQM_CCM_STATE_SERR(val) vBIT(val, 1, 7) argument
3756 #define VXGE_HAL_QCC_CQM_FLM_ID_CQM_CQM_FLM_HEAD_CQEGRP_ID(val) vBIT(val, 8, 24) argument
3757 #define VXGE_HAL_QCC_CQM_FLM_ID_CQM_CQM_FLM_TAIL_CQEGRP_ID(val)\ argument
3761 #define VXGE_HAL_QCC_SQM_FLM_ID_SQM_SQM_CCM_STATE_SERR(val) vBIT(val, 1, 7) argument
3762 #define VXGE_HAL_QCC_SQM_FLM_ID_SQM_SQM_FLM_HEAD_WQEGRP_ID(val) vBIT(val, 8, 24) argument
3763 #define VXGE_HAL_QCC_SQM_FLM_ID_SQM_SQM_FLM_TAIL_WQEGRP_ID(val)\ argument
3781 #define VXGE_HAL_RPE_ERR_REG_RPE_RCM_PA_DB_ERR(val) vBIT(val, 0, 4) argument
3782 #define VXGE_HAL_RPE_ERR_REG_RPE_RCM_PB_DB_ERR(val) vBIT(val, 4, 4) argument
3787 #define VXGE_HAL_RPE_ERR_REG_RPE_RCM_PA_SG_ERR(val) vBIT(val, 16, 4) argument
3788 #define VXGE_HAL_RPE_ERR_REG_RPE_RCM_PB_SG_ERR(val) vBIT(val, 20, 4) argument
3874 #define VXGE_HAL_RXPE_ERR_REG_RXPE_MSG2RXPE_SG_ERR(val) vBIT(val, 3, 2) argument
3875 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT0_IRAM_SG_ERR(val) vBIT(val, 5, 2) argument
3876 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT1_IRAM_SG_ERR(val) vBIT(val, 7, 2) argument
3877 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT_DRAM_PA_SG_ERR(val) vBIT(val, 9, 2) argument
3878 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT_DRAM_PB_SG_ERR(val) vBIT(val, 11, 2) argument
3884 #define VXGE_HAL_RXPE_ERR_REG_RXPE_MSG2RXPE_DB_ERR(val) vBIT(val, 35, 2) argument
3885 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT0_IRAM_DB_ERR(val) vBIT(val, 37, 2) argument
3886 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT1_IRAM_DB_ERR(val) vBIT(val, 39, 2) argument
3887 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT_DRAM_PA_DB_ERR(val) vBIT(val, 41, 2) argument
3888 #define VXGE_HAL_RXPE_ERR_REG_RXPE_XT_DRAM_PB_DB_ERR(val) vBIT(val, 43, 2) argument
3979 #define VXGE_HAL_TXPE_ERR_REG_TXPE_MSG2TXPE_SG_ERR(val) vBIT(val, 0, 2) argument
3982 #define VXGE_HAL_TXPE_ERR_REG_TXPE_XT_DRAM_SG_ERR(val) vBIT(val, 4, 2) argument
3983 #define VXGE_HAL_TXPE_ERR_REG_TXPE_XT_IRAM_SG_ERR(val) vBIT(val, 6, 2) argument
3991 #define VXGE_HAL_TXPE_ERR_REG_TXPE_MSG2TXPE_DB_ERR(val) vBIT(val, 16, 2) argument
3994 #define VXGE_HAL_TXPE_ERR_REG_TXPE_XT_DRAM_DB_ERR(val) vBIT(val, 20, 2) argument
3995 #define VXGE_HAL_TXPE_ERR_REG_TXPE_XT_IRAM_DB_ERR(val) vBIT(val, 22, 2) argument
4038 #define VXGE_HAL_TXPE_BCC_MEM_SG_ECC_ERR_REG_TXPE_BASE_TXPE_SG_ERR(val)\ argument
4040 #define VXGE_HAL_TXPE_BCC_MEM_SG_ECC_ERR_REG_TXPE_BASE_CDP_SG_ERR(val)\ argument
4045 #define VXGE_HAL_TXPE_BCC_MEM_DB_ECC_ERR_REG_TXPE_BASE_TXPE_DB_ERR(val)\ argument
4047 #define VXGE_HAL_TXPE_BCC_MEM_DB_ECC_ERR_REG_TXPE_BASE_CDP_DB_ERR(val)\ argument
4090 #define VXGE_HAL_SGRP_ALLOC_SGRP_ALLOC(val) vBIT(val, 0, 64) argument
4093 #define VXGE_HAL_SGRP_IWARP_LRO_ALLOC_LAST_IWARP_SGRP(val) vBIT(val, 11, 5) argument
4095 #define VXGE_HAL_RPE_CFG0_RCC_NBR_SLOTS(val) vBIT(val, 3, 5) argument
4096 #define VXGE_HAL_RPE_CFG0_RCC_NBR_FREE_SLOTS(val) vBIT(val, 11, 5) argument
4098 #define VXGE_HAL_RPE_CFG0_LL_SEND_MAX_SIZE(val) vBIT(val, 24, 8) argument
4116 #define VXGE_HAL_RPE_CFG1_DLM_RCMD_MAX_CREDITS(val) vBIT(val, 10, 6) argument
4117 #define VXGE_HAL_RPE_CFG1_MSG_RCMD_MAX_CREDITS(val) vBIT(val, 18, 6) argument
4118 #define VXGE_HAL_RPE_CFG1_PDM_RCMD_MAX_CREDITS(val) vBIT(val, 25, 7) argument
4119 #define VXGE_HAL_RPE_CFG1_RCQ_MAX_CREDITS(val) vBIT(val, 32, 8) argument
4120 #define VXGE_HAL_RPE_CFG1_RCQ_DLM_PRI(val) vBIT(val, 46, 2) argument
4121 #define VXGE_HAL_RPE_CFG1_RCQ_MSG_PRI(val) vBIT(val, 54, 2) argument
4122 #define VXGE_HAL_RPE_CFG1_RCQ_PDM_PRI(val) vBIT(val, 62, 2) argument
4124 #define VXGE_HAL_RPE_CFG2_RCQ_ARB_CAL0_PRI(val) vBIT(val, 6, 2) argument
4125 #define VXGE_HAL_RPE_CFG2_RCQ_ARB_CAL1_PRI(val) vBIT(val, 14, 2) argument
4126 #define VXGE_HAL_RPE_CFG2_RCQ_ARB_CAL2_PRI(val) vBIT(val, 22, 2) argument
4127 #define VXGE_HAL_RPE_CFG2_RCQ_ARB_CAL3_PRI(val) vBIT(val, 30, 2) argument
4128 #define VXGE_HAL_RPE_CFG2_RCQ_ARB_CAL4_PRI(val) vBIT(val, 38, 2) argument
4129 #define VXGE_HAL_RPE_CFG2_RCQ_ARB_CAL5_PRI(val) vBIT(val, 46, 2) argument
4157 #define VXGE_HAL_WQEOWN0_RPE_LRO_CTR(val) vBIT(val, 13, 19) argument
4158 #define VXGE_HAL_WQEOWN0_RPE_BS_CTR(val) vBIT(val, 45, 19) argument
4160 #define VXGE_HAL_WQEOWN1_RPE_IWARP_CTR(val) vBIT(val, 13, 19) argument
4162 #define VXGE_HAL_RPE_WQEOWN2_LRO_THRESHOLD(val) vBIT(val, 13, 19) argument
4163 #define VXGE_HAL_RPE_WQEOWN2_BS_THRESHOLD(val) vBIT(val, 45, 19) argument
4168 #define VXGE_HAL_PE_CTXT_S1_SIZE(val) vBIT(val, 10, 6) argument
4169 #define VXGE_HAL_PE_CTXT_S2_SIZE(val) vBIT(val, 26, 6) argument
4170 #define VXGE_HAL_PE_CTXT_S3_SIZE(val) vBIT(val, 42, 6) argument
4179 #define VXGE_HAL_PE_CFG_MAX_RXB2B(val) vBIT(val, 56, 8) argument
4183 #define VXGE_HAL_PE_STATS_CMD_ADDRESS(val) vBIT(val, 21, 11) argument
4185 #define VXGE_HAL_PE_STATS_DATA_PE_RETURNED(val) vBIT(val, 0, 64) argument
4187 #define VXGE_HAL_RXPE_FP_MASK_RXPE_FP_MASK(val) vBIT(val, 18, 46) argument
4192 #define VXGE_HAL_PE_XT_CTRL1_IRAM_ADDRESS(val) vBIT(val, 4, 12) argument
4210 #define VXGE_HAL_PE_XT_CTRL2_IRAM_WRITE_DATA(val) vBIT(val, 0, 64) argument
4214 #define VXGE_HAL_PE_XT_CTRL4_PE_IRAM_READ_DATA(val) vBIT(val, 0, 64) argument
4216 #define VXGE_HAL_PET_IWARP_COUNTERS_MASTER(val) vBIT(val, 0, 32) argument
4217 #define VXGE_HAL_PET_IWARP_COUNTERS_INTERVAL(val) vBIT(val, 40, 24) argument
4219 #define VXGE_HAL_PET_IWARP_SLOW_COUNTER_MASTER(val) vBIT(val, 0, 32) argument
4221 #define VXGE_HAL_PET_IWARP_TIMERS_TCP_NOW(val) vBIT(val, 0, 32) argument
4222 #define VXGE_HAL_PET_IWARP_TIMERS_TCP_SLOW_CLK(val) vBIT(val, 32, 32) argument
4224 #define VXGE_HAL_PET_LRO_CFG_START_VALUE(val) vBIT(val, 6, 2) argument
4226 #define VXGE_HAL_PET_LRO_COUNTERS_MASTER(val) vBIT(val, 0, 32) argument
4227 #define VXGE_HAL_PET_LRO_COUNTERS_INTERVAL(val) vBIT(val, 40, 24) argument
4234 #define VXGE_HAL_PE_VP_ACK_BLK_LIMIT(val) vBIT(val, 32, 32) argument
4236 #define VXGE_HAL_PE_VP_RIRR_BLK_LIMIT(val) vBIT(val, 0, 32) argument
4237 #define VXGE_HAL_PE_VP_LIRR_BLK_LIMIT(val) vBIT(val, 32, 32) argument
4240 #define VXGE_HAL_DLM_CFG_ACK_PTR_AE_LEVEL(val) vBIT(val, 12, 4) argument
4242 #define VXGE_HAL_DLM_CFG_LIRR_PTR_AE_LEVEL(val) vBIT(val, 28, 4) argument
4243 #define VXGE_HAL_DLM_CFG_RIRR_PTR_AE_LEVEL(val) vBIT(val, 44, 4) argument
4247 #define VXGE_HAL_TXPE_TOWI_CFG_TOWI_CACHE_SIZE(val) vBIT(val, 48, 8) argument
4248 #define VXGE_HAL_TXPE_TOWI_CFG_TOWI_DMA_THRESHOLD(val) vBIT(val, 56, 8) argument
4253 #define VXGE_HAL_TXPE_PMON_SAMPLE_PERIOD(val) vBIT(val, 16, 48) argument
4255 #define VXGE_HAL_TXPE_PMON_DOWNCOUNT_TXPE_REMAINDER(val) vBIT(val, 16, 48) argument
4257 #define VXGE_HAL_TXPE_PMON_EVENT_TXPE_STALL_CNT(val) vBIT(val, 16, 48) argument
4259 #define VXGE_HAL_TXPE_PMON_OTHER_TXPE_STALL_CNT(val) vBIT(val, 16, 48) argument
4263 #define VXGE_HAL_OES_INEVT_PRIORITY_0(val) vBIT(val, 5, 3) argument
4264 #define VXGE_HAL_OES_INEVT_PRIORITY_1(val) vBIT(val, 13, 3) argument
4265 #define VXGE_HAL_OES_INEVT_PRIORITY_2(val) vBIT(val, 21, 3) argument
4266 #define VXGE_HAL_OES_INEVT_PRIORITY_3(val) vBIT(val, 29, 3) argument
4267 #define VXGE_HAL_OES_INEVT_PRIORITY_4(val) vBIT(val, 37, 3) argument
4270 #define VXGE_HAL_OES_INBKBKEVT_PRIORITY_0(val) vBIT(val, 5, 3) argument
4271 #define VXGE_HAL_OES_INBKBKEVT_PRIORITY_1(val) vBIT(val, 13, 3) argument
4272 #define VXGE_HAL_OES_INBKBKEVT_PRIORITY_2(val) vBIT(val, 21, 3) argument
4273 #define VXGE_HAL_OES_INBKBKEVT_PRIORITY_3(val) vBIT(val, 29, 3) argument
4274 #define VXGE_HAL_OES_INBKBKEVT_PRIORITY_4(val) vBIT(val, 37, 3) argument
4276 #define VXGE_HAL_OES_INEVT_WRR0_SS_0(val) vBIT(val, 5, 3) argument
4277 #define VXGE_HAL_OES_INEVT_WRR0_SS_1(val) vBIT(val, 13, 3) argument
4278 #define VXGE_HAL_OES_INEVT_WRR0_SS_2(val) vBIT(val, 21, 3) argument
4279 #define VXGE_HAL_OES_INEVT_WRR0_SS_3(val) vBIT(val, 29, 3) argument
4280 #define VXGE_HAL_OES_INEVT_WRR0_SS_4(val) vBIT(val, 37, 3) argument
4281 #define VXGE_HAL_OES_INEVT_WRR0_SS_5(val) vBIT(val, 45, 3) argument
4282 #define VXGE_HAL_OES_INEVT_WRR0_SS_6(val) vBIT(val, 53, 3) argument
4283 #define VXGE_HAL_OES_INEVT_WRR0_SS_7(val) vBIT(val, 61, 3) argument
4285 #define VXGE_HAL_OES_INEVT_WRR1_SS_8(val) vBIT(val, 5, 3) argument
4286 #define VXGE_HAL_OES_INEVT_WRR1_SS_9(val) vBIT(val, 13, 3) argument
4287 #define VXGE_HAL_OES_INEVT_WRR1_SS_10(val) vBIT(val, 21, 3) argument
4288 #define VXGE_HAL_OES_INEVT_WRR1_SS_11(val) vBIT(val, 29, 3) argument
4289 #define VXGE_HAL_OES_INEVT_WRR1_SS_12(val) vBIT(val, 37, 3) argument
4290 #define VXGE_HAL_OES_INEVT_WRR1_SS_13(val) vBIT(val, 45, 3) argument
4291 #define VXGE_HAL_OES_INEVT_WRR1_SS_14(val) vBIT(val, 53, 3) argument
4293 #define VXGE_HAL_OES_PENDEVT_PRIORITY_0(val) vBIT(val, 5, 3) argument
4294 #define VXGE_HAL_OES_PENDEVT_PRIORITY_1(val) vBIT(val, 13, 3) argument
4295 #define VXGE_HAL_OES_PENDEVT_PRIORITY_2(val) vBIT(val, 21, 3) argument
4296 #define VXGE_HAL_OES_PENDEVT_PRIORITY_3(val) vBIT(val, 29, 3) argument
4297 #define VXGE_HAL_OES_PENDEVT_PRIORITY_4(val) vBIT(val, 37, 3) argument
4300 #define VXGE_HAL_OES_PENDBKBKEVT_PRIORITY_0(val) vBIT(val, 5, 3) argument
4301 #define VXGE_HAL_OES_PENDBKBKEVT_PRIORITY_1(val) vBIT(val, 13, 3) argument
4302 #define VXGE_HAL_OES_PENDBKBKEVT_PRIORITY_2(val) vBIT(val, 21, 3) argument
4303 #define VXGE_HAL_OES_PENDBKBKEVT_PRIORITY_3(val) vBIT(val, 29, 3) argument
4304 #define VXGE_HAL_OES_PENDBKBKEVT_PRIORITY_4(val) vBIT(val, 37, 3) argument
4306 #define VXGE_HAL_OES_PENDEVT_WRR0_SS_0(val) vBIT(val, 5, 3) argument
4307 #define VXGE_HAL_OES_PENDEVT_WRR0_SS_1(val) vBIT(val, 13, 3) argument
4308 #define VXGE_HAL_OES_PENDEVT_WRR0_SS_2(val) vBIT(val, 21, 3) argument
4309 #define VXGE_HAL_OES_PENDEVT_WRR0_SS_3(val) vBIT(val, 29, 3) argument
4310 #define VXGE_HAL_OES_PENDEVT_WRR0_SS_4(val) vBIT(val, 37, 3) argument
4311 #define VXGE_HAL_OES_PENDEVT_WRR0_SS_5(val) vBIT(val, 45, 3) argument
4312 #define VXGE_HAL_OES_PENDEVT_WRR0_SS_6(val) vBIT(val, 53, 3) argument
4313 #define VXGE_HAL_OES_PENDEVT_WRR0_SS_7(val) vBIT(val, 61, 3) argument
4315 #define VXGE_HAL_OES_PENDEVT_WRR1_SS_8(val) vBIT(val, 5, 3) argument
4316 #define VXGE_HAL_OES_PENDEVT_WRR1_SS_9(val) vBIT(val, 13, 3) argument
4317 #define VXGE_HAL_OES_PENDEVT_WRR1_SS_10(val) vBIT(val, 21, 3) argument
4318 #define VXGE_HAL_OES_PENDEVT_WRR1_SS_11(val) vBIT(val, 29, 3) argument
4319 #define VXGE_HAL_OES_PENDEVT_WRR1_SS_12(val) vBIT(val, 37, 3) argument
4320 #define VXGE_HAL_OES_PENDEVT_WRR1_SS_13(val) vBIT(val, 45, 3) argument
4321 #define VXGE_HAL_OES_PENDEVT_WRR1_SS_14(val) vBIT(val, 53, 3) argument
4323 #define VXGE_HAL_OES_PEND_QUEUE_RX_PEND_THRESHOLD(val) vBIT(val, 27, 5) argument
4324 #define VXGE_HAL_OES_PEND_QUEUE_TX_PEND_THRESHOLD(val) vBIT(val, 57, 7) argument
4328 #define VXGE_HAL_ROCRC_BYPQ0_STAT_WATERMARK_RCQ_ROCRC_BYPQ0_STAT_WATERMARK(val)\ argument
4331 #define VXGE_HAL_ROCRC_BYPQ1_STAT_WATERMARK_RCQ_ROCRC_BYPQ1_STAT_WATERMARK(val)\ argument
4334 #define VXGE_HAL_ROCRC_BYPQ2_STAT_WATERMARK_RCQ_ROCRC_BYPQ2_STAT_WATERMARK(val)\ argument
4339 #define VXGE_HAL_RC_CFG2_BUFF1_SIZE(val) vBIT(val, 0, 16) argument
4340 #define VXGE_HAL_RC_CFG2_BUFF2_SIZE(val) vBIT(val, 16, 16) argument
4341 #define VXGE_HAL_RC_CFG2_BUFF3_SIZE(val) vBIT(val, 32, 16) argument
4342 #define VXGE_HAL_RC_CFG2_BUFF4_SIZE(val) vBIT(val, 48, 16) argument
4344 #define VXGE_HAL_RC_CFG3_BUFF5_SIZE(val) vBIT(val, 0, 16) argument
4347 #define VXGE_HAL_RX_MULTI_CAST_CTRL1_DELAY_COUNT(val) vBIT(val, 11, 5) argument
4349 #define VXGE_HAL_RXDM_DBG_RD_ADDR(val) vBIT(val, 0, 12) argument
4352 #define VXGE_HAL_RXDM_DBG_RD_DATA_RMC_RXDM_DBG_RD_DATA(val) vBIT(val, 0, 64) argument
4354 #define VXGE_HAL_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH(val) vBIT(val, 59, 5) argument
4368 #define VXGE_HAL_TIM_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT(val) vBIT(val, 0, 32) argument
4370 #define VXGE_HAL_TIM_BMAP_MAPPING_VP_ERR_TIM_DEST_VPATH(val) vBIT(val, 3, 5) argument
4379 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_MEM_DB_ERR(val) vBIT(val, 0, 4) argument
4380 #define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_MEM_SG_ERR(val) vBIT(val, 4, 4) argument
4423 #define VXGE_HAL_CMC_L2_CLIENT_UQM_1_NUMBER(val) vBIT(val, 5, 3) argument
4425 #define VXGE_HAL_CMC_L2_CLIENT_SSC_L_NUMBER(val) vBIT(val, 5, 3) argument
4427 #define VXGE_HAL_CMC_L2_CLIENT_QCC_SQM_0_NUMBER(val) vBIT(val, 5, 3) argument
4429 #define VXGE_HAL_CMC_L2_CLIENT_DAM_0_NUMBER(val) vBIT(val, 5, 3) argument
4431 #define VXGE_HAL_CMC_L2_CLIENT_H2L_0_NUMBER(val) vBIT(val, 5, 3) argument
4433 #define VXGE_HAL_CMC_L2_CLIENT_STC_0_NUMBER(val) vBIT(val, 5, 3) argument
4435 #define VXGE_HAL_CMC_L2_CLIENT_XTMC_0_NUMBER(val) vBIT(val, 5, 3) argument
4437 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_0(val) vBIT(val, 5, 3) argument
4438 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_1(val) vBIT(val, 13, 3) argument
4439 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_2(val) vBIT(val, 21, 3) argument
4440 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_3(val) vBIT(val, 29, 3) argument
4441 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_4(val) vBIT(val, 37, 3) argument
4442 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_5(val) vBIT(val, 45, 3) argument
4443 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_6(val) vBIT(val, 53, 3) argument
4444 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_7(val) vBIT(val, 61, 3) argument
4446 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_8(val) vBIT(val, 5, 3) argument
4447 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_9(val) vBIT(val, 13, 3) argument
4448 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_10(val) vBIT(val, 21, 3) argument
4449 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_11(val) vBIT(val, 29, 3) argument
4450 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_12(val) vBIT(val, 37, 3) argument
4451 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_13(val) vBIT(val, 45, 3) argument
4452 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_14(val) vBIT(val, 53, 3) argument
4453 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_15(val) vBIT(val, 61, 3) argument
4455 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_16(val) vBIT(val, 5, 3) argument
4456 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_17(val) vBIT(val, 13, 3) argument
4457 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_18(val) vBIT(val, 21, 3) argument
4458 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_19(val) vBIT(val, 29, 3) argument
4459 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_20(val) vBIT(val, 37, 3) argument
4460 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_21(val) vBIT(val, 45, 3) argument
4461 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_22(val) vBIT(val, 53, 3) argument
4462 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_23(val) vBIT(val, 61, 3) argument
4464 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_3_NUMBER_24(val) vBIT(val, 5, 3) argument
4465 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_3_NUMBER_25(val) vBIT(val, 13, 3) argument
4466 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_3_NUMBER_26(val) vBIT(val, 21, 3) argument
4467 #define VXGE_HAL_CMC_WRR_L2_CALENDAR_3_NUMBER_27(val) vBIT(val, 29, 3) argument
4469 #define VXGE_HAL_CMC_L3_CLIENT_QCC_SQM_1_NUMBER(val) vBIT(val, 5, 3) argument
4471 #define VXGE_HAL_CMC_L3_CLIENT_QCC_CQM_NUMBER(val) vBIT(val, 5, 3) argument
4473 #define VXGE_HAL_CMC_L3_CLIENT_DAM_1_NUMBER(val) vBIT(val, 5, 3) argument
4475 #define VXGE_HAL_CMC_L3_CLIENT_H2L_1_NUMBER(val) vBIT(val, 5, 3) argument
4477 #define VXGE_HAL_CMC_L3_CLIENT_STC_1_NUMBER(val) vBIT(val, 5, 3) argument
4479 #define VXGE_HAL_CMC_L3_CLIENT_XTMC_1_NUMBER(val) vBIT(val, 5, 3) argument
4481 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_0(val) vBIT(val, 5, 3) argument
4482 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_1(val) vBIT(val, 13, 3) argument
4483 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_2(val) vBIT(val, 21, 3) argument
4484 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_3(val) vBIT(val, 29, 3) argument
4485 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_4(val) vBIT(val, 37, 3) argument
4486 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_5(val) vBIT(val, 45, 3) argument
4487 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_6(val) vBIT(val, 53, 3) argument
4488 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_7(val) vBIT(val, 61, 3) argument
4490 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_8(val) vBIT(val, 5, 3) argument
4491 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_9(val) vBIT(val, 13, 3) argument
4492 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_10(val) vBIT(val, 21, 3) argument
4493 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_11(val) vBIT(val, 29, 3) argument
4494 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_12(val) vBIT(val, 37, 3) argument
4495 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_13(val) vBIT(val, 45, 3) argument
4496 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_14(val) vBIT(val, 53, 3) argument
4497 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_15(val) vBIT(val, 61, 3) argument
4499 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_2_NUMBER_16(val) vBIT(val, 5, 3) argument
4500 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_2_NUMBER_17(val) vBIT(val, 13, 3) argument
4501 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_2_NUMBER_18(val) vBIT(val, 21, 3) argument
4502 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_2_NUMBER_19(val) vBIT(val, 29, 3) argument
4503 #define VXGE_HAL_CMC_WRR_L3_CALENDAR_2_NUMBER_20(val) vBIT(val, 37, 3) argument
4505 #define VXGE_HAL_CMC_USER_DOORBELL_PARTITION_BASE(val) vBIT(val, 8, 24) argument
4507 #define VXGE_HAL_CMC_HIT_RECORD_PARTITION_0_BASE(val) vBIT(val, 8, 24) argument
4509 #define VXGE_HAL_CMC_HIT_RECORD_PARTITION_1_BASE(val) vBIT(val, 8, 24) argument
4511 #define VXGE_HAL_CMC_HIT_RECORD_PARTITION_2_BASE(val) vBIT(val, 8, 24) argument
4513 #define VXGE_HAL_CMC_HIT_RECORD_PARTITION_3_BASE(val) vBIT(val, 8, 24) argument
4515 #define VXGE_HAL_CMC_HIT_RECORD_PARTITION_4_BASE(val) vBIT(val, 8, 24) argument
4517 #define VXGE_HAL_CMC_HIT_RECORD_PARTITION_5_BASE(val) vBIT(val, 8, 24) argument
4519 #define VXGE_HAL_CMC_HIT_RECORD_PARTITION_6_BASE(val) vBIT(val, 8, 24) argument
4521 #define VXGE_HAL_CMC_HIT_RECORD_PARTITION_7_BASE(val) vBIT(val, 8, 24) argument
4523 #define VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_0_BASE(val) vBIT(val, 8, 24) argument
4525 #define VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_1_BASE(val) vBIT(val, 8, 24) argument
4527 #define VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_2_BASE(val) vBIT(val, 8, 24) argument
4529 #define VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_3_BASE(val) vBIT(val, 8, 24) argument
4531 #define VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_4_BASE(val) vBIT(val, 8, 24) argument
4533 #define VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_5_BASE(val) vBIT(val, 8, 24) argument
4535 #define VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_6_BASE(val) vBIT(val, 8, 24) argument
4537 #define VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_7_BASE(val) vBIT(val, 8, 24) argument
4539 #define VXGE_HAL_CMC_WQE_OD_GROUP_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) argument
4541 #define VXGE_HAL_CMC_ACK_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) argument
4543 #define VXGE_HAL_CMC_LIRR_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) argument
4545 #define VXGE_HAL_CMC_RIRR_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) argument
4547 #define VXGE_HAL_CMC_TCE_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) argument
4549 #define VXGE_HAL_CMC_HOQ_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) argument
4551 #define VXGE_HAL_CMC_STAG_VP_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) argument
4553 #define VXGE_HAL_CMC_R_SCR_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) argument
4555 #define VXGE_HAL_CMC_CQRQ_CONTEXT_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) argument
4557 #define VXGE_HAL_CMC_CQE_GROUP_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) argument
4559 #define VXGE_HAL_CMC_P_SCR_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) argument
4561 #define VXGE_HAL_CMC_NCE_CONTEXT_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) argument
4563 #define VXGE_HAL_CMC_BYPASS_QUEUE_PARTITION_BASE(val) vBIT(val, 8, 24) argument
4565 #define VXGE_HAL_CMC_H_SCR_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) argument
4567 #define VXGE_HAL_CMC_PBL_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) argument
4569 #define VXGE_HAL_CMC_LIT_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) argument
4571 #define VXGE_HAL_CMC_SRQ_CONTEXT_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) argument
4573 #define VXGE_HAL_CMC_P_SCR_RECORD_SIZE(val) vBIT(val, 2, 6) argument
4575 #define VXGE_HAL_CMC_DEVICE_SELECT_CODE(val) vBIT(val, 5, 3) argument
4577 #define VXGE_HAL_G3IF_FIFO_DST_ECC_ENABLE(val) vBIT(val, 3, 5) argument
4583 #define VXGE_HAL_GXTMC_CFG_GPSYNC_CNTDOWN_START_VALUE(val) vBIT(val, 20, 4) argument
4593 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_DB_ERR(val) vBIT(val, 0, 2) argument
4646 #define VXGE_HAL_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_SG_ERR(val) vBIT(val, 54, 2) argument
4652 #define VXGE_HAL_CP_ERR_REG_CP_CP_DCACHE_SG_ERR(val) vBIT(val, 0, 8) argument
4653 #define VXGE_HAL_CP_ERR_REG_CP_CP_ICACHE_SG_ERR(val) vBIT(val, 8, 2) argument
4660 #define VXGE_HAL_CP_ERR_REG_CP_STC2CP_SG_ERR(val) vBIT(val, 16, 2) argument
4661 #define VXGE_HAL_CP_ERR_REG_CP_CP_DCACHE_DB_ERR(val) vBIT(val, 24, 8) argument
4662 #define VXGE_HAL_CP_ERR_REG_CP_CP_ICACHE_DB_ERR(val) vBIT(val, 32, 2) argument
4669 #define VXGE_HAL_CP_ERR_REG_CP_STC2CP_DB_ERR(val) vBIT(val, 40, 2) argument
4702 #define VXGE_HAL_CP_EXC_CAUSE_CP_CP_CAUSE(val) vBIT(val, 32, 32) argument
4706 #define VXGE_HAL_XTMC_IMG_CTRL0_LD_BANK_DEPTH(val) vBIT(val, 5, 3) argument
4710 #define VXGE_HAL_XTMC_IMG_CTRL0_ADDR(val) vBIT(val, 40, 24) argument
4712 #define VXGE_HAL_XTMC_IMG_CTRL1_DATA(val) vBIT(val, 0, 64) argument
4733 #define VXGE_HAL_PXTMC_CFG1_MAX_NBR_MXP_EVENTS(val) vBIT(val, 6, 2) argument
4734 #define VXGE_HAL_PXTMC_CFG1_MAX_NBR_UXP_EVENTS(val) vBIT(val, 14, 2) argument
4735 #define VXGE_HAL_PXTMC_CFG1_MAX_NBR_CXP_EVENTS(val) vBIT(val, 22, 2) argument
4739 #define VXGE_HAL_PXTMC_CFG1_PGSYNC_CNTDOWN_START_VALUE(val) vBIT(val, 36, 4) argument
4741 #define VXGE_HAL_XTMC_MEM_CFG_CTXT_MEM_SPARSE_BASE(val) vBIT(val, 5, 3) argument
4742 #define VXGE_HAL_XTMC_MEM_CFG_CTXT_MEM_PACKED_BASE(val) vBIT(val, 13, 3) argument
4743 #define VXGE_HAL_XTMC_MEM_CFG_SHARED_SRAM_BASE(val) vBIT(val, 21, 3) argument
4744 #define VXGE_HAL_XTMC_MEM_CFG_CTXT_MEM_SIZE(val) vBIT(val, 29, 3) argument
4745 #define VXGE_HAL_XTMC_MEM_CFG_SRAM_SPARSE_BASE_ADDR(val) vBIT(val, 32, 16) argument
4746 #define VXGE_HAL_XTMC_MEM_CFG_SRAM_PACKED_BASE_ADDR(val) vBIT(val, 48, 16) argument
4748 #define VXGE_HAL_XTMC_MEM_BYPASS_CFG_CTXT_MEM_SPARSE_BASE(val) vBIT(val, 5, 3) argument
4749 #define VXGE_HAL_XTMC_MEM_BYPASS_CFG_CTXT_MEM_PACKED_BASE(val) vBIT(val, 13, 3) argument
4750 #define VXGE_HAL_XTMC_MEM_BYPASS_CFG_SHARED_SRAM_BASE(val) vBIT(val, 21, 3) argument
4752 #define VXGE_HAL_XTMC_CXP_REGION0_START_ADDR(val) vBIT(val, 0, 32) argument
4753 #define VXGE_HAL_XTMC_CXP_REGION0_END_ADDR(val) vBIT(val, 32, 32) argument
4755 #define VXGE_HAL_XTMC_MXP_REGION0_START_ADDR(val) vBIT(val, 0, 32) argument
4756 #define VXGE_HAL_XTMC_MXP_REGION0_END_ADDR(val) vBIT(val, 32, 32) argument
4758 #define VXGE_HAL_XTMC_UXP_REGION0_START_ADDR(val) vBIT(val, 0, 32) argument
4759 #define VXGE_HAL_XTMC_UXP_REGION0_END_ADDR(val) vBIT(val, 32, 32) argument
4761 #define VXGE_HAL_XTMC_CXP_REGION1_START_ADDR(val) vBIT(val, 0, 32) argument
4762 #define VXGE_HAL_XTMC_CXP_REGION1_END_ADDR(val) vBIT(val, 32, 32) argument
4764 #define VXGE_HAL_XTMC_MXP_REGION1_START_ADDR(val) vBIT(val, 0, 32) argument
4765 #define VXGE_HAL_XTMC_MXP_REGION1_END_ADDR(val) vBIT(val, 32, 32) argument
4767 #define VXGE_HAL_XTMC_UXP_REGION1_START_ADDR(val) vBIT(val, 0, 32) argument
4768 #define VXGE_HAL_XTMC_UXP_REGION1_END_ADDR(val) vBIT(val, 32, 32) argument
4770 #define VXGE_HAL_XTMC_CXP_REGION2_START_ADDR(val) vBIT(val, 0, 32) argument
4771 #define VXGE_HAL_XTMC_CXP_REGION2_END_ADDR(val) vBIT(val, 32, 32) argument
4773 #define VXGE_HAL_XTMC_MXP_REGION2_START_ADDR(val) vBIT(val, 0, 32) argument
4774 #define VXGE_HAL_XTMC_MXP_REGION2_END_ADDR(val) vBIT(val, 32, 32) argument
4776 #define VXGE_HAL_XTMC_UXP_REGION2_START_ADDR(val) vBIT(val, 0, 32) argument
4777 #define VXGE_HAL_XTMC_UXP_REGION2_END_ADDR(val) vBIT(val, 32, 32) argument
4869 #define VXGE_HAL_MSG_DISPATCH_VPATH_CUTOFF(val) vBIT(val, 59, 5) argument
4882 #define VXGE_HAL_MSG_EXC_CAUSE_MP_MXP(val) vBIT(val, 0, 32) argument
4883 #define VXGE_HAL_MSG_EXC_CAUSE_UP_UXP(val) vBIT(val, 32, 32) argument
4889 #define VXGE_HAL_MSG_DIRECT_PIC_UMQ_VPA(val) vBIT(val, 59, 5) argument
4891 #define VXGE_HAL_UMQ_IR_TEST_VPA_NUMBER(val) vBIT(val, 0, 5) argument
4893 #define VXGE_HAL_UMQ_IR_TEST_BYTE_VALUE_START(val) vBIT(val, 0, 32) argument
4994 #define VXGE_HAL_UMQ_BWR_PFCH_INIT_NUMBER(val) vBIT(val, 0, 8) argument
4998 #define VXGE_HAL_UMQ_BWR_EOL_POLL_LATENCY(val) vBIT(val, 32, 32) argument
5013 #define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_SG_ERR(val)\ argument
5015 #define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_DB_ERR(val)\ argument
5019 #define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_SG_ERR(val)\ argument
5021 #define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_DB_ERR(val)\ argument
5025 #define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_SG_ERR(val)\ argument
5027 #define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_DB_ERR(val)\ argument
5029 #define VXGE_HAL_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_SG_ERR(val) vBIT(val, 18, 2) argument
5030 #define VXGE_HAL_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_DB_ERR(val) vBIT(val, 20, 2) argument
5037 #define VXGE_HAL_FAU_GLOBAL_CFG_ARB_ALG(val) vBIT(val, 2, 2) argument
5039 #define VXGE_HAL_RX_DATAPATH_UTIL_FAU_RX_UTILIZATION(val) vBIT(val, 7, 9) argument
5040 #define VXGE_HAL_RX_DATAPATH_UTIL_RX_UTIL_CFG(val) vBIT(val, 16, 4) argument
5041 #define VXGE_HAL_RX_DATAPATH_UTIL_FAU_RX_FRAC_UTIL(val) vBIT(val, 20, 4) argument
5042 #define VXGE_HAL_RX_DATAPATH_UTIL_RX_PKT_WEIGHT(val) vBIT(val, 24, 4) argument
5050 #define VXGE_HAL_DBG_STATS_FAU_RX_PATH_RX_PERMITTED_FRMS(val) vBIT(val, 32, 32) argument
5053 #define VXGE_HAL_FAU_AUTO_LRO_CONTROL_FRAME_COUNT(val) vBIT(val, 8, 24) argument
5054 #define VXGE_HAL_FAU_AUTO_LRO_CONTROL_TIMER_VALUE(val) vBIT(val, 32, 32) argument
5056 #define VXGE_HAL_FAU_AUTO_LRO_DATA_0_SOURCE_VPATH(val) vBIT(val, 3, 5) argument
5059 #define VXGE_HAL_FAU_AUTO_LRO_DATA_0_VLAN_VID(val) vBIT(val, 20, 12) argument
5060 #define VXGE_HAL_FAU_AUTO_LRO_DATA_0_TCP_DEST_PORT(val) vBIT(val, 32, 16) argument
5061 #define VXGE_HAL_FAU_AUTO_LRO_DATA_0_TCP_SOURCE_PORT(val) vBIT(val, 48, 16) argument
5063 #define VXGE_HAL_FAU_AUTO_LRO_DATA_1_IP_SOURCE_ADDR_0(val) vBIT(val, 0, 64) argument
5065 #define VXGE_HAL_FAU_AUTO_LRO_DATA_2_IP_SOURCE_ADDR_1(val) vBIT(val, 0, 64) argument
5067 #define VXGE_HAL_FAU_AUTO_LRO_DATA_3_IP_DEST_ADDR_0(val) vBIT(val, 0, 64) argument
5069 #define VXGE_HAL_FAU_AUTO_LRO_DATA_4_IP_DEST_ADDR_1(val) vBIT(val, 0, 64) argument
5073 #define VXGE_HAL_FAU_LAG_CFG_COLL_ALG(val) vBIT(val, 2, 2) argument
5083 #define VXGE_HAL_XMAC_RX_XGMII_CAPTURE_DATA_PORT_COL_INDX(val) vBIT(val, 0, 12) argument
5084 #define VXGE_HAL_XMAC_RX_XGMII_CAPTURE_DATA_PORT_FAUJ_FLAG(val) vBIT(val, 26, 2) argument
5085 #define VXGE_HAL_XMAC_RX_XGMII_CAPTURE_DATA_PORT_FAUJ_RXC(val) vBIT(val, 28, 4) argument
5086 #define VXGE_HAL_XMAC_RX_XGMII_CAPTURE_DATA_PORT_FAUJ_RXD(val) vBIT(val, 32, 32) argument
5114 #define VXGE_HAL_PTM_ALARM_REG_PTM_FRMM_ECC_DB_ERR(val) vBIT(val, 18, 2) argument
5115 #define VXGE_HAL_PTM_ALARM_REG_PTM_FRMM_ECC_SG_ERR(val) vBIT(val, 22, 2) argument
5128 #define VXGE_HAL_TX_DATAPATH_UTIL_TPA_TX_UTILIZATION(val) vBIT(val, 7, 9) argument
5129 #define VXGE_HAL_TX_DATAPATH_UTIL_TX_UTIL_CFG(val) vBIT(val, 16, 4) argument
5130 #define VXGE_HAL_TX_DATAPATH_UTIL_TPA_TX_FRAC_UTIL(val) vBIT(val, 20, 4) argument
5131 #define VXGE_HAL_TX_DATAPATH_UTIL_TX_PKT_WEIGHT(val) vBIT(val, 24, 4) argument
5133 #define VXGE_HAL_ORP_CFG_FIFO_CREDITS(val) vBIT(val, 5, 3) argument
5142 #define VXGE_HAL_ORP_LRO_EVENTS_ORP_LRO_EVENTS(val) vBIT(val, 0, 64) argument
5144 #define VXGE_HAL_ORP_BS_EVENTS_ORP_BS_EVENTS(val) vBIT(val, 0, 64) argument
5146 #define VXGE_HAL_ORP_IWARP_EVENTS_ORP_IWARP_EVENTS(val) vBIT(val, 0, 64) argument
5148 #define VXGE_HAL_DBG_STATS_TPA_TX_PATH_TX_PERMITTED_FRMS(val) vBIT(val, 32, 32) argument
5182 #define VXGE_HAL_TXMAC_GEN_CFG1_IFS_STRETCH_RATIO(val) vBIT(val, 40, 16) argument
5183 #define VXGE_HAL_TXMAC_GEN_CFG1_IFS_NUM_EXTENSION(val) vBIT(val, 59, 5) argument
5187 #define VXGE_HAL_TXMAC_ERR_INJECT_CFG_INJECTOR_ERROR_RATE(val) vBIT(val, 0, 32) argument
5190 #define VXGE_HAL_TXMAC_FRMGEN_CFG_MODE(val) vBIT(val, 6, 2) argument
5191 #define VXGE_HAL_TXMAC_FRMGEN_CFG_PERIOD(val) vBIT(val, 8, 4) argument
5193 #define VXGE_HAL_TXMAC_FRMGEN_CFG_VPATH_VECTOR(val) vBIT(val, 19, 17) argument
5194 #define VXGE_HAL_TXMAC_FRMGEN_CFG_SRC_VPATH(val) vBIT(val, 39, 5) argument
5195 #define VXGE_HAL_TXMAC_FRMGEN_CFG_HOST_STEERING(val) vBIT(val, 44, 2) argument
5196 #define VXGE_HAL_TXMAC_FRMGEN_CFG_IFS_SEL(val) vBIT(val, 47, 3) argument
5198 #define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_PATTERN_SEL(val) vBIT(val, 2, 2) argument
5199 #define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_DA_SEL(val) vBIT(val, 6, 2) argument
5201 #define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_MIN_LEN(val) vBIT(val, 14, 14) argument
5202 #define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_MAX_LEN(val) vBIT(val, 30, 14) argument
5203 #define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_LT_FIELD(val) vBIT(val, 44, 16) argument
5204 #define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_DATA_SEL(val) vBIT(val, 62, 2) argument
5206 #define VXGE_HAL_TXMAC_FRMGEN_DATA_FRMDATA(val) vBIT(val, 0, 64) argument
5208 #define VXGE_HAL_DBG_STAT_TX_ANY_FRMS_PORT0_TX_ANY_FRMS(val) vBIT(val, 0, 8) argument
5209 #define VXGE_HAL_DBG_STAT_TX_ANY_FRMS_PORT1_TX_ANY_FRMS(val) vBIT(val, 8, 8) argument
5210 #define VXGE_HAL_DBG_STAT_TX_ANY_FRMS_PORT2_TX_ANY_FRMS(val) vBIT(val, 16, 8) argument
5214 #define VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_UTILIZATION(val) vBIT(val, 1, 7) argument
5215 #define VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG(val) vBIT(val, 8, 4) argument
5216 #define VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_FRAC_UTIL(val) vBIT(val, 12, 4) argument
5217 #define VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_PKT_WEIGHT(val) vBIT(val, 16, 4) argument
5222 #define VXGE_HAL_TXMAC_CFG0_PORT_PAD_BYTE(val) vBIT(val, 8, 8) argument
5224 #define VXGE_HAL_TXMAC_CFG1_PORT_AVG_IPG(val) vBIT(val, 40, 8) argument
5234 #define VXGE_HAL_LAG_MARKER_CFG_RESP_TIMEOUT(val) vBIT(val, 16, 16) argument
5235 #define VXGE_HAL_LAG_MARKER_CFG_SLOW_PROTO_MRKR_MIN_INTERVAL(val)\ argument
5240 #define VXGE_HAL_LAG_TX_CFG_DISTRIB_ALG_SEL(val) vBIT(val, 6, 2) argument
5242 #define VXGE_HAL_LAG_TX_CFG_COLL_MAX_DELAY(val) vBIT(val, 16, 16) argument
5244 #define VXGE_HAL_LAG_TX_STATUS_TLAG_TIMER_VAL_EMPTIED_LINK(val) vBIT(val, 0, 8) argument
5245 #define VXGE_HAL_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKR(val)\ argument
5247 #define VXGE_HAL_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKRRESP(val)\ argument
5252 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_LANE_CHAR1(val) vBIT(val, 1, 3) argument
5254 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_TXD_CHAR1(val) vBIT(val, 8, 8) argument
5255 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_LANE_CHAR2(val) vBIT(val, 17, 3) argument
5257 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_TXD_CHAR2(val) vBIT(val, 24, 8) argument
5259 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_BEHAV_CHAR2_NUM_CHAR(val)\ argument
5263 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXD_LANE0(val) vBIT(val, 8, 8) argument
5265 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXD_LANE1(val) vBIT(val, 24, 8) argument
5267 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXD_LANE2(val) vBIT(val, 40, 8) argument
5269 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXD_LANE3(val) vBIT(val, 56, 8) argument
5272 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXD_LANE0(val) vBIT(val, 8, 8) argument
5274 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXD_LANE1(val) vBIT(val, 24, 8) argument
5276 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXD_LANE2(val) vBIT(val, 40, 8) argument
5278 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXD_LANE3(val) vBIT(val, 56, 8) argument
5281 #define VXGE_HAL_TXMAC_STATS_TX_XGMII_BEHAV_COLUMN2_NUM_COL(val)\ argument
5286 #define VXGE_HAL_SHAREDIO_STATUS_PCI_NEGOTIATED_ACTIVE_VPLANE(val)\ argument
5288 #define VXGE_HAL_SHAREDIO_STATUS_PCI_NEGOTIATED_VPLANE_COUNT(val)\ argument
5292 #define VXGE_HAL_SHAREDIO_STATUS_PCI_RX_ILLEGAL_TLP_VPLANE_VAL(val)\ argument
5295 #define VXGE_HAL_CRDT_STATUS1_VPLANE_PCI_ABS_PD(val) vBIT(val, 4, 12) argument
5296 #define VXGE_HAL_CRDT_STATUS1_VPLANE_PCI_ABS_NPD(val) vBIT(val, 20, 12) argument
5297 #define VXGE_HAL_CRDT_STATUS1_VPLANE_PCI_ABS_CPLD(val) vBIT(val, 36, 12) argument
5302 #define VXGE_HAL_CRDT_STATUS2_VPLANE_PCI_ABS_PH(val) vBIT(val, 0, 8) argument
5303 #define VXGE_HAL_CRDT_STATUS2_VPLANE_PCI_ABS_NPH(val) vBIT(val, 8, 8) argument
5304 #define VXGE_HAL_CRDT_STATUS2_VPLANE_PCI_ABS_CPLH(val) vBIT(val, 16, 8) argument
5309 #define VXGE_HAL_CRDT_STATUS3_VPLANE_PCI_AVAIL_ABS_BUF_PD(val) vBIT(val, 4, 12) argument
5310 #define VXGE_HAL_CRDT_STATUS3_VPLANE_PCI_AVAIL_ABS_BUF_NPD(val)\ argument
5312 #define VXGE_HAL_CRDT_STATUS3_VPLANE_PCI_AVAIL_ABS_BUF_CPLD(val)\ argument
5315 #define VXGE_HAL_CRDT_STATUS4_VPLANE_PCI_AVAIL_ABS_BUF_PH(val) vBIT(val, 0, 8) argument
5316 #define VXGE_HAL_CRDT_STATUS4_VPLANE_PCI_AVAIL_ABS_BUF_NPH(val) vBIT(val, 8, 8) argument
5317 #define VXGE_HAL_CRDT_STATUS4_VPLANE_PCI_AVAIL_ABS_BUF_CPLH(val)\ argument
5320 #define VXGE_HAL_CRDT_STATUS5_PCI_DEPL_PH(val) vBIT(val, 0, 17) argument
5321 #define VXGE_HAL_CRDT_STATUS5_PCI_DEPL_NPH(val) vBIT(val, 20, 17) argument
5322 #define VXGE_HAL_CRDT_STATUS5_PCI_DEPL_CPLH(val) vBIT(val, 40, 17) argument
5324 #define VXGE_HAL_CRDT_STATUS6_PCI_DEPL_PD(val) vBIT(val, 0, 17) argument
5325 #define VXGE_HAL_CRDT_STATUS6_PCI_DEPL_NPD(val) vBIT(val, 20, 17) argument
5326 #define VXGE_HAL_CRDT_STATUS6_PCI_DEPL_CPLD(val) vBIT(val, 40, 17) argument
5328 #define VXGE_HAL_CRDT_STATUS7_PCI_ABS_PD(val) vBIT(val, 4, 12) argument
5329 #define VXGE_HAL_CRDT_STATUS7_PCI_ABS_NPD(val) vBIT(val, 20, 12) argument
5330 #define VXGE_HAL_CRDT_STATUS7_PCI_ABS_CPLD(val) vBIT(val, 36, 12) argument
5335 #define VXGE_HAL_CRDT_STATUS8_PCI_ABS_PH(val) vBIT(val, 0, 8) argument
5336 #define VXGE_HAL_CRDT_STATUS8_PCI_ABS_NPH(val) vBIT(val, 8, 8) argument
5337 #define VXGE_HAL_CRDT_STATUS8_PCI_ABS_CPLH(val) vBIT(val, 16, 8) argument
5342 #define VXGE_HAL_SRPCIM_TO_MRPCIM_VPLANE_RMSG_RMSG(val) vBIT(val, 0, 64) argument
5346 #define VXGE_HAL_PCIE_LANE_CFG1_RX_0_SEL(val) vBIT(val, 1, 3) argument
5347 #define VXGE_HAL_PCIE_LANE_CFG1_RX_1_SEL(val) vBIT(val, 5, 3) argument
5348 #define VXGE_HAL_PCIE_LANE_CFG1_RX_2_SEL(val) vBIT(val, 9, 3) argument
5349 #define VXGE_HAL_PCIE_LANE_CFG1_RX_3_SEL(val) vBIT(val, 13, 3) argument
5350 #define VXGE_HAL_PCIE_LANE_CFG1_RX_4_SEL(val) vBIT(val, 17, 3) argument
5351 #define VXGE_HAL_PCIE_LANE_CFG1_RX_5_SEL(val) vBIT(val, 21, 3) argument
5352 #define VXGE_HAL_PCIE_LANE_CFG1_RX_6_SEL(val) vBIT(val, 25, 3) argument
5353 #define VXGE_HAL_PCIE_LANE_CFG1_RX_7_SEL(val) vBIT(val, 29, 3) argument
5354 #define VXGE_HAL_PCIE_LANE_CFG1_TX_0_SEL(val) vBIT(val, 33, 3) argument
5355 #define VXGE_HAL_PCIE_LANE_CFG1_TX_1_SEL(val) vBIT(val, 37, 3) argument
5356 #define VXGE_HAL_PCIE_LANE_CFG1_TX_2_SEL(val) vBIT(val, 41, 3) argument
5357 #define VXGE_HAL_PCIE_LANE_CFG1_TX_3_SEL(val) vBIT(val, 45, 3) argument
5358 #define VXGE_HAL_PCIE_LANE_CFG1_TX_4_SEL(val) vBIT(val, 49, 3) argument
5359 #define VXGE_HAL_PCIE_LANE_CFG1_TX_5_SEL(val) vBIT(val, 53, 3) argument
5360 #define VXGE_HAL_PCIE_LANE_CFG1_TX_6_SEL(val) vBIT(val, 57, 3) argument
5361 #define VXGE_HAL_PCIE_LANE_CFG1_TX_7_SEL(val) vBIT(val, 61, 3) argument
5365 #define VXGE_HAL_PCICFG_NO_TO_FUNC_CFG_PCICFG_NO_TO_FUNC_CFG(val)\ argument
5368 #define VXGE_HAL_RESOURCE_TO_VPLANE_CFG_RESOURCE_TO_VPLANE_CFG(val)\ argument
5371 #define VXGE_HAL_PCICFG_NO_TO_VPLANE_CFG_PCICFG_NO_TO_VPLANE_CFG(val)\ argument
5378 #define VXGE_HAL_GENERAL_CFG_RST_CPLTO_VAL(val) vBIT(val, 4, 4) argument
5380 #define VXGE_HAL_GENERAL_CFG_INIT_OSD_COUNT(val) vBIT(val, 12, 8) argument
5381 #define VXGE_HAL_GENERAL_CFG_INIT_SHC(val) vBIT(val, 20, 8) argument
5382 #define VXGE_HAL_GENERAL_CFG_INITOSD_VERSION(val) vBIT(val, 29, 3) argument
5384 #define VXGE_HAL_GENERAL_CFG_FC_UPDT_FREQ_VAL(val) vBIT(val, 36, 4) argument
5404 #define VXGE_HAL_BIST_CFG_JTAG_BIST_COMPLETION_CODE(val) vBIT(val, 8, 4) argument
5409 #define VXGE_HAL_SHOW_SRIOV_CAP_SHOW_SRIOV_CAP(val) vBIT(val, 0, 9) argument
5411 #define VXGE_HAL_LINK_RST_WAIT_CNT_LINK_RST_WAIT_CNT(val) vBIT(val, 0, 16) argument
5413 #define VXGE_HAL_PCIE_BASED_CRDT_CFG1_INIT_PD(val) vBIT(val, 4, 12) argument
5414 #define VXGE_HAL_PCIE_BASED_CRDT_CFG1_INIT_NPD(val) vBIT(val, 20, 12) argument
5415 #define VXGE_HAL_PCIE_BASED_CRDT_CFG1_INIT_CPLD(val) vBIT(val, 36, 12) argument
5417 #define VXGE_HAL_PCIE_BASED_CRDT_CFG2_INIT_PH(val) vBIT(val, 0, 8) argument
5418 #define VXGE_HAL_PCIE_BASED_CRDT_CFG2_INIT_NPH(val) vBIT(val, 8, 8) argument
5419 #define VXGE_HAL_PCIE_BASED_CRDT_CFG2_INIT_CPLH(val) vBIT(val, 16, 8) argument
5421 #define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG1_VPLANE_ABS_PD(val)\ argument
5423 #define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG1_VPLANE_ABS_NPD(val)\ argument
5425 #define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG1_VPLANE_ABS_CPLD(val)\ argument
5431 #define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG2_VPLANE_ABS_PH(val)\ argument
5433 #define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG2_VPLANE_ABS_NPH(val)\ argument
5435 #define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG2_VPLANE_ABS_CPLH(val)\ argument
5441 #define VXGE_HAL_ARBITER_CFG_CPL_PRIORITY(val) vBIT(val, 2, 2) argument
5442 #define VXGE_HAL_ARBITER_CFG_MRD_PRIORITY(val) vBIT(val, 6, 2) argument
5443 #define VXGE_HAL_ARBITER_CFG_MWR_PRIORITY(val) vBIT(val, 10, 2) argument
5445 #define VXGE_HAL_ARBITER_CFG_CALSTATE0_PRIORITY(val) vBIT(val, 18, 2) argument
5446 #define VXGE_HAL_ARBITER_CFG_CALSTATE1_PRIORITY(val) vBIT(val, 22, 2) argument
5447 #define VXGE_HAL_ARBITER_CFG_CALSTATE2_PRIORITY(val) vBIT(val, 26, 2) argument
5448 #define VXGE_HAL_ARBITER_CFG_CALSTATE3_PRIORITY(val) vBIT(val, 30, 2) argument
5449 #define VXGE_HAL_ARBITER_CFG_CALSTATE4_PRIORITY(val) vBIT(val, 34, 2) argument
5450 #define VXGE_HAL_ARBITER_CFG_CALSTATE5_PRIORITY(val) vBIT(val, 38, 2) argument
5452 #define VXGE_HAL_SERDES_CFG1_TX_CLOCK_ALIGN(val) vBIT(val, 0, 8) argument
5453 #define VXGE_HAL_SERDES_CFG1_TX_CALC(val) vBIT(val, 8, 8) argument
5454 #define VXGE_HAL_SERDES_CFG1_TX_LVL(val) vBIT(val, 19, 5) argument
5455 #define VXGE_HAL_SERDES_CFG1_LOS_LVL(val) vBIT(val, 27, 5) argument
5457 #define VXGE_HAL_SERDES_CFG2_TX_0_BOOST(val) vBIT(val, 0, 4) argument
5458 #define VXGE_HAL_SERDES_CFG2_TX_1_BOOST(val) vBIT(val, 4, 4) argument
5459 #define VXGE_HAL_SERDES_CFG2_TX_2_BOOST(val) vBIT(val, 8, 4) argument
5460 #define VXGE_HAL_SERDES_CFG2_TX_3_BOOST(val) vBIT(val, 12, 4) argument
5461 #define VXGE_HAL_SERDES_CFG2_TX_4_BOOST(val) vBIT(val, 16, 4) argument
5462 #define VXGE_HAL_SERDES_CFG2_TX_5_BOOST(val) vBIT(val, 20, 4) argument
5463 #define VXGE_HAL_SERDES_CFG2_TX_6_BOOST(val) vBIT(val, 24, 4) argument
5464 #define VXGE_HAL_SERDES_CFG2_TX_7_BOOST(val) vBIT(val, 28, 4) argument
5465 #define VXGE_HAL_SERDES_CFG2_TX_0_ATTEN(val) vBIT(val, 33, 3) argument
5466 #define VXGE_HAL_SERDES_CFG2_TX_1_ATTEN(val) vBIT(val, 37, 3) argument
5467 #define VXGE_HAL_SERDES_CFG2_TX_2_ATTEN(val) vBIT(val, 41, 3) argument
5468 #define VXGE_HAL_SERDES_CFG2_TX_3_ATTEN(val) vBIT(val, 45, 3) argument
5469 #define VXGE_HAL_SERDES_CFG2_TX_4_ATTEN(val) vBIT(val, 49, 3) argument
5470 #define VXGE_HAL_SERDES_CFG2_TX_5_ATTEN(val) vBIT(val, 53, 3) argument
5471 #define VXGE_HAL_SERDES_CFG2_TX_6_ATTEN(val) vBIT(val, 57, 3) argument
5472 #define VXGE_HAL_SERDES_CFG2_TX_7_ATTEN(val) vBIT(val, 61, 3) argument
5474 #define VXGE_HAL_SERDES_CFG3_TX_0_EDGERATE(val) vBIT(val, 2, 2) argument
5475 #define VXGE_HAL_SERDES_CFG3_TX_1_EDGERATE(val) vBIT(val, 6, 2) argument
5476 #define VXGE_HAL_SERDES_CFG3_TX_2_EDGERATE(val) vBIT(val, 10, 2) argument
5477 #define VXGE_HAL_SERDES_CFG3_TX_3_EDGERATE(val) vBIT(val, 14, 2) argument
5478 #define VXGE_HAL_SERDES_CFG3_TX_4_EDGERATE(val) vBIT(val, 18, 2) argument
5479 #define VXGE_HAL_SERDES_CFG3_TX_5_EDGERATE(val) vBIT(val, 22, 2) argument
5480 #define VXGE_HAL_SERDES_CFG3_TX_6_EDGERATE(val) vBIT(val, 26, 2) argument
5481 #define VXGE_HAL_SERDES_CFG3_TX_7_EDGERATE(val) vBIT(val, 30, 2) argument
5482 #define VXGE_HAL_SERDES_CFG3_RX_0_EQ_VAL(val) vBIT(val, 33, 3) argument
5483 #define VXGE_HAL_SERDES_CFG3_RX_1_EQ_VAL(val) vBIT(val, 37, 3) argument
5484 #define VXGE_HAL_SERDES_CFG3_RX_2_EQ_VAL(val) vBIT(val, 41, 3) argument
5485 #define VXGE_HAL_SERDES_CFG3_RX_3_EQ_VAL(val) vBIT(val, 45, 3) argument
5486 #define VXGE_HAL_SERDES_CFG3_RX_4_EQ_VAL(val) vBIT(val, 49, 3) argument
5487 #define VXGE_HAL_SERDES_CFG3_RX_5_EQ_VAL(val) vBIT(val, 53, 3) argument
5488 #define VXGE_HAL_SERDES_CFG3_RX_6_EQ_VAL(val) vBIT(val, 57, 3) argument
5489 #define VXGE_HAL_SERDES_CFG3_RX_7_EQ_VAL(val) vBIT(val, 61, 3) argument
5491 #define VXGE_HAL_VHLABEL_TO_VPLANE_CFG_VHLABEL_TO_VPLANE_CFG(val)\ argument
5494 #define VXGE_HAL_MRPCIM_TO_SRPCIM_VPLANE_WMSG_WMSG(val) vBIT(val, 0, 64) argument
5498 #define VXGE_HAL_DEBUG_STATS0_RSTDROP_MSG(val) vBIT(val, 0, 32) argument
5499 #define VXGE_HAL_DEBUG_STATS0_RSTDROP_CPL(val) vBIT(val, 32, 32) argument
5501 #define VXGE_HAL_DEBUG_STATS1_RSTDROP_CLIENT0(val) vBIT(val, 0, 32) argument
5502 #define VXGE_HAL_DEBUG_STATS1_RSTDROP_CLIENT1(val) vBIT(val, 32, 32) argument
5504 #define VXGE_HAL_DEBUG_STATS2_RSTDROP_CLIENT2(val) vBIT(val, 0, 32) argument
5506 #define VXGE_HAL_DEBUG_STATS3_VPLANE_DEPL_PH(val) vBIT(val, 0, 16) argument
5507 #define VXGE_HAL_DEBUG_STATS3_VPLANE_DEPL_NPH(val) vBIT(val, 16, 16) argument
5508 #define VXGE_HAL_DEBUG_STATS3_VPLANE_DEPL_CPLH(val) vBIT(val, 32, 16) argument
5510 #define VXGE_HAL_DEBUG_STATS4_VPLANE_DEPL_PD(val) vBIT(val, 0, 16) argument
5511 #define VXGE_HAL_DEBUG_STATS4_VPLANE_DEPL_NPD(val) vBIT(val, 16, 16) argument
5512 #define VXGE_HAL_DEBUG_STATS4_VPLANE_DEPL_CPLD(val) vBIT(val, 32, 16) argument
5516 #define VXGE_HAL_RC_RXDMEM_END_OFST_RC_RXDMEM_END_OFST(val) vBIT(val, 49, 8) argument
5755 #define VXGE_HAL_SRPCIM_TO_MRPCIM_ALARM_REG_ALARM(val) vBIT(val, 0, 17) argument
5759 #define VXGE_HAL_VPATH_TO_MRPCIM_ALARM_REG_ALARM(val) vBIT(val, 0, 17) argument
5782 #define VXGE_HAL_SPLIT_TABLE_STATUS1_SCPL_TAG_ENTRY1(val) vBIT(val, 0, 64) argument
5784 #define VXGE_HAL_SPLIT_TABLE_STATUS2_SCPL_TAG_ENTRY2(val) vBIT(val, 0, 64) argument
5786 #define VXGE_HAL_SPLIT_TABLE_STATUS3_SCPL_TAG_ENTRY3(val) vBIT(val, 0, 64) argument
5788 #define VXGE_HAL_MRPCIM_GENERAL_STATUS1_INI_RCPL_ERRSYND(val) vBIT(val, 0, 8) argument
5790 #define VXGE_HAL_MRPCIM_GENERAL_STATUS1_SCPL_NUM_OUTSTANDING_RDS(val)\ argument
5792 #define VXGE_HAL_MRPCIM_GENERAL_STATUS1_TGT_VENDOR_MSG_PAYLOAD(val)\ argument
5795 #define VXGE_HAL_MRPCIM_GENERAL_STATUS2_CFGM_TIMEOUT_ADDR(val) vBIT(val, 6, 10) argument
5796 #define VXGE_HAL_MRPCIM_GENERAL_STATUS2_RIC_TIMEOUT_ADDR(val) vBIT(val, 22, 10) argument
5797 #define VXGE_HAL_MRPCIM_GENERAL_STATUS2_PIFM_ILLEGAL_CLIENT(val)\ argument
5800 #define VXGE_HAL_MRPCIM_GENERAL_STATUS2_PIFM_ILLEGAL_ADDR(val) vBIT(val, 44, 20) argument
5802 #define VXGE_HAL_MRPCIM_GENERAL_STATUS3_PIFM_TIMEOUT_ADDR(val) vBIT(val, 0, 20) argument
5803 #define VXGE_HAL_MRPCIM_GENERAL_STATUS3_TGT_NOT_MEM_TLP_FMT(val)\ argument
5805 #define VXGE_HAL_MRPCIM_GENERAL_STATUS3_TGT_NOT_MEM_TLP_TYPE(val)\ argument
5807 #define VXGE_HAL_MRPCIM_GENERAL_STATUS3_TGT_UNKNOWN_MEM_TLP_FMT(val)\ argument
5809 #define VXGE_HAL_MRPCIM_GENERAL_STATUS3_TGT_UNKNOWN_MEM_TLP_TYPE(val)\ argument
5863 #define VXGE_HAL_KDFCCTL_DBG_STATUS_KDFCCTL_ADDR_ERR(val) vBIT(val, 2, 22) argument
5864 #define VXGE_HAL_KDFCCTL_DBG_STATUS_KDFCCTL_FIFO_NO_ERR(val) vBIT(val, 26, 6) argument
5866 #define VXGE_HAL_MSIX_ADDR_MSIX_ADDR(val) vBIT(val, 0, 64) argument
5868 #define VXGE_HAL_MSIX_TABLE_DATA(val) vBIT(val, 0, 32) argument
5871 #define VXGE_HAL_MSIX_CTL_VECTOR_NO(val) vBIT(val, 1, 7) argument
5894 #define VXGE_HAL_DMAIF_DMADBL_PENDING_DBLGEN_IN_PROG(val) vBIT(val, 13, 51) argument
5896 #define VXGE_HAL_WRCRDTARB_STATUS0_VPLANE_WRCRDTARB_ABS_AVAIL_P_H(val)\ argument
5899 #define VXGE_HAL_WRCRDTARB_STATUS1_VPLANE_WRCRDTARB_ABS_AVAIL_P_D(val)\ argument
5915 #define VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_MAP_TO_VPATH(val)\ argument
5927 #define VXGE_HAL_MRPCIM_GENERAL_CFG3_MR_MAX_MVFS(val) vBIT(val, 20, 16) argument
5928 #define VXGE_HAL_MRPCIM_GENERAL_CFG3_MR_MVF_TBL_SIZE(val) vBIT(val, 36, 16) argument
5930 #define VXGE_HAL_MRPCIM_GENERAL_CFG3_REG_MODIFIED_CFG(val) vBIT(val, 56, 2) argument
5934 #define VXGE_HAL_MRPCIM_STATS_START_HOST_ADDR_MRPCIM_STATS_START_HOST_ADDR(val)\ argument
5937 #define VXGE_HAL_ASIC_MODE_PIC(val) vBIT(val, 2, 2) argument
5941 #define VXGE_HAL_INI_TIMEOUT_VAL_MWR(val) vBIT(val, 0, 32) argument
5942 #define VXGE_HAL_INI_TIMEOUT_VAL_MRD(val) vBIT(val, 32, 32) argument
5950 #define VXGE_HAL_READ_ARBITER_WRDMA_PRIORITY(val) vBIT(val, 2, 2) argument
5951 #define VXGE_HAL_READ_ARBITER_RTDMA_PRIORITY(val) vBIT(val, 6, 2) argument
5952 #define VXGE_HAL_READ_ARBITER_DBLGEN_PRIORITY(val) vBIT(val, 10, 2) argument
5953 #define VXGE_HAL_READ_ARBITER_CALSTATE0_PRIORITY(val) vBIT(val, 14, 2) argument
5954 #define VXGE_HAL_READ_ARBITER_CALSTATE1_PRIORITY(val) vBIT(val, 18, 2) argument
5955 #define VXGE_HAL_READ_ARBITER_CALSTATE2_PRIORITY(val) vBIT(val, 22, 2) argument
5956 #define VXGE_HAL_READ_ARBITER_CALSTATE3_PRIORITY(val) vBIT(val, 26, 2) argument
5957 #define VXGE_HAL_READ_ARBITER_CALSTATE4_PRIORITY(val) vBIT(val, 30, 2) argument
5958 #define VXGE_HAL_READ_ARBITER_CALSTATE5_PRIORITY(val) vBIT(val, 34, 2) argument
5961 #define VXGE_HAL_WRITE_ARBITER_WRDMA_PRIORITY(val) vBIT(val, 2, 2) argument
5962 #define VXGE_HAL_WRITE_ARBITER_RTDMA_PRIORITY(val) vBIT(val, 6, 2) argument
5963 #define VXGE_HAL_WRITE_ARBITER_STATS_PRIORITY(val) vBIT(val, 10, 2) argument
5964 #define VXGE_HAL_WRITE_ARBITER_MSG_PRIORITY(val) vBIT(val, 14, 2) argument
5965 #define VXGE_HAL_WRITE_ARBITER_CALSTATE0_PRIORITY(val) vBIT(val, 18, 2) argument
5966 #define VXGE_HAL_WRITE_ARBITER_CALSTATE1_PRIORITY(val) vBIT(val, 22, 2) argument
5967 #define VXGE_HAL_WRITE_ARBITER_CALSTATE2_PRIORITY(val) vBIT(val, 26, 2) argument
5968 #define VXGE_HAL_WRITE_ARBITER_CALSTATE3_PRIORITY(val) vBIT(val, 30, 2) argument
5969 #define VXGE_HAL_WRITE_ARBITER_CALSTATE4_PRIORITY(val) vBIT(val, 34, 2) argument
5970 #define VXGE_HAL_WRITE_ARBITER_CALSTATE5_PRIORITY(val) vBIT(val, 38, 2) argument
5971 #define VXGE_HAL_WRITE_ARBITER_CALSTATE6_PRIORITY(val) vBIT(val, 42, 2) argument
5972 #define VXGE_HAL_WRITE_ARBITER_CALSTATE7_PRIORITY(val) vBIT(val, 46, 2) argument
5973 #define VXGE_HAL_WRITE_ARBITER_CALSTATE8_PRIORITY(val) vBIT(val, 50, 2) argument
5974 #define VXGE_HAL_WRITE_ARBITER_CALSTATE9_PRIORITY(val) vBIT(val, 52, 2) argument
5981 #define VXGE_HAL_PROGRAM_CFG0_I2C_SLAVE_ADDR(val) vBIT(val, 1, 7) argument
5985 #define VXGE_HAL_PROGRAM_CFG1_CFGM_TIMEOUT_LOAD_VAL(val) vBIT(val, 0, 32) argument
5986 #define VXGE_HAL_PROGRAM_CFG1_PIFM_TIMEOUT_LOAD_VAL(val) vBIT(val, 32, 32) argument
5988 #define VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_0_NUM(val) vBIT(val, 3, 5) argument
5989 #define VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_1_NUM(val) vBIT(val, 11, 5) argument
5990 #define VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_2_NUM(val) vBIT(val, 19, 5) argument
5991 #define VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_3_NUM(val) vBIT(val, 27, 5) argument
5992 #define VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_4_NUM(val) vBIT(val, 35, 5) argument
5993 #define VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_5_NUM(val) vBIT(val, 43, 5) argument
5994 #define VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_6_NUM(val) vBIT(val, 51, 5) argument
5995 #define VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_7_NUM(val) vBIT(val, 59, 5) argument
5997 #define VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_8_NUM(val) vBIT(val, 3, 5) argument
5998 #define VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_9_NUM(val) vBIT(val, 11, 5) argument
5999 #define VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_10_NUM(val) vBIT(val, 19, 5) argument
6000 #define VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_11_NUM(val) vBIT(val, 27, 5) argument
6001 #define VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_12_NUM(val) vBIT(val, 35, 5) argument
6002 #define VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_13_NUM(val) vBIT(val, 43, 5) argument
6003 #define VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_14_NUM(val) vBIT(val, 51, 5) argument
6004 #define VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_15_NUM(val) vBIT(val, 59, 5) argument
6006 #define VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_16_NUM(val) vBIT(val, 3, 5) argument
6007 #define VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_17_NUM(val) vBIT(val, 11, 5) argument
6008 #define VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_18_NUM(val) vBIT(val, 19, 5) argument
6009 #define VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_19_NUM(val) vBIT(val, 27, 5) argument
6010 #define VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_20_NUM(val) vBIT(val, 35, 5) argument
6011 #define VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_21_NUM(val) vBIT(val, 43, 5) argument
6012 #define VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_22_NUM(val) vBIT(val, 51, 5) argument
6013 #define VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_23_NUM(val) vBIT(val, 59, 5) argument
6015 #define VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_24_NUM(val) vBIT(val, 3, 5) argument
6016 #define VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_25_NUM(val) vBIT(val, 11, 5) argument
6017 #define VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_26_NUM(val) vBIT(val, 19, 5) argument
6018 #define VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_27_NUM(val) vBIT(val, 27, 5) argument
6019 #define VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_28_NUM(val) vBIT(val, 35, 5) argument
6020 #define VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_29_NUM(val) vBIT(val, 43, 5) argument
6021 #define VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_30_NUM(val) vBIT(val, 51, 5) argument
6022 #define VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_31_NUM(val) vBIT(val, 59, 5) argument
6024 #define VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_32_NUM(val) vBIT(val, 3, 5) argument
6025 #define VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_33_NUM(val) vBIT(val, 11, 5) argument
6026 #define VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_34_NUM(val) vBIT(val, 19, 5) argument
6027 #define VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_35_NUM(val) vBIT(val, 27, 5) argument
6028 #define VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_36_NUM(val) vBIT(val, 35, 5) argument
6029 #define VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_37_NUM(val) vBIT(val, 43, 5) argument
6030 #define VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_38_NUM(val) vBIT(val, 51, 5) argument
6031 #define VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_39_NUM(val) vBIT(val, 59, 5) argument
6033 #define VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_40_NUM(val) vBIT(val, 3, 5) argument
6034 #define VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_41_NUM(val) vBIT(val, 11, 5) argument
6035 #define VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_42_NUM(val) vBIT(val, 19, 5) argument
6036 #define VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_43_NUM(val) vBIT(val, 27, 5) argument
6037 #define VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_44_NUM(val) vBIT(val, 35, 5) argument
6038 #define VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_45_NUM(val) vBIT(val, 43, 5) argument
6039 #define VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_46_NUM(val) vBIT(val, 51, 5) argument
6040 #define VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_47_NUM(val) vBIT(val, 59, 5) argument
6042 #define VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_48_NUM(val) vBIT(val, 3, 5) argument
6043 #define VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_49_NUM(val) vBIT(val, 11, 5) argument
6044 #define VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_50_NUM(val) vBIT(val, 19, 5) argument
6045 #define VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_51_NUM(val) vBIT(val, 27, 5) argument
6046 #define VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_52_NUM(val) vBIT(val, 35, 5) argument
6047 #define VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_53_NUM(val) vBIT(val, 43, 5) argument
6048 #define VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_54_NUM(val) vBIT(val, 51, 5) argument
6049 #define VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_55_NUM(val) vBIT(val, 59, 5) argument
6051 #define VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_56_NUM(val) vBIT(val, 3, 5) argument
6052 #define VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_57_NUM(val) vBIT(val, 11, 5) argument
6053 #define VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_58_NUM(val) vBIT(val, 19, 5) argument
6054 #define VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_59_NUM(val) vBIT(val, 27, 5) argument
6055 #define VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_60_NUM(val) vBIT(val, 35, 5) argument
6056 #define VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_61_NUM(val) vBIT(val, 43, 5) argument
6057 #define VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_62_NUM(val) vBIT(val, 51, 5) argument
6058 #define VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_63_NUM(val) vBIT(val, 59, 5) argument
6060 #define VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_64_NUM(val) vBIT(val, 3, 5) argument
6061 #define VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_65_NUM(val) vBIT(val, 11, 5) argument
6062 #define VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_66_NUM(val) vBIT(val, 19, 5) argument
6063 #define VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_67_NUM(val) vBIT(val, 27, 5) argument
6064 #define VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_68_NUM(val) vBIT(val, 35, 5) argument
6065 #define VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_69_NUM(val) vBIT(val, 43, 5) argument
6066 #define VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_70_NUM(val) vBIT(val, 51, 5) argument
6067 #define VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_71_NUM(val) vBIT(val, 59, 5) argument
6069 #define VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_72_NUM(val) vBIT(val, 3, 5) argument
6070 #define VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_73_NUM(val) vBIT(val, 11, 5) argument
6071 #define VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_74_NUM(val) vBIT(val, 19, 5) argument
6072 #define VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_75_NUM(val) vBIT(val, 27, 5) argument
6073 #define VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_76_NUM(val) vBIT(val, 35, 5) argument
6074 #define VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_77_NUM(val) vBIT(val, 43, 5) argument
6075 #define VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_78_NUM(val) vBIT(val, 51, 5) argument
6076 #define VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_79_NUM(val) vBIT(val, 59, 5) argument
6078 #define VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_80_NUM(val) vBIT(val, 3, 5) argument
6079 #define VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_81_NUM(val) vBIT(val, 11, 5) argument
6080 #define VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_82_NUM(val) vBIT(val, 19, 5) argument
6081 #define VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_83_NUM(val) vBIT(val, 27, 5) argument
6082 #define VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_84_NUM(val) vBIT(val, 35, 5) argument
6083 #define VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_85_NUM(val) vBIT(val, 43, 5) argument
6084 #define VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_86_NUM(val) vBIT(val, 51, 5) argument
6085 #define VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_87_NUM(val) vBIT(val, 59, 5) argument
6087 #define VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_88_NUM(val) vBIT(val, 3, 5) argument
6088 #define VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_89_NUM(val) vBIT(val, 11, 5) argument
6089 #define VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_90_NUM(val) vBIT(val, 19, 5) argument
6090 #define VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_91_NUM(val) vBIT(val, 27, 5) argument
6091 #define VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_92_NUM(val) vBIT(val, 35, 5) argument
6092 #define VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_93_NUM(val) vBIT(val, 43, 5) argument
6093 #define VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_94_NUM(val) vBIT(val, 51, 5) argument
6094 #define VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_95_NUM(val) vBIT(val, 59, 5) argument
6096 #define VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_96_NUM(val) vBIT(val, 3, 5) argument
6097 #define VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_97_NUM(val) vBIT(val, 11, 5) argument
6098 #define VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_98_NUM(val) vBIT(val, 19, 5) argument
6099 #define VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_99_NUM(val) vBIT(val, 27, 5) argument
6100 #define VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_100_NUM(val) vBIT(val, 35, 5) argument
6101 #define VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_101_NUM(val) vBIT(val, 43, 5) argument
6102 #define VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_102_NUM(val) vBIT(val, 51, 5) argument
6103 #define VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_103_NUM(val) vBIT(val, 59, 5) argument
6105 #define VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_104_NUM(val) vBIT(val, 3, 5) argument
6106 #define VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_105_NUM(val) vBIT(val, 11, 5) argument
6107 #define VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_106_NUM(val) vBIT(val, 19, 5) argument
6108 #define VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_107_NUM(val) vBIT(val, 27, 5) argument
6109 #define VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_108_NUM(val) vBIT(val, 35, 5) argument
6110 #define VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_109_NUM(val) vBIT(val, 43, 5) argument
6111 #define VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_110_NUM(val) vBIT(val, 51, 5) argument
6112 #define VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_111_NUM(val) vBIT(val, 59, 5) argument
6114 #define VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_112_NUM(val) vBIT(val, 3, 5) argument
6115 #define VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_113_NUM(val) vBIT(val, 11, 5) argument
6116 #define VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_114_NUM(val) vBIT(val, 19, 5) argument
6117 #define VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_115_NUM(val) vBIT(val, 27, 5) argument
6118 #define VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_116_NUM(val) vBIT(val, 35, 5) argument
6119 #define VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_117_NUM(val) vBIT(val, 43, 5) argument
6120 #define VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_118_NUM(val) vBIT(val, 51, 5) argument
6121 #define VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_119_NUM(val) vBIT(val, 59, 5) argument
6123 #define VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_120_NUM(val) vBIT(val, 3, 5) argument
6124 #define VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_121_NUM(val) vBIT(val, 11, 5) argument
6125 #define VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_122_NUM(val) vBIT(val, 19, 5) argument
6126 #define VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_123_NUM(val) vBIT(val, 27, 5) argument
6127 #define VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_124_NUM(val) vBIT(val, 35, 5) argument
6128 #define VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_125_NUM(val) vBIT(val, 43, 5) argument
6129 #define VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_126_NUM(val) vBIT(val, 51, 5) argument
6130 #define VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_127_NUM(val) vBIT(val, 59, 5) argument
6132 #define VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_128_NUM(val) vBIT(val, 3, 5) argument
6133 #define VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_129_NUM(val) vBIT(val, 11, 5) argument
6134 #define VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_130_NUM(val) vBIT(val, 19, 5) argument
6135 #define VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_131_NUM(val) vBIT(val, 27, 5) argument
6136 #define VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_132_NUM(val) vBIT(val, 35, 5) argument
6137 #define VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_133_NUM(val) vBIT(val, 43, 5) argument
6138 #define VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_134_NUM(val) vBIT(val, 51, 5) argument
6139 #define VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_135_NUM(val) vBIT(val, 59, 5) argument
6141 #define VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_136_NUM(val) vBIT(val, 3, 5) argument
6142 #define VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_137_NUM(val) vBIT(val, 11, 5) argument
6143 #define VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_138_NUM(val) vBIT(val, 19, 5) argument
6144 #define VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_139_NUM(val) vBIT(val, 27, 5) argument
6145 #define VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_140_NUM(val) vBIT(val, 35, 5) argument
6146 #define VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_141_NUM(val) vBIT(val, 43, 5) argument
6147 #define VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_142_NUM(val) vBIT(val, 51, 5) argument
6148 #define VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_143_NUM(val) vBIT(val, 59, 5) argument
6150 #define VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_144_NUM(val) vBIT(val, 3, 5) argument
6151 #define VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_145_NUM(val) vBIT(val, 11, 5) argument
6152 #define VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_146_NUM(val) vBIT(val, 19, 5) argument
6153 #define VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_147_NUM(val) vBIT(val, 27, 5) argument
6154 #define VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_148_NUM(val) vBIT(val, 35, 5) argument
6155 #define VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_149_NUM(val) vBIT(val, 43, 5) argument
6156 #define VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_150_NUM(val) vBIT(val, 51, 5) argument
6157 #define VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_151_NUM(val) vBIT(val, 59, 5) argument
6159 #define VXGE_HAL_DBLGEN_WRR_CFG20_CTRL_SS_152_NUM(val) vBIT(val, 3, 5) argument
6161 #define VXGE_HAL_DEBUG_CFG1_TAG_TO_OBSERVE(val) vBIT(val, 3, 5) argument
6174 #define VXGE_HAL_TEST_CFG2_PERR_TIMEOUT_VAL(val) vBIT(val, 0, 32) argument
6178 #define VXGE_HAL_WRCRDTARB_CFG0_WAIT_CNT(val) vBIT(val, 48, 4) argument
6185 #define VXGE_HAL_WRCRDTARB_CFG2_STATS_PRTY_TIMEOUT_VAL(val) vBIT(val, 0, 32) argument
6186 #define VXGE_HAL_WRCRDTARB_CFG2_STATS_DROP_TIMEOUT_VAL(val) vBIT(val, 32, 32) argument
6188 #define VXGE_HAL_TEST_WRCRDTARB_CFG1_BLOCK_VPLANE_TIMEOUT1_VAL(val)\ argument
6190 #define VXGE_HAL_TEST_WRCRDTARB_CFG1_BLOCK_VPLANE_TIMEOUT2_VAL(val)\ argument
6193 #define VXGE_HAL_TEST_WRCRDTARB_CFG2_BLOCK_VPLANE_TIMEOUT3_VAL(val)\ argument
6195 #define VXGE_HAL_TEST_WRCRDTARB_CFG2_BLOCK_VPLANE_TIMEOUT4_VAL(val)\ argument
6198 #define VXGE_HAL_TEST_WRCRDTARB_CFG3_TIMEOUT1_MAP(val) vBIT(val, 3, 5) argument
6199 #define VXGE_HAL_TEST_WRCRDTARB_CFG3_TIMEOUT2_MAP(val) vBIT(val, 11, 5) argument
6200 #define VXGE_HAL_TEST_WRCRDTARB_CFG3_TIMEOUT3_MAP(val) vBIT(val, 19, 5) argument
6201 #define VXGE_HAL_TEST_WRCRDTARB_CFG3_TIMEOUT4_MAP(val) vBIT(val, 27, 5) argument
6208 #define VXGE_HAL_RDCRDTARB_CFG0_RDA_MAX_OUTSTANDING_RDS(val) vBIT(val, 18, 6) argument
6209 #define VXGE_HAL_RDCRDTARB_CFG0_PDA_MAX_OUTSTANDING_RDS(val) vBIT(val, 26, 6) argument
6210 #define VXGE_HAL_RDCRDTARB_CFG0_DBLGEN_MAX_OUTSTANDING_RDS(val) vBIT(val, 34, 6) argument
6211 #define VXGE_HAL_RDCRDTARB_CFG0_WAIT_CNT(val) vBIT(val, 48, 4) argument
6212 #define VXGE_HAL_RDCRDTARB_CFG0_MAX_OUTSTANDING_RDS(val) vBIT(val, 54, 6) argument
6217 #define VXGE_HAL_RDCRDTARB_CFG2_SOFTNAK_TIMER_VAL_DIV4(val) vBIT(val, 0, 32) argument
6219 #define VXGE_HAL_TEST_RDCRDTARB_CFG1_BLOCK_VPLANE_TIMEOUT1_VAL(val)\ argument
6221 #define VXGE_HAL_TEST_RDCRDTARB_CFG1_BLOCK_VPLANE_TIMEOUT2_VAL(val)\ argument
6224 #define VXGE_HAL_TEST_RDCRDTARB_CFG2_BLOCK_VPLANE_TIMEOUT3_VAL(val)\ argument
6226 #define VXGE_HAL_TEST_RDCRDTARB_CFG2_BLOCK_VPLANE_TIMEOUT4_VAL(val)\ argument
6229 #define VXGE_HAL_TEST_RDCRDTARB_CFG3_TIMEOUT1_MAP(val) vBIT(val, 3, 5) argument
6230 #define VXGE_HAL_TEST_RDCRDTARB_CFG3_TIMEOUT2_MAP(val) vBIT(val, 11, 5) argument
6231 #define VXGE_HAL_TEST_RDCRDTARB_CFG3_TIMEOUT3_MAP(val) vBIT(val, 19, 5) argument
6232 #define VXGE_HAL_TEST_RDCRDTARB_CFG3_TIMEOUT4_MAP(val) vBIT(val, 27, 5) argument
6239 #define VXGE_HAL_PIC_DEBUG_CONTROL_DBG_ALL_CLKA_SEL(val) vBIT(val, 0, 4) argument
6240 #define VXGE_HAL_PIC_DEBUG_CONTROL_DBG_ALL_CLKB_SEL(val) vBIT(val, 4, 4) argument
6241 #define VXGE_HAL_PIC_DEBUG_CONTROL_DBG_ALL_DA_SEL(val) vBIT(val, 10, 6) argument
6242 #define VXGE_HAL_PIC_DEBUG_CONTROL_DBG_ALL_DB_SEL(val) vBIT(val, 18, 6) argument
6243 #define VXGE_HAL_PIC_DEBUG_CONTROL_DBGA_SEL(val) vBIT(val, 28, 4) argument
6244 #define VXGE_HAL_PIC_DEBUG_CONTROL_DBGB_SEL(val) vBIT(val, 32, 4) argument
6248 #define VXGE_HAL_SPI_CONTROL_3_REG_SECTOR_0_WR_EN(val) vBIT(val, 0, 32) argument
6259 #define VXGE_HAL_VECTOR_SRPCIM_ALARM_MAP_VECTOR_SRPCIM_ALARM_MAP(val)\ argument
6264 #define VXGE_HAL_VPLANE_RDCRDTARB_CFG0_TAGS_THRESHOLD_XOFF(val)\ argument
6266 #define VXGE_HAL_VPLANE_RDCRDTARB_CFG0_MAX_OUTSTANDING_RDS(val)\ argument
6271 #define VXGE_HAL_MRPCIM_SPI_CONTROL_KEY(val) vBIT(val, 0, 4) argument
6276 #define VXGE_HAL_MRPCIM_SPI_CONTROL_BYTE_CNT(val) vBIT(val, 29, 3) argument
6277 #define VXGE_HAL_MRPCIM_SPI_CONTROL_CMD(val) vBIT(val, 32, 8) argument
6278 #define VXGE_HAL_MRPCIM_SPI_CONTROL_ADD(val) vBIT(val, 40, 24) argument
6280 #define VXGE_HAL_MRPCIM_SPI_DATA_SPI_RWDATA(val) vBIT(val, 0, 64) argument
6289 #define VXGE_HAL_CHIP_FULL_RESET_CHIP_FULL_RESET(val) vBIT(val, 0, 8) argument
6291 #define VXGE_HAL_BF_SW_RESET_BF_SW_RESET(val) vBIT(val, 0, 8) argument
6299 #define VXGE_HAL_SW_RESET_CFG1_WAIT_TIME_FOR_FLUSH_PCI(val) vBIT(val, 7, 25) argument
6300 #define VXGE_HAL_SW_RESET_CFG1_SOPR_ASSERT_TIME(val) vBIT(val, 32, 4) argument
6301 #define VXGE_HAL_SW_RESET_CFG1_WAIT_TIME_AFTER_RESET(val) vBIT(val, 38, 25) argument
6304 #define VXGE_HAL_RIC_TIMEOUT_VAL(val) vBIT(val, 32, 32) argument
6306 #define VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_CFG1_ADDRESS(val) vBIT(val, 4, 10) argument
6307 #define VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_CFG1_VPLANE(val) vBIT(val, 19, 5) argument
6308 #define VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_CFG1_FUNC(val) vBIT(val, 27, 5) argument
6314 #define VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_STATUS_DATA(val) vBIT(val, 32, 32) argument
6318 #define VXGE_HAL_RDCRDTARB_STATUS0_VPLANE_RDCRDTARB_ABS_AVAIL_NP_H(val)\ argument
6321 #define VXGE_HAL_MRPCIM_DEBUG_STATS0_INI_WR_DROP(val) vBIT(val, 0, 32) argument
6322 #define VXGE_HAL_MRPCIM_DEBUG_STATS0_INI_RD_DROP(val) vBIT(val, 32, 32) argument
6324 #define VXGE_HAL_MRPCIM_DEBUG_STATS1_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED(val)\ argument
6327 #define VXGE_HAL_MRPCIM_DEBUG_STATS2_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED(val)\ argument
6330 #define VXGE_HAL_MRPCIM_DEBUG_STATS3_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED(val)\ argument
6333 #define VXGE_HAL_MRPCIM_DEBUG_STATS4_INI_WR_VPIN_DROP(val) vBIT(val, 0, 32) argument
6334 #define VXGE_HAL_MRPCIM_DEBUG_STATS4_INI_RD_VPIN_DROP(val) vBIT(val, 32, 32) argument
6336 #define VXGE_HAL_GENSTATS_COUNT01_GENSTATS_COUNT1(val) vBIT(val, 0, 32) argument
6337 #define VXGE_HAL_GENSTATS_COUNT01_GENSTATS_COUNT0(val) vBIT(val, 32, 32) argument
6339 #define VXGE_HAL_GENSTATS_COUNT23_GENSTATS_COUNT3(val) vBIT(val, 0, 32) argument
6340 #define VXGE_HAL_GENSTATS_COUNT23_GENSTATS_COUNT2(val) vBIT(val, 32, 32) argument
6342 #define VXGE_HAL_GENSTATS_COUNT4_GENSTATS_COUNT4(val) vBIT(val, 32, 32) argument
6344 #define VXGE_HAL_GENSTATS_COUNT5_GENSTATS_COUNT5(val) vBIT(val, 32, 32) argument
6346 #define VXGE_HAL_MRPCIM_MMIO_CFG1_WRITE_DATA(val) vBIT(val, 0, 32) argument
6347 #define VXGE_HAL_MRPCIM_MMIO_CFG1_ADDRESS(val) vBIT(val, 34, 6) argument
6348 #define VXGE_HAL_MRPCIM_MMIO_CFG1_MRIOVCTL_READ_DATA(val) vBIT(val, 48, 16) argument
6352 #define VXGE_HAL_GENSTATS_CFG_DTYPE_SEL(val) vBIT(val, 3, 5) argument
6353 #define VXGE_HAL_GENSTATS_CFG_CLIENT_NO_SEL(val) vBIT(val, 9, 3) argument
6354 #define VXGE_HAL_GENSTATS_CFG_WR_RD_CPL_SEL(val) vBIT(val, 14, 2) argument
6355 #define VXGE_HAL_GENSTATS_CFG_VPATH_SEL(val) vBIT(val, 31, 17) argument
6360 #define VXGE_HAL_PLL_SLIP_COUNTERS_CMG(val) vBIT(val, 0, 16) argument
6361 #define VXGE_HAL_PLL_SLIP_COUNTERS_FB(val) vBIT(val, 16, 16) argument
6362 #define VXGE_HAL_PLL_SLIP_COUNTERS_X(val) vBIT(val, 32, 16) argument
6375 #define VXGE_HAL_GSTC_ERR0_REG_STC_BDM_CACHE_DB_ERR(val) vBIT(val, 0, 3) argument
6376 #define VXGE_HAL_GSTC_ERR0_REG_STC_BDM_CMRSP_DB_ERR(val) vBIT(val, 3, 5) argument
6377 #define VXGE_HAL_GSTC_ERR0_REG_STC_ECI_CACHE0_DB_ERR(val) vBIT(val, 8, 4) argument
6378 #define VXGE_HAL_GSTC_ERR0_REG_STC_ECI_CACHE1_DB_ERR(val) vBIT(val, 12, 4) argument
6379 #define VXGE_HAL_GSTC_ERR0_REG_STC_H2L_EVENT_DB_ERR(val) vBIT(val, 16, 5) argument
6380 #define VXGE_HAL_GSTC_ERR0_REG_STC_PRM_EVENT_DB_ERR(val) vBIT(val, 21, 3) argument
6381 #define VXGE_HAL_GSTC_ERR0_REG_STC_SRCH_MEM_DB_ERR(val) vBIT(val, 24, 2) argument
6383 #define VXGE_HAL_GSTC_ERR0_REG_STC_BDM_CACHE_SG_ERR(val) vBIT(val, 32, 3) argument
6384 #define VXGE_HAL_GSTC_ERR0_REG_STC_BDM_CMRSP_SG_ERR(val) vBIT(val, 35, 5) argument
6385 #define VXGE_HAL_GSTC_ERR0_REG_STC_ECI_CACHE0_SG_ERR(val) vBIT(val, 40, 4) argument
6386 #define VXGE_HAL_GSTC_ERR0_REG_STC_ECI_CACHE1_SG_ERR(val) vBIT(val, 44, 4) argument
6387 #define VXGE_HAL_GSTC_ERR0_REG_STC_H2L_EVENT_SG_ERR(val) vBIT(val, 48, 5) argument
6388 #define VXGE_HAL_GSTC_ERR0_REG_STC_PRM_EVENT_SG_ERR(val) vBIT(val, 53, 3) argument
6389 #define VXGE_HAL_GSTC_ERR0_REG_STC_SRCH_MEM_SG_ERR(val) vBIT(val, 56, 2) argument
6438 #define VXGE_HAL_GH2L_ERR0_REG_H2L_HOC_DATX_DB_ERR(val) vBIT(val, 0, 2) argument
6439 #define VXGE_HAL_GH2L_ERR0_REG_H2L_WRDBL0_DB_ERR(val) vBIT(val, 2, 2) argument
6440 #define VXGE_HAL_GH2L_ERR0_REG_H2L_WRDBL1_DB_ERR(val) vBIT(val, 4, 2) argument
6441 #define VXGE_HAL_GH2L_ERR0_REG_H2L_WRBUF_DB_ERR(val) vBIT(val, 6, 2) argument
6443 #define VXGE_HAL_GH2L_ERR0_REG_H2L_CMCRSP_DB_ERR(val) vBIT(val, 9, 4) argument
6444 #define VXGE_HAL_GH2L_ERR0_REG_H2L_HOC_HEAD_DB_ERR(val) vBIT(val, 13, 2) argument
6447 #define VXGE_HAL_GH2L_ERR0_REG_H2L_HOC_DATX_SG_ERR(val) vBIT(val, 32, 2) argument
6448 #define VXGE_HAL_GH2L_ERR0_REG_H2L_WRDBL0_SG_ERR(val) vBIT(val, 34, 2) argument
6449 #define VXGE_HAL_GH2L_ERR0_REG_H2L_WRDBL1_SG_ERR(val) vBIT(val, 36, 2) argument
6450 #define VXGE_HAL_GH2L_ERR0_REG_H2L_WRBUF_SG_ERR(val) vBIT(val, 38, 2) argument
6451 #define VXGE_HAL_GH2L_ERR0_REG_H2L_CMCRSP_SG_ERR(val) vBIT(val, 41, 4) argument
6452 #define VXGE_HAL_GH2L_ERR0_REG_H2L_HOC_HEAD_SG_ERR(val) vBIT(val, 45, 2) argument
6532 #define VXGE_HAL_HCC_ALARM_REG_H2L_RWCRA_RW0_SG_ERR(val) vBIT(val, 0, 4) argument
6533 #define VXGE_HAL_HCC_ALARM_REG_H2L_RWCRA_RW0_DB_ERR(val) vBIT(val, 4, 4) argument
6534 #define VXGE_HAL_HCC_ALARM_REG_H2L_RWCRA_RW1_SG_ERR(val) vBIT(val, 8, 4) argument
6535 #define VXGE_HAL_HCC_ALARM_REG_H2L_RWCRA_RW1_DB_ERR(val) vBIT(val, 12, 4) argument
6543 #define VXGE_HAL_GSTC_CFG0_SCC_NBR_FREE_SLOTS(val) vBIT(val, 18, 6) argument
6544 #define VXGE_HAL_GSTC_CFG0_STC_LEFT_HASH_INDEX(val) vBIT(val, 27, 5) argument
6545 #define VXGE_HAL_GSTC_CFG0_STC_RIGHT_HASH_INDEX(val) vBIT(val, 35, 5) argument
6551 #define VXGE_HAL_GSTC_CFG1_INDIRECT_MODE(val) vBIT(val, 0, 17) argument
6552 #define VXGE_HAL_GSTC_CFG1_RPE_PF_COUNTDOWN(val) vBIT(val, 36, 12) argument
6553 #define VXGE_HAL_GSTC_CFG1_BDM_RATE_CTRL(val) vBIT(val, 54, 2) argument
6556 #define VXGE_HAL_GSTC_CFG2_MAX_FRE_CMREQ_ENTRIES(val) vBIT(val, 5, 3) argument
6571 #define VXGE_HAL_GSTC_CFG2_GPSYNC_CNTDOWN_START_VALUE(val) vBIT(val, 36, 4) argument
6573 #define VXGE_HAL_STC_ARB_CFG0_RPE_PRI(val) vBIT(val, 6, 2) argument
6574 #define VXGE_HAL_STC_ARB_CFG0_H2L_PRI(val) vBIT(val, 14, 2) argument
6575 #define VXGE_HAL_STC_ARB_CFG0_CP_PRI(val) vBIT(val, 22, 2) argument
6576 #define VXGE_HAL_STC_ARB_CFG0_CAL0_PRI(val) vBIT(val, 30, 2) argument
6577 #define VXGE_HAL_STC_ARB_CFG0_CAL1_PRI(val) vBIT(val, 38, 2) argument
6578 #define VXGE_HAL_STC_ARB_CFG0_CAL2_PRI(val) vBIT(val, 46, 2) argument
6579 #define VXGE_HAL_STC_ARB_CFG0_CAL3_PRI(val) vBIT(val, 54, 2) argument
6580 #define VXGE_HAL_STC_ARB_CFG0_CAL4_PRI(val) vBIT(val, 62, 2) argument
6582 #define VXGE_HAL_STC_ARB_CFG1_CAL5_PRI(val) vBIT(val, 6, 2) argument
6583 #define VXGE_HAL_STC_ARB_CFG1_CAL6_PRI(val) vBIT(val, 14, 2) argument
6584 #define VXGE_HAL_STC_ARB_CFG1_CAL7_PRI(val) vBIT(val, 22, 2) argument
6585 #define VXGE_HAL_STC_ARB_CFG1_CAL8_PRI(val) vBIT(val, 30, 2) argument
6587 #define VXGE_HAL_STC_ARB_CFG2_MAX_NBR_H2L0_EVENTS(val) vBIT(val, 4, 4) argument
6588 #define VXGE_HAL_STC_ARB_CFG2_MAX_NBR_H2L1_EVENTS(val) vBIT(val, 12, 4) argument
6589 #define VXGE_HAL_STC_ARB_CFG2_MAX_NBR_H2L2_EVENTS(val) vBIT(val, 20, 4) argument
6590 #define VXGE_HAL_STC_ARB_CFG2_MAX_NBR_H2L3_EVENTS(val) vBIT(val, 28, 4) argument
6591 #define VXGE_HAL_STC_ARB_CFG2_MAX_NBR_RPE_EVENTS(val) vBIT(val, 35, 5) argument
6592 #define VXGE_HAL_STC_ARB_CFG2_MAX_NBR_MR_EVENTS(val) vBIT(val, 45, 3) argument
6594 #define VXGE_HAL_STC_ARB_CFG3_MAX_NBR_H2L0_FETCHES(val) vBIT(val, 5, 3) argument
6595 #define VXGE_HAL_STC_ARB_CFG3_MAX_NBR_H2L1_FETCHES(val) vBIT(val, 13, 3) argument
6596 #define VXGE_HAL_STC_ARB_CFG3_MAX_NBR_H2L2_FETCHES(val) vBIT(val, 21, 3) argument
6597 #define VXGE_HAL_STC_ARB_CFG3_MAX_NBR_H2L3_FETCHES(val) vBIT(val, 29, 3) argument
6598 #define VXGE_HAL_STC_ARB_CFG3_MAX_NBR_RPE_FETCHES(val) vBIT(val, 37, 3) argument
6599 #define VXGE_HAL_STC_ARB_CFG3_MAX_NBR_RPE_PF_FETCHES(val) vBIT(val, 46, 2) argument
6601 #define VXGE_HAL_STC_JHASH_CFG_GOLDEN(val) vBIT(val, 0, 32) argument
6602 #define VXGE_HAL_STC_JHASH_CFG_INIT_VAL(val) vBIT(val, 32, 32) argument
6604 #define VXGE_HAL_STC_SMI_ARB_CFG0_RPE_PRI(val) vBIT(val, 6, 2) argument
6605 #define VXGE_HAL_STC_SMI_ARB_CFG0_H2L_PRI(val) vBIT(val, 14, 2) argument
6606 #define VXGE_HAL_STC_SMI_ARB_CFG0_CP_PRI(val) vBIT(val, 22, 2) argument
6607 #define VXGE_HAL_STC_SMI_ARB_CFG0_CAL0_PRI(val) vBIT(val, 30, 2) argument
6608 #define VXGE_HAL_STC_SMI_ARB_CFG0_CAL1_PRI(val) vBIT(val, 38, 2) argument
6609 #define VXGE_HAL_STC_SMI_ARB_CFG0_CAL2_PRI(val) vBIT(val, 46, 2) argument
6610 #define VXGE_HAL_STC_SMI_ARB_CFG0_CAL3_PRI(val) vBIT(val, 54, 2) argument
6611 #define VXGE_HAL_STC_SMI_ARB_CFG0_CAL4_PRI(val) vBIT(val, 62, 2) argument
6613 #define VXGE_HAL_STC_SMI_ARB_CFG1_CAL5_PRI(val) vBIT(val, 6, 2) argument
6614 #define VXGE_HAL_STC_SMI_ARB_CFG1_CAL6_PRI(val) vBIT(val, 14, 2) argument
6615 #define VXGE_HAL_STC_SMI_ARB_CFG1_CAL7_PRI(val) vBIT(val, 22, 2) argument
6616 #define VXGE_HAL_STC_SMI_ARB_CFG1_CAL8_PRI(val) vBIT(val, 30, 2) argument
6617 #define VXGE_HAL_STC_SMI_ARB_CFG1_CAL9_PRI(val) vBIT(val, 38, 2) argument
6620 #define VXGE_HAL_STC_CAA_ARB_CFG0_RPE_PRI(val) vBIT(val, 6, 2) argument
6621 #define VXGE_HAL_STC_CAA_ARB_CFG0_H2L_PRI(val) vBIT(val, 14, 2) argument
6622 #define VXGE_HAL_STC_CAA_ARB_CFG0_CP_PRI(val) vBIT(val, 22, 2) argument
6623 #define VXGE_HAL_STC_CAA_ARB_CFG0_CAL0_PRI(val) vBIT(val, 30, 2) argument
6624 #define VXGE_HAL_STC_CAA_ARB_CFG0_CAL1_PRI(val) vBIT(val, 38, 2) argument
6625 #define VXGE_HAL_STC_CAA_ARB_CFG0_CAL2_PRI(val) vBIT(val, 46, 2) argument
6626 #define VXGE_HAL_STC_CAA_ARB_CFG0_CAL3_PRI(val) vBIT(val, 54, 2) argument
6627 #define VXGE_HAL_STC_CAA_ARB_CFG0_CAL4_PRI(val) vBIT(val, 62, 2) argument
6629 #define VXGE_HAL_STC_CAA_ARB_CFG1_CAL5_PRI(val) vBIT(val, 6, 2) argument
6630 #define VXGE_HAL_STC_CAA_ARB_CFG1_CAL6_PRI(val) vBIT(val, 14, 2) argument
6631 #define VXGE_HAL_STC_CAA_ARB_CFG1_CAL7_PRI(val) vBIT(val, 22, 2) argument
6632 #define VXGE_HAL_STC_CAA_ARB_CFG1_CAL8_PRI(val) vBIT(val, 30, 2) argument
6635 #define VXGE_HAL_STC_ECI_ARB_CFG0_RPE_PRI(val) vBIT(val, 6, 2) argument
6636 #define VXGE_HAL_STC_ECI_ARB_CFG0_H2L_PRI(val) vBIT(val, 14, 2) argument
6637 #define VXGE_HAL_STC_ECI_ARB_CFG0_CP_PRI(val) vBIT(val, 22, 2) argument
6638 #define VXGE_HAL_STC_ECI_ARB_CFG0_CAL0_PRI(val) vBIT(val, 30, 2) argument
6639 #define VXGE_HAL_STC_ECI_ARB_CFG0_CAL1_PRI(val) vBIT(val, 38, 2) argument
6640 #define VXGE_HAL_STC_ECI_ARB_CFG0_CAL2_PRI(val) vBIT(val, 46, 2) argument
6641 #define VXGE_HAL_STC_ECI_ARB_CFG0_CAL3_PRI(val) vBIT(val, 54, 2) argument
6642 #define VXGE_HAL_STC_ECI_ARB_CFG0_CAL4_PRI(val) vBIT(val, 62, 2) argument
6644 #define VXGE_HAL_STC_ECI_ARB_CFG1_CAL5_PRI(val) vBIT(val, 6, 2) argument
6645 #define VXGE_HAL_STC_ECI_ARB_CFG1_CAL6_PRI(val) vBIT(val, 14, 2) argument
6646 #define VXGE_HAL_STC_ECI_ARB_CFG1_CAL7_PRI(val) vBIT(val, 22, 2) argument
6647 #define VXGE_HAL_STC_ECI_ARB_CFG1_CAL8_PRI(val) vBIT(val, 30, 2) argument
6663 #define VXGE_HAL_STC_ECI_CFG0_RESUBMIT_INTERVAL(val) vBIT(val, 40, 8) argument
6705 #define VXGE_HAL_H2L_MISC_CFG_HOCHEAD_RD_THRES(val) vBIT(val, 10, 6) argument
6706 #define VXGE_HAL_H2L_MISC_CFG_HCC_WB_THRESHOLD(val) vBIT(val, 19, 5) argument
6707 #define VXGE_HAL_H2L_MISC_CFG_HOP_BCK_STATS_MODE(val) vBIT(val, 25, 2) argument
6708 #define VXGE_HAL_H2L_MISC_CFG_HOP_BCK_STATS_VPATH(val) vBIT(val, 27, 5) argument
6717 #define VXGE_HAL_HSQ_CFG_BASE_ADDR(val) vBIT(val, 8, 24) argument
6718 #define VXGE_HAL_HSQ_CFG_SIZE224(val) vBIT(val, 40, 24) argument
6720 #define VXGE_HAL_USDC_VPBP_CFG_THRES224(val) vBIT(val, 8, 24) argument
6721 #define VXGE_HAL_USDC_VPBP_CFG_HYST224(val) vBIT(val, 40, 24) argument
6723 #define VXGE_HAL_KDFC_VPBP_CFG_THRES224(val) vBIT(val, 8, 24) argument
6724 #define VXGE_HAL_KDFC_VPBP_CFG_HYST224(val) vBIT(val, 40, 24) argument
6726 #define VXGE_HAL_TXPE_VPBP_CFG_THRES224(val) vBIT(val, 8, 24) argument
6727 #define VXGE_HAL_TXPE_VPBP_CFG_HYST224(val) vBIT(val, 40, 24) argument
6729 #define VXGE_HAL_ONE_VPBP_CFG_THRES224(val) vBIT(val, 8, 24) argument
6730 #define VXGE_HAL_ONE_VPBP_CFG_HYST224(val) vBIT(val, 40, 24) argument
6732 #define VXGE_HAL_HOPARB_WRR_CTRL_0_SS_0_NUM(val) vBIT(val, 3, 5) argument
6733 #define VXGE_HAL_HOPARB_WRR_CTRL_0_SS_1_NUM(val) vBIT(val, 11, 5) argument
6734 #define VXGE_HAL_HOPARB_WRR_CTRL_0_SS_2_NUM(val) vBIT(val, 19, 5) argument
6735 #define VXGE_HAL_HOPARB_WRR_CTRL_0_SS_3_NUM(val) vBIT(val, 27, 5) argument
6736 #define VXGE_HAL_HOPARB_WRR_CTRL_0_SS_4_NUM(val) vBIT(val, 35, 5) argument
6737 #define VXGE_HAL_HOPARB_WRR_CTRL_0_SS_5_NUM(val) vBIT(val, 43, 5) argument
6738 #define VXGE_HAL_HOPARB_WRR_CTRL_0_SS_6_NUM(val) vBIT(val, 51, 5) argument
6739 #define VXGE_HAL_HOPARB_WRR_CTRL_0_SS_7_NUM(val) vBIT(val, 59, 5) argument
6741 #define VXGE_HAL_HOPARB_WRR_CTRL_1_SS_8_NUM(val) vBIT(val, 3, 5) argument
6742 #define VXGE_HAL_HOPARB_WRR_CTRL_1_SS_9_NUM(val) vBIT(val, 11, 5) argument
6743 #define VXGE_HAL_HOPARB_WRR_CTRL_1_SS_10_NUM(val) vBIT(val, 19, 5) argument
6744 #define VXGE_HAL_HOPARB_WRR_CTRL_1_SS_11_NUM(val) vBIT(val, 27, 5) argument
6745 #define VXGE_HAL_HOPARB_WRR_CTRL_1_SS_12_NUM(val) vBIT(val, 35, 5) argument
6746 #define VXGE_HAL_HOPARB_WRR_CTRL_1_SS_13_NUM(val) vBIT(val, 43, 5) argument
6747 #define VXGE_HAL_HOPARB_WRR_CTRL_1_SS_14_NUM(val) vBIT(val, 51, 5) argument
6748 #define VXGE_HAL_HOPARB_WRR_CTRL_1_SS_15_NUM(val) vBIT(val, 59, 5) argument
6750 #define VXGE_HAL_HOPARB_WRR_CTRL_2_SS_16_NUM(val) vBIT(val, 3, 5) argument
6751 #define VXGE_HAL_HOPARB_WRR_CTRL_2_SS_17_NUM(val) vBIT(val, 11, 5) argument
6752 #define VXGE_HAL_HOPARB_WRR_CTRL_2_SS_18_NUM(val) vBIT(val, 19, 5) argument
6753 #define VXGE_HAL_HOPARB_WRR_CTRL_2_SS_19_NUM(val) vBIT(val, 27, 5) argument
6754 #define VXGE_HAL_HOPARB_WRR_CTRL_2_SS_20_NUM(val) vBIT(val, 35, 5) argument
6755 #define VXGE_HAL_HOPARB_WRR_CTRL_2_SS_21_NUM(val) vBIT(val, 43, 5) argument
6756 #define VXGE_HAL_HOPARB_WRR_CTRL_2_SS_22_NUM(val) vBIT(val, 51, 5) argument
6757 #define VXGE_HAL_HOPARB_WRR_CTRL_2_SS_23_NUM(val) vBIT(val, 59, 5) argument
6759 #define VXGE_HAL_HOPARB_WRR_CTRL_3_SS_24_NUM(val) vBIT(val, 3, 5) argument
6760 #define VXGE_HAL_HOPARB_WRR_CTRL_3_SS_25_NUM(val) vBIT(val, 11, 5) argument
6761 #define VXGE_HAL_HOPARB_WRR_CTRL_3_SS_26_NUM(val) vBIT(val, 19, 5) argument
6762 #define VXGE_HAL_HOPARB_WRR_CTRL_3_SS_27_NUM(val) vBIT(val, 27, 5) argument
6763 #define VXGE_HAL_HOPARB_WRR_CTRL_3_SS_28_NUM(val) vBIT(val, 35, 5) argument
6764 #define VXGE_HAL_HOPARB_WRR_CTRL_3_SS_29_NUM(val) vBIT(val, 43, 5) argument
6765 #define VXGE_HAL_HOPARB_WRR_CTRL_3_SS_30_NUM(val) vBIT(val, 51, 5) argument
6766 #define VXGE_HAL_HOPARB_WRR_CTRL_3_SS_31_NUM(val) vBIT(val, 59, 5) argument
6768 #define VXGE_HAL_HOPARB_WRR_CTRL_4_SS_32_NUM(val) vBIT(val, 3, 5) argument
6769 #define VXGE_HAL_HOPARB_WRR_CTRL_4_SS_33_NUM(val) vBIT(val, 11, 5) argument
6770 #define VXGE_HAL_HOPARB_WRR_CTRL_4_SS_34_NUM(val) vBIT(val, 19, 5) argument
6771 #define VXGE_HAL_HOPARB_WRR_CTRL_4_SS_35_NUM(val) vBIT(val, 27, 5) argument
6772 #define VXGE_HAL_HOPARB_WRR_CTRL_4_SS_36_NUM(val) vBIT(val, 35, 5) argument
6773 #define VXGE_HAL_HOPARB_WRR_CTRL_4_SS_37_NUM(val) vBIT(val, 43, 5) argument
6774 #define VXGE_HAL_HOPARB_WRR_CTRL_4_SS_38_NUM(val) vBIT(val, 51, 5) argument
6775 #define VXGE_HAL_HOPARB_WRR_CTRL_4_SS_39_NUM(val) vBIT(val, 59, 5) argument
6777 #define VXGE_HAL_HOPARB_WRR_CTRL_5_SS_40_NUM(val) vBIT(val, 3, 5) argument
6778 #define VXGE_HAL_HOPARB_WRR_CTRL_5_SS_41_NUM(val) vBIT(val, 11, 5) argument
6779 #define VXGE_HAL_HOPARB_WRR_CTRL_5_SS_42_NUM(val) vBIT(val, 19, 5) argument
6780 #define VXGE_HAL_HOPARB_WRR_CTRL_5_SS_43_NUM(val) vBIT(val, 27, 5) argument
6781 #define VXGE_HAL_HOPARB_WRR_CTRL_5_SS_44_NUM(val) vBIT(val, 35, 5) argument
6782 #define VXGE_HAL_HOPARB_WRR_CTRL_5_SS_45_NUM(val) vBIT(val, 43, 5) argument
6783 #define VXGE_HAL_HOPARB_WRR_CTRL_5_SS_46_NUM(val) vBIT(val, 51, 5) argument
6784 #define VXGE_HAL_HOPARB_WRR_CTRL_5_SS_47_NUM(val) vBIT(val, 59, 5) argument
6786 #define VXGE_HAL_HOPARB_WRR_CTRL_6_SS_48_NUM(val) vBIT(val, 3, 5) argument
6787 #define VXGE_HAL_HOPARB_WRR_CTRL_6_SS_49_NUM(val) vBIT(val, 11, 5) argument
6788 #define VXGE_HAL_HOPARB_WRR_CTRL_6_SS_50_NUM(val) vBIT(val, 19, 5) argument
6789 #define VXGE_HAL_HOPARB_WRR_CTRL_6_SS_51_NUM(val) vBIT(val, 27, 5) argument
6790 #define VXGE_HAL_HOPARB_WRR_CTRL_6_SS_52_NUM(val) vBIT(val, 35, 5) argument
6791 #define VXGE_HAL_HOPARB_WRR_CTRL_6_SS_53_NUM(val) vBIT(val, 43, 5) argument
6792 #define VXGE_HAL_HOPARB_WRR_CTRL_6_SS_54_NUM(val) vBIT(val, 51, 5) argument
6793 #define VXGE_HAL_HOPARB_WRR_CTRL_6_SS_55_NUM(val) vBIT(val, 59, 5) argument
6795 #define VXGE_HAL_HOPARB_WRR_CTRL_7_SS_56_NUM(val) vBIT(val, 3, 5) argument
6796 #define VXGE_HAL_HOPARB_WRR_CTRL_7_SS_57_NUM(val) vBIT(val, 11, 5) argument
6797 #define VXGE_HAL_HOPARB_WRR_CTRL_7_SS_58_NUM(val) vBIT(val, 19, 5) argument
6798 #define VXGE_HAL_HOPARB_WRR_CTRL_7_SS_59_NUM(val) vBIT(val, 27, 5) argument
6799 #define VXGE_HAL_HOPARB_WRR_CTRL_7_SS_60_NUM(val) vBIT(val, 35, 5) argument
6800 #define VXGE_HAL_HOPARB_WRR_CTRL_7_SS_61_NUM(val) vBIT(val, 43, 5) argument
6801 #define VXGE_HAL_HOPARB_WRR_CTRL_7_SS_62_NUM(val) vBIT(val, 51, 5) argument
6802 #define VXGE_HAL_HOPARB_WRR_CTRL_7_SS_63_NUM(val) vBIT(val, 59, 5) argument
6804 #define VXGE_HAL_HOPARB_WRR_CTRL_8_SS_64_NUM(val) vBIT(val, 3, 5) argument
6805 #define VXGE_HAL_HOPARB_WRR_CTRL_8_SS_65_NUM(val) vBIT(val, 11, 5) argument
6806 #define VXGE_HAL_HOPARB_WRR_CTRL_8_SS_66_NUM(val) vBIT(val, 19, 5) argument
6807 #define VXGE_HAL_HOPARB_WRR_CTRL_8_SS_67_NUM(val) vBIT(val, 27, 5) argument
6808 #define VXGE_HAL_HOPARB_WRR_CTRL_8_SS_68_NUM(val) vBIT(val, 35, 5) argument
6809 #define VXGE_HAL_HOPARB_WRR_CTRL_8_SS_69_NUM(val) vBIT(val, 43, 5) argument
6810 #define VXGE_HAL_HOPARB_WRR_CTRL_8_SS_70_NUM(val) vBIT(val, 51, 5) argument
6811 #define VXGE_HAL_HOPARB_WRR_CTRL_8_SS_71_NUM(val) vBIT(val, 59, 5) argument
6813 #define VXGE_HAL_HOPARB_WRR_CTRL_9_SS_72_NUM(val) vBIT(val, 3, 5) argument
6814 #define VXGE_HAL_HOPARB_WRR_CTRL_9_SS_73_NUM(val) vBIT(val, 11, 5) argument
6815 #define VXGE_HAL_HOPARB_WRR_CTRL_9_SS_74_NUM(val) vBIT(val, 19, 5) argument
6816 #define VXGE_HAL_HOPARB_WRR_CTRL_9_SS_75_NUM(val) vBIT(val, 27, 5) argument
6817 #define VXGE_HAL_HOPARB_WRR_CTRL_9_SS_76_NUM(val) vBIT(val, 35, 5) argument
6818 #define VXGE_HAL_HOPARB_WRR_CTRL_9_SS_77_NUM(val) vBIT(val, 43, 5) argument
6819 #define VXGE_HAL_HOPARB_WRR_CTRL_9_SS_78_NUM(val) vBIT(val, 51, 5) argument
6820 #define VXGE_HAL_HOPARB_WRR_CTRL_9_SS_79_NUM(val) vBIT(val, 59, 5) argument
6822 #define VXGE_HAL_HOPARB_WRR_CTRL_10_SS_80_NUM(val) vBIT(val, 3, 5) argument
6823 #define VXGE_HAL_HOPARB_WRR_CTRL_10_SS_81_NUM(val) vBIT(val, 11, 5) argument
6824 #define VXGE_HAL_HOPARB_WRR_CTRL_10_SS_82_NUM(val) vBIT(val, 19, 5) argument
6825 #define VXGE_HAL_HOPARB_WRR_CTRL_10_SS_83_NUM(val) vBIT(val, 27, 5) argument
6826 #define VXGE_HAL_HOPARB_WRR_CTRL_10_SS_84_NUM(val) vBIT(val, 35, 5) argument
6827 #define VXGE_HAL_HOPARB_WRR_CTRL_10_SS_85_NUM(val) vBIT(val, 43, 5) argument
6828 #define VXGE_HAL_HOPARB_WRR_CTRL_10_SS_86_NUM(val) vBIT(val, 51, 5) argument
6829 #define VXGE_HAL_HOPARB_WRR_CTRL_10_SS_87_NUM(val) vBIT(val, 59, 5) argument
6831 #define VXGE_HAL_HOPARB_WRR_CTRL_11_SS_88_NUM(val) vBIT(val, 3, 5) argument
6832 #define VXGE_HAL_HOPARB_WRR_CTRL_11_SS_89_NUM(val) vBIT(val, 11, 5) argument
6833 #define VXGE_HAL_HOPARB_WRR_CTRL_11_SS_90_NUM(val) vBIT(val, 19, 5) argument
6834 #define VXGE_HAL_HOPARB_WRR_CTRL_11_SS_91_NUM(val) vBIT(val, 27, 5) argument
6835 #define VXGE_HAL_HOPARB_WRR_CTRL_11_SS_92_NUM(val) vBIT(val, 35, 5) argument
6836 #define VXGE_HAL_HOPARB_WRR_CTRL_11_SS_93_NUM(val) vBIT(val, 43, 5) argument
6837 #define VXGE_HAL_HOPARB_WRR_CTRL_11_SS_94_NUM(val) vBIT(val, 51, 5) argument
6838 #define VXGE_HAL_HOPARB_WRR_CTRL_11_SS_95_NUM(val) vBIT(val, 59, 5) argument
6840 #define VXGE_HAL_HOPARB_WRR_CTRL_12_SS_96_NUM(val) vBIT(val, 3, 5) argument
6841 #define VXGE_HAL_HOPARB_WRR_CTRL_12_SS_97_NUM(val) vBIT(val, 11, 5) argument
6842 #define VXGE_HAL_HOPARB_WRR_CTRL_12_SS_98_NUM(val) vBIT(val, 19, 5) argument
6843 #define VXGE_HAL_HOPARB_WRR_CTRL_12_SS_99_NUM(val) vBIT(val, 27, 5) argument
6844 #define VXGE_HAL_HOPARB_WRR_CTRL_12_SS_100_NUM(val) vBIT(val, 35, 5) argument
6845 #define VXGE_HAL_HOPARB_WRR_CTRL_12_SS_101_NUM(val) vBIT(val, 43, 5) argument
6846 #define VXGE_HAL_HOPARB_WRR_CTRL_12_SS_102_NUM(val) vBIT(val, 51, 5) argument
6847 #define VXGE_HAL_HOPARB_WRR_CTRL_12_SS_103_NUM(val) vBIT(val, 59, 5) argument
6849 #define VXGE_HAL_HOPARB_WRR_CTRL_13_SS_104_NUM(val) vBIT(val, 3, 5) argument
6850 #define VXGE_HAL_HOPARB_WRR_CTRL_13_SS_105_NUM(val) vBIT(val, 11, 5) argument
6851 #define VXGE_HAL_HOPARB_WRR_CTRL_13_SS_106_NUM(val) vBIT(val, 19, 5) argument
6852 #define VXGE_HAL_HOPARB_WRR_CTRL_13_SS_107_NUM(val) vBIT(val, 27, 5) argument
6853 #define VXGE_HAL_HOPARB_WRR_CTRL_13_SS_108_NUM(val) vBIT(val, 35, 5) argument
6854 #define VXGE_HAL_HOPARB_WRR_CTRL_13_SS_109_NUM(val) vBIT(val, 43, 5) argument
6855 #define VXGE_HAL_HOPARB_WRR_CTRL_13_SS_110_NUM(val) vBIT(val, 51, 5) argument
6856 #define VXGE_HAL_HOPARB_WRR_CTRL_13_SS_111_NUM(val) vBIT(val, 59, 5) argument
6858 #define VXGE_HAL_HOPARB_WRR_CTRL_14_SS_112_NUM(val) vBIT(val, 3, 5) argument
6859 #define VXGE_HAL_HOPARB_WRR_CTRL_14_SS_113_NUM(val) vBIT(val, 11, 5) argument
6860 #define VXGE_HAL_HOPARB_WRR_CTRL_14_SS_114_NUM(val) vBIT(val, 19, 5) argument
6861 #define VXGE_HAL_HOPARB_WRR_CTRL_14_SS_115_NUM(val) vBIT(val, 27, 5) argument
6862 #define VXGE_HAL_HOPARB_WRR_CTRL_14_SS_116_NUM(val) vBIT(val, 35, 5) argument
6863 #define VXGE_HAL_HOPARB_WRR_CTRL_14_SS_117_NUM(val) vBIT(val, 43, 5) argument
6864 #define VXGE_HAL_HOPARB_WRR_CTRL_14_SS_118_NUM(val) vBIT(val, 51, 5) argument
6865 #define VXGE_HAL_HOPARB_WRR_CTRL_14_SS_119_NUM(val) vBIT(val, 59, 5) argument
6867 #define VXGE_HAL_HOPARB_WRR_CTRL_15_SS_120_NUM(val) vBIT(val, 3, 5) argument
6868 #define VXGE_HAL_HOPARB_WRR_CTRL_15_SS_121_NUM(val) vBIT(val, 11, 5) argument
6869 #define VXGE_HAL_HOPARB_WRR_CTRL_15_SS_122_NUM(val) vBIT(val, 19, 5) argument
6870 #define VXGE_HAL_HOPARB_WRR_CTRL_15_SS_123_NUM(val) vBIT(val, 27, 5) argument
6871 #define VXGE_HAL_HOPARB_WRR_CTRL_15_SS_124_NUM(val) vBIT(val, 35, 5) argument
6872 #define VXGE_HAL_HOPARB_WRR_CTRL_15_SS_125_NUM(val) vBIT(val, 43, 5) argument
6873 #define VXGE_HAL_HOPARB_WRR_CTRL_15_SS_126_NUM(val) vBIT(val, 51, 5) argument
6874 #define VXGE_HAL_HOPARB_WRR_CTRL_15_SS_127_NUM(val) vBIT(val, 59, 5) argument
6876 #define VXGE_HAL_HOPARB_WRR_CTRL_16_SS_128_NUM(val) vBIT(val, 3, 5) argument
6877 #define VXGE_HAL_HOPARB_WRR_CTRL_16_SS_129_NUM(val) vBIT(val, 11, 5) argument
6878 #define VXGE_HAL_HOPARB_WRR_CTRL_16_SS_130_NUM(val) vBIT(val, 19, 5) argument
6879 #define VXGE_HAL_HOPARB_WRR_CTRL_16_SS_131_NUM(val) vBIT(val, 27, 5) argument
6880 #define VXGE_HAL_HOPARB_WRR_CTRL_16_SS_132_NUM(val) vBIT(val, 35, 5) argument
6881 #define VXGE_HAL_HOPARB_WRR_CTRL_16_SS_133_NUM(val) vBIT(val, 43, 5) argument
6882 #define VXGE_HAL_HOPARB_WRR_CTRL_16_SS_134_NUM(val) vBIT(val, 51, 5) argument
6883 #define VXGE_HAL_HOPARB_WRR_CTRL_16_SS_135_NUM(val) vBIT(val, 59, 5) argument
6885 #define VXGE_HAL_HOPARB_WRR_CTRL_17_SS_136_NUM(val) vBIT(val, 3, 5) argument
6886 #define VXGE_HAL_HOPARB_WRR_CTRL_17_SS_137_NUM(val) vBIT(val, 11, 5) argument
6887 #define VXGE_HAL_HOPARB_WRR_CTRL_17_SS_138_NUM(val) vBIT(val, 19, 5) argument
6888 #define VXGE_HAL_HOPARB_WRR_CTRL_17_SS_139_NUM(val) vBIT(val, 27, 5) argument
6889 #define VXGE_HAL_HOPARB_WRR_CTRL_17_SS_140_NUM(val) vBIT(val, 35, 5) argument
6890 #define VXGE_HAL_HOPARB_WRR_CTRL_17_SS_141_NUM(val) vBIT(val, 43, 5) argument
6891 #define VXGE_HAL_HOPARB_WRR_CTRL_17_SS_142_NUM(val) vBIT(val, 51, 5) argument
6892 #define VXGE_HAL_HOPARB_WRR_CTRL_17_SS_143_NUM(val) vBIT(val, 59, 5) argument
6894 #define VXGE_HAL_HOPARB_WRR_CTRL_18_SS_144_NUM(val) vBIT(val, 3, 5) argument
6895 #define VXGE_HAL_HOPARB_WRR_CTRL_18_SS_145_NUM(val) vBIT(val, 11, 5) argument
6896 #define VXGE_HAL_HOPARB_WRR_CTRL_18_SS_146_NUM(val) vBIT(val, 19, 5) argument
6897 #define VXGE_HAL_HOPARB_WRR_CTRL_18_SS_147_NUM(val) vBIT(val, 27, 5) argument
6898 #define VXGE_HAL_HOPARB_WRR_CTRL_18_SS_148_NUM(val) vBIT(val, 35, 5) argument
6899 #define VXGE_HAL_HOPARB_WRR_CTRL_18_SS_149_NUM(val) vBIT(val, 43, 5) argument
6900 #define VXGE_HAL_HOPARB_WRR_CTRL_18_SS_150_NUM(val) vBIT(val, 51, 5) argument
6901 #define VXGE_HAL_HOPARB_WRR_CTRL_18_SS_151_NUM(val) vBIT(val, 59, 5) argument
6903 #define VXGE_HAL_HOPARB_WRR_CTRL_19_SS_152_NUM(val) vBIT(val, 3, 5) argument
6905 #define VXGE_HAL_HOPARB_WRR_CMP_0_VP0_NUM(val) vBIT(val, 3, 5) argument
6906 #define VXGE_HAL_HOPARB_WRR_CMP_0_VP1_NUM(val) vBIT(val, 11, 5) argument
6907 #define VXGE_HAL_HOPARB_WRR_CMP_0_VP2_NUM(val) vBIT(val, 19, 5) argument
6908 #define VXGE_HAL_HOPARB_WRR_CMP_0_VP3_NUM(val) vBIT(val, 27, 5) argument
6909 #define VXGE_HAL_HOPARB_WRR_CMP_0_VP4_NUM(val) vBIT(val, 35, 5) argument
6910 #define VXGE_HAL_HOPARB_WRR_CMP_0_VP5_NUM(val) vBIT(val, 43, 5) argument
6911 #define VXGE_HAL_HOPARB_WRR_CMP_0_VP6_NUM(val) vBIT(val, 51, 5) argument
6912 #define VXGE_HAL_HOPARB_WRR_CMP_0_VP7_NUM(val) vBIT(val, 59, 5) argument
6914 #define VXGE_HAL_HOPARB_WRR_CMP_1_VP8_NUM(val) vBIT(val, 3, 5) argument
6915 #define VXGE_HAL_HOPARB_WRR_CMP_1_VP9_NUM(val) vBIT(val, 11, 5) argument
6916 #define VXGE_HAL_HOPARB_WRR_CMP_1_VP10_NUM(val) vBIT(val, 19, 5) argument
6917 #define VXGE_HAL_HOPARB_WRR_CMP_1_VP11_NUM(val) vBIT(val, 27, 5) argument
6918 #define VXGE_HAL_HOPARB_WRR_CMP_1_VP12_NUM(val) vBIT(val, 35, 5) argument
6919 #define VXGE_HAL_HOPARB_WRR_CMP_1_VP13_NUM(val) vBIT(val, 43, 5) argument
6920 #define VXGE_HAL_HOPARB_WRR_CMP_1_VP14_NUM(val) vBIT(val, 51, 5) argument
6921 #define VXGE_HAL_HOPARB_WRR_CMP_1_VP15_NUM(val) vBIT(val, 59, 5) argument
6923 #define VXGE_HAL_HOPARB_WRR_CMP_2_VP16_NUM(val) vBIT(val, 3, 5) argument
6927 #define VXGE_HAL_HOP_BCK_STATS0_HO_DISPATCH_CNT(val) vBIT(val, 0, 32) argument
6928 #define VXGE_HAL_HOP_BCK_STATS0_HO_DROP_CNT(val) vBIT(val, 32, 32) argument
6973 #define VXGE_HAL_PH2L_ERR0_REG_H2L_PHDR_MEM_DB_ERR(val) vBIT(val, 8, 2) argument
6974 #define VXGE_HAL_PH2L_ERR0_REG_H2L_IDATA_MEM_DB_ERR(val) vBIT(val, 10, 2) argument
6975 #define VXGE_HAL_PH2L_ERR0_REG_H2L_RO_CACHE_DB_ERR(val) vBIT(val, 12, 3) argument
7001 #define VXGE_HAL_PH2L_ERR0_REG_H2L_PHDR_MEM_SG_ERR(val) vBIT(val, 48, 2) argument
7002 #define VXGE_HAL_PH2L_ERR0_REG_H2L_IDATA_MEM_SG_ERR(val) vBIT(val, 50, 2) argument
7003 #define VXGE_HAL_PH2L_ERR0_REG_H2L_RO_CACHE_SG_ERR(val) vBIT(val, 52, 3) argument
7009 #define VXGE_HAL_DAM_BYPASS_QUEUE_0_BASE(val) vBIT(val, 8, 24) argument
7010 #define VXGE_HAL_DAM_BYPASS_QUEUE_0_LENGTH(val) vBIT(val, 40, 24) argument
7012 #define VXGE_HAL_DAM_BYPASS_QUEUE_1_BASE(val) vBIT(val, 8, 24) argument
7013 #define VXGE_HAL_DAM_BYPASS_QUEUE_1_LENGTH(val) vBIT(val, 40, 24) argument
7015 #define VXGE_HAL_DAM_BYPASS_QUEUE_2_BASE(val) vBIT(val, 8, 24) argument
7016 #define VXGE_HAL_DAM_BYPASS_QUEUE_2_LENGTH(val) vBIT(val, 40, 24) argument
7026 #define VXGE_HAL_PH2L_CFG0_NBR_RETX_SLOTS_PER_VP(val) vBIT(val, 62, 2) argument
7031 #define VXGE_HAL_PSTC_CFG0_PGSYNC_CNTDOWN_START_VALUE(val) vBIT(val, 12, 4) argument
7053 #define VXGE_HAL_NETERION_MEMBIST_CONTROL_NMBC_ERROR(val) vBIT(val, 56, 4) argument
7055 #define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_CMG1(val) vBIT(val, 0, 3) argument
7056 #define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_CMG2(val) vBIT(val, 3, 3) argument
7057 #define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_CMG3(val) vBIT(val, 6, 3) argument
7058 #define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_DRBELL(val) vBIT(val, 9, 3) argument
7060 #define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_MSG(val) vBIT(val, 15, 3) argument
7061 #define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_ONE(val) vBIT(val, 18, 3) argument
7062 #define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_PCI(val) vBIT(val, 21, 3) argument
7063 #define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_RTDMA(val) vBIT(val, 24, 3) argument
7064 #define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_WRDMA(val) vBIT(val, 27, 3) argument
7065 #define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_XGMAC(val) vBIT(val, 30, 3) argument
7069 #define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7071 #define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK1_FUSE(val)\ argument
7073 #define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK1_ADD_FUSE(val)\ argument
7075 #define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK0_FUSE(val)\ argument
7077 #define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK0_ADD_FUSE(val)\ argument
7080 #define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7082 #define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK1_FUSE(val)\ argument
7084 #define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK1_ADD_FUSE(val)\ argument
7086 #define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK0_FUSE(val)\ argument
7088 #define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK0_ADD_FUSE(val)\ argument
7091 #define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7093 #define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK1_FUSE(val)\ argument
7095 #define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK1_ADD_FUSE(val)\ argument
7097 #define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK0_FUSE(val)\ argument
7099 #define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK0_ADD_FUSE(val)\ argument
7102 #define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7104 #define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK1_FUSE(val)\ argument
7106 #define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK1_ADD_FUSE(val)\ argument
7108 #define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK0_FUSE(val)\ argument
7110 #define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK0_ADD_FUSE(val)\ argument
7113 #define VXGE_HAL_RF_SQM_LPRPEDAT_RTL_TOP_0_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7115 #define VXGE_HAL_RF_SQM_LPRPEDAT_RTL_TOP_0_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7118 #define VXGE_HAL_RF_SQM_LPRPEDAT_RTL_TOP_1_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7120 #define VXGE_HAL_RF_SQM_LPRPEDAT_RTL_TOP_1_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7123 #define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_0_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7125 #define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_0_CMG1_NMB_IO_BANK1_FUSE(val)\ argument
7127 #define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_0_CMG1_NMB_IO_BANK1_ADD_FUSE(val)\ argument
7129 #define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_0_CMG1_NMB_IO_BANK0_FUSE(val)\ argument
7131 #define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_0_CMG1_NMB_IO_BANK0_ADD_FUSE(val)\ argument
7134 #define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_1_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7136 #define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_1_CMG1_NMB_IO_BANK1_FUSE(val)\ argument
7138 #define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_1_CMG1_NMB_IO_BANK1_ADD_FUSE(val)\ argument
7140 #define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_1_CMG1_NMB_IO_BANK0_FUSE(val)\ argument
7142 #define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_1_CMG1_NMB_IO_BANK0_ADD_FUSE(val)\ argument
7145 #define VXGE_HAL_RF_CQM_DMACQERSP_RTL_TOP_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7147 #define VXGE_HAL_RF_CQM_DMACQERSP_RTL_TOP_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7150 #define VXGE_HAL_RF_SQM_RPEREQDAT_RTL_TOP_0_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7152 #define VXGE_HAL_RF_SQM_RPEREQDAT_RTL_TOP_0_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7155 #define VXGE_HAL_RF_SQM_RPEREQDAT_RTL_TOP_1_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7157 #define VXGE_HAL_RF_SQM_RPEREQDAT_RTL_TOP_1_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7160 #define VXGE_HAL_RF_SSCC_SSR_RTL_TOP_0_0_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7162 #define VXGE_HAL_RF_SSCC_SSR_RTL_TOP_0_0_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7165 #define VXGE_HAL_RF_SSCC_SSR_RTL_TOP_1_0_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7167 #define VXGE_HAL_RF_SSCC_SSR_RTL_TOP_1_0_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7170 #define VXGE_HAL_RF_SSCC_SSR_RTL_TOP_0_1_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7172 #define VXGE_HAL_RF_SSCC_SSR_RTL_TOP_0_1_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7175 #define VXGE_HAL_RF_SSCC_SSR_RTL_TOP_1_1_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7177 #define VXGE_HAL_RF_SSCC_SSR_RTL_TOP_1_1_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7180 #define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_1_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7182 #define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_1_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7185 #define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_0_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7187 #define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_0_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7190 #define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_1_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7192 #define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_1_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7195 #define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_0_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7197 #define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_0_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7200 #define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_1_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7202 #define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_1_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7205 #define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_0_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7207 #define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_0_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7210 #define VXGE_HAL_RF_SSC_SSR_RESP_RTL_TOP_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7212 #define VXGE_HAL_RF_SSC_SSR_RESP_RTL_TOP_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7215 #define VXGE_HAL_RF_SSC_SSR_RESP_RTL_TOP_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7217 #define VXGE_HAL_RF_SSC_SSR_RESP_RTL_TOP_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7220 #define VXGE_HAL_RF_SSC_SSR_RESP_RTL_TOP_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7222 #define VXGE_HAL_RF_SSC_SSR_RESP_RTL_TOP_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7225 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_1_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7227 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_1_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7230 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_2_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7232 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_2_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7235 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_2_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7237 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_2_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7240 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_0_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7242 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_0_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7245 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_0_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7247 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_0_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7250 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_0_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7252 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_0_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7255 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_1_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7257 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_1_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7260 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_1_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7262 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_1_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7265 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_2_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7267 #define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_2_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7270 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_1_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7272 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_1_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7275 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_2_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7277 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_2_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7280 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_1_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7282 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_1_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7285 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_2_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7287 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_2_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7290 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_1_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7292 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_1_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7295 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_2_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7297 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_2_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7300 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_0_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7302 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_0_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7305 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_3_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7307 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_3_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7310 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_0_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7312 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_0_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7315 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_3_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7317 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_3_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7320 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_0_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7322 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_0_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7325 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_3_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7327 #define VXGE_HAL_RF_SSC_STATE_RTL_TOP_3_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7330 #define VXGE_HAL_RF_SSCC_TSR_RTL_TOP_0_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7332 #define VXGE_HAL_RF_SSCC_TSR_RTL_TOP_0_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7335 #define VXGE_HAL_RF_SSCC_TSR_RTL_TOP_1_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7337 #define VXGE_HAL_RF_SSCC_TSR_RTL_TOP_1_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7340 #define VXGE_HAL_RF_SSCC_TSR_RTL_TOP_2_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7342 #define VXGE_HAL_RF_SSCC_TSR_RTL_TOP_2_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7345 #define VXGE_HAL_RF_UQM_CMCREQ_RTL_TOP_CMG1_NMB_IO_REPAIR_STATUS(val)\ argument
7347 #define VXGE_HAL_RF_UQM_CMCREQ_RTL_TOP_CMG1_NMB_IO_ALL_FUSE(val)\ argument
7350 #define VXGE_HAL_RR0_G3IF_CM_CTRL_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7352 #define VXGE_HAL_RR0_G3IF_CM_CTRL_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7355 #define VXGE_HAL_RR1_G3IF_CM_CTRL_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7357 #define VXGE_HAL_RR1_G3IF_CM_CTRL_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7360 #define VXGE_HAL_RR2_G3IF_CM_CTRL_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7362 #define VXGE_HAL_RR2_G3IF_CM_CTRL_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7365 #define VXGE_HAL_RF_G3IF_CM_RD_RTL_TOP0_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7367 #define VXGE_HAL_RF_G3IF_CM_RD_RTL_TOP0_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7370 #define VXGE_HAL_RF_G3IF_CM_RD_RTL_TOP1_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7372 #define VXGE_HAL_RF_G3IF_CM_RD_RTL_TOP1_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7375 #define VXGE_HAL_RF_G3IF_CM_RD_RTL_TOP2_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7377 #define VXGE_HAL_RF_G3IF_CM_RD_RTL_TOP2_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7380 #define VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_0_0_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7382 #define VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_0_0_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7385 #define VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_1_0_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7387 #define VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_1_0_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7390 #define VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_0_1_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7392 #define VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_0_1_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7395 #define VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_1_1_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7397 #define VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_1_1_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7400 #define VXGE_HAL_RF_CP_DMA_RESP_RTL_TOP_0_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7402 #define VXGE_HAL_RF_CP_DMA_RESP_RTL_TOP_0_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7405 #define VXGE_HAL_RF_CP_DMA_RESP_RTL_TOP_1_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7407 #define VXGE_HAL_RF_CP_DMA_RESP_RTL_TOP_1_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7410 #define VXGE_HAL_RF_CP_DMA_RESP_RTL_TOP_2_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7412 #define VXGE_HAL_RF_CP_DMA_RESP_RTL_TOP_2_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7415 #define VXGE_HAL_RF_CP_QCC2CXP_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7417 #define VXGE_HAL_RF_CP_QCC2CXP_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7420 #define VXGE_HAL_RF_CP_STC2CP_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7422 #define VXGE_HAL_RF_CP_STC2CP_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7425 #define VXGE_HAL_RF_CP_XT_TRACE_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7427 #define VXGE_HAL_RF_CP_XT_TRACE_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7430 #define VXGE_HAL_RF_CP_XT_DTAG_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7432 #define VXGE_HAL_RF_CP_XT_DTAG_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7435 #define VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_0_0_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7437 #define VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_0_0_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7440 #define VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_1_0_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7442 #define VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_1_0_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7445 #define VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_0_1_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7447 #define VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_0_1_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7450 #define VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_1_1_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7452 #define VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_1_1_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7455 #define VXGE_HAL_RF_CP_XT_ITAG_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7457 #define VXGE_HAL_RF_CP_XT_ITAG_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7460 #define VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_0_0_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7462 #define VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_0_0_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7465 #define VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_1_0_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7467 #define VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_1_0_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7470 #define VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_0_1_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7472 #define VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_0_1_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7475 #define VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_1_1_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7477 #define VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_1_1_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7480 #define VXGE_HAL_RF_XTMC_BDT_MEM_RTL_TOP_0_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7482 #define VXGE_HAL_RF_XTMC_BDT_MEM_RTL_TOP_0_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7485 #define VXGE_HAL_RF_XTMC_BDT_MEM_RTL_TOP_1_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7487 #define VXGE_HAL_RF_XTMC_BDT_MEM_RTL_TOP_1_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7490 #define VXGE_HAL_RF_XT_PIF_SRAM_RTL_TOP_SRAM0_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7492 #define VXGE_HAL_RF_XT_PIF_SRAM_RTL_TOP_SRAM0_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7495 #define VXGE_HAL_RF_XT_PIF_SRAM_RTL_TOP_SRAM1_CMG2_NMB_IO_REPAIR_STATUS(val)\ argument
7497 #define VXGE_HAL_RF_XT_PIF_SRAM_RTL_TOP_SRAM1_CMG2_NMB_IO_ALL_FUSE(val)\ argument
7500 #define VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_0_0_CMG3_NMB_IO_REPAIR_STATUS(val)\ argument
7502 #define VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_0_0_CMG3_NMB_IO_ALL_FUSE(val)\ argument
7505 #define VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_1_0_CMG3_NMB_IO_REPAIR_STATUS(val)\ argument
7507 #define VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_1_0_CMG3_NMB_IO_ALL_FUSE(val)\ argument
7510 #define VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_0_1_CMG3_NMB_IO_REPAIR_STATUS(val)\ argument
7512 #define VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_0_1_CMG3_NMB_IO_ALL_FUSE(val)\ argument
7515 #define VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_1_1_CMG3_NMB_IO_REPAIR_STATUS(val)\ argument
7517 #define VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_1_1_CMG3_NMB_IO_ALL_FUSE(val)\ argument
7520 #define VXGE_HAL_RF_DAM_WRRESP_RTL_TOP_CMG3_NMB_IO_REPAIR_STATUS(val)\ argument
7522 #define VXGE_HAL_RF_DAM_WRRESP_RTL_TOP_CMG3_NMB_IO_ALL_FUSE(val)\ argument
7525 #define VXGE_HAL_RF_DAM_RDSB_FIFO_RTL_TOP_CMG3_NMB_IO_REPAIR_STATUS(val)\ argument
7527 #define VXGE_HAL_RF_DAM_RDSB_FIFO_RTL_TOP_CMG3_NMB_IO_ALL_FUSE(val)\ argument
7530 #define VXGE_HAL_RF_DAM_WRSB_FIFO_RTL_TOP_CMG3_NMB_IO_REPAIR_STATUS(val)\ argument
7532 #define VXGE_HAL_RF_DAM_WRSB_FIFO_RTL_TOP_CMG3_NMB_IO_ALL_FUSE(val)\ argument
7535 #define VXGE_HAL_RR_DBF_LADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ argument
7537 #define VXGE_HAL_RR_DBF_LADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_FUSE(val)\ argument
7539 #define VXGE_HAL_RR_DBF_LADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_ADD_FUSE(val)\ argument
7541 #define VXGE_HAL_RR_DBF_LADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_FUSE(val)\ argument
7543 #define VXGE_HAL_RR_DBF_LADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_ADD_FUSE(val)\ argument
7546 #define VXGE_HAL_RR_DBF_LADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ argument
7548 #define VXGE_HAL_RR_DBF_LADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_FUSE(val)\ argument
7550 #define VXGE_HAL_RR_DBF_LADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_ADD_FUSE(val)\ argument
7552 #define VXGE_HAL_RR_DBF_LADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_FUSE(val)\ argument
7554 #define VXGE_HAL_RR_DBF_LADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_ADD_FUSE(val)\ argument
7557 #define VXGE_HAL_RR_DBF_LADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ argument
7559 #define VXGE_HAL_RR_DBF_LADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_FUSE(val)\ argument
7561 #define VXGE_HAL_RR_DBF_LADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_ADD_FUSE(val)\ argument
7563 #define VXGE_HAL_RR_DBF_LADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_FUSE(val)\ argument
7565 #define VXGE_HAL_RR_DBF_LADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_ADD_FUSE(val)\ argument
7568 #define VXGE_HAL_RR_DBF_HADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ argument
7570 #define VXGE_HAL_RR_DBF_HADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_FUSE(val)\ argument
7572 #define VXGE_HAL_RR_DBF_HADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_ADD_FUSE(val)\ argument
7574 #define VXGE_HAL_RR_DBF_HADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_FUSE(val)\ argument
7576 #define VXGE_HAL_RR_DBF_HADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_ADD_FUSE(val)\ argument
7579 #define VXGE_HAL_RR_DBF_HADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ argument
7581 #define VXGE_HAL_RR_DBF_HADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_FUSE(val)\ argument
7583 #define VXGE_HAL_RR_DBF_HADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_ADD_FUSE(val)\ argument
7585 #define VXGE_HAL_RR_DBF_HADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_FUSE(val)\ argument
7587 #define VXGE_HAL_RR_DBF_HADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_ADD_FUSE(val)\ argument
7590 #define VXGE_HAL_RR_DBF_HADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ argument
7592 #define VXGE_HAL_RR_DBF_HADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_FUSE(val)\ argument
7594 #define VXGE_HAL_RR_DBF_HADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_ADD_FUSE(val)\ argument
7596 #define VXGE_HAL_RR_DBF_HADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_FUSE(val)\ argument
7598 #define VXGE_HAL_RR_DBF_HADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_ADD_FUSE(val)\ argument
7601 #define VXGE_HAL_RF_USDC_0_FIFO_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ argument
7603 #define VXGE_HAL_RF_USDC_0_FIFO_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\ argument
7606 #define VXGE_HAL_RF_USDC_1_FIFO_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ argument
7608 #define VXGE_HAL_RF_USDC_1_FIFO_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\ argument
7611 #define VXGE_HAL_RF_USDC_0_WA_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ argument
7613 #define VXGE_HAL_RF_USDC_0_WA_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\ argument
7616 #define VXGE_HAL_RF_USDC_1_WA_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ argument
7618 #define VXGE_HAL_RF_USDC_1_WA_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\ argument
7621 #define VXGE_HAL_RF_USDC_0_SA_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ argument
7623 #define VXGE_HAL_RF_USDC_0_SA_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\ argument
7626 #define VXGE_HAL_RF_USDC_1_SA_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ argument
7628 #define VXGE_HAL_RF_USDC_1_SA_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\ argument
7631 #define VXGE_HAL_RF_USDC_0_CA_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ argument
7633 #define VXGE_HAL_RF_USDC_0_CA_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\ argument
7636 #define VXGE_HAL_RF_USDC_1_CA_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ argument
7638 #define VXGE_HAL_RF_USDC_1_CA_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\ argument
7641 #define VXGE_HAL_RF_G3IF_FB_RD1_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7643 #define VXGE_HAL_RF_G3IF_FB_RD1_FBIF_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8) argument
7645 #define VXGE_HAL_RF_G3IF_FB_RD2_FBIF_NMB_IO_REPAIR_STATUS(val) vBIT(val, 0, 2) argument
7646 #define VXGE_HAL_RF_G3IF_FB_RD2_FBIF_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8) argument
7648 #define VXGE_HAL_RF_G3IF_FB_CTRL_RTL_TOP1_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7650 #define VXGE_HAL_RF_G3IF_FB_CTRL_RTL_TOP1_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7653 #define VXGE_HAL_RF_G3IF_FB_CTRL_RTL_TOP_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7655 #define VXGE_HAL_RF_G3IF_FB_CTRL_RTL_TOP_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7658 #define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_0_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7660 #define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_0_FBIF_NMB_IO_BANK1_FUSE(val)\ argument
7662 #define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_0_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\ argument
7664 #define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_0_FBIF_NMB_IO_BANK0_FUSE(val)\ argument
7666 #define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_0_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\ argument
7669 #define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_1_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7671 #define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_1_FBIF_NMB_IO_BANK1_FUSE(val)\ argument
7673 #define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_1_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\ argument
7675 #define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_1_FBIF_NMB_IO_BANK0_FUSE(val)\ argument
7677 #define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_1_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\ argument
7680 #define VXGE_HAL_RR_FAU_XFMD_INS_RTL_TOP_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7682 #define VXGE_HAL_RR_FAU_XFMD_INS_RTL_TOP_FBIF_NMB_IO_BANK1_FUSE(val)\ argument
7684 #define VXGE_HAL_RR_FAU_XFMD_INS_RTL_TOP_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\ argument
7686 #define VXGE_HAL_RR_FAU_XFMD_INS_RTL_TOP_FBIF_NMB_IO_BANK0_FUSE(val)\ argument
7688 #define VXGE_HAL_RR_FAU_XFMD_INS_RTL_TOP_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\ argument
7691 #define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_A1_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7693 #define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_A1_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7696 #define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_A2_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7698 #define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_A2_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7701 #define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_A3_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7703 #define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_A3_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7706 #define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_B1_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7708 #define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_B1_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7711 #define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_B2_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7713 #define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_B2_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7716 #define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_B3_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7718 #define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_B3_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7721 #define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT0_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7723 #define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK1_FUSE(val)\ argument
7725 #define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\ argument
7727 #define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK0_FUSE(val)\ argument
7729 #define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\ argument
7732 #define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT1_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7734 #define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK1_FUSE(val)\ argument
7736 #define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\ argument
7738 #define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK0_FUSE(val)\ argument
7740 #define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\ argument
7743 #define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT0_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7745 #define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK1_FUSE(val)\ argument
7747 #define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\ argument
7749 #define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK0_FUSE(val)\ argument
7751 #define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\ argument
7754 #define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT1_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7756 #define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK1_FUSE(val)\ argument
7758 #define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\ argument
7760 #define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK0_FUSE(val)\ argument
7762 #define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\ argument
7765 #define VXGE_HAL_RR_FAU_MAC2F_W_L_RTL_TOP_PORT2_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7767 #define VXGE_HAL_RR_FAU_MAC2F_W_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK1_FUSE(val)\ argument
7769 #define VXGE_HAL_RR_FAU_MAC2F_W_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\ argument
7771 #define VXGE_HAL_RR_FAU_MAC2F_W_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK0_FUSE(val)\ argument
7773 #define VXGE_HAL_RR_FAU_MAC2F_W_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\ argument
7776 #define VXGE_HAL_RR_FAU_MAC2F_N_L_RTL_TOP_PORT2_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7778 #define VXGE_HAL_RR_FAU_MAC2F_N_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK1_FUSE(val)\ argument
7780 #define VXGE_HAL_RR_FAU_MAC2F_N_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\ argument
7782 #define VXGE_HAL_RR_FAU_MAC2F_N_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK0_FUSE(val)\ argument
7784 #define VXGE_HAL_RR_FAU_MAC2F_N_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\ argument
7787 #define VXGE_HAL_RF_ORP_FRM_FIFO_RTL_TOP_0_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7789 #define VXGE_HAL_RF_ORP_FRM_FIFO_RTL_TOP_0_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7792 #define VXGE_HAL_RF_ORP_FRM_FIFO_RTL_TOP_1_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7794 #define VXGE_HAL_RF_ORP_FRM_FIFO_RTL_TOP_1_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7797 #define VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_0_0_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7799 #define VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_0_0_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7802 #define VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_1_0_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7804 #define VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_1_0_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7807 #define VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_0_1_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7809 #define VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_0_1_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7812 #define VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_1_1_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7814 #define VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_1_1_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7817 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_0_0_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7819 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_0_0_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7822 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_1_0_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7824 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_1_0_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7827 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_2_0_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7829 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_2_0_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7832 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_0_1_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7834 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_0_1_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7837 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_1_1_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7839 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_1_1_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7842 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_2_1_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7844 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_2_1_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7847 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_0_2_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7849 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_0_2_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7852 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_1_2_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7854 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_1_2_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7857 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_2_2_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7859 #define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_2_2_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7862 #define VXGE_HAL_RF_TMAC_TPA2M_DA_RTL_TOP_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7864 #define VXGE_HAL_RF_TMAC_TPA2M_DA_RTL_TOP_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7867 #define VXGE_HAL_RF_TMAC_TPA2M_SB_RTL_TOP_FBIF_NMB_IO_REPAIR_STATUS(val)\ argument
7869 #define VXGE_HAL_RF_TMAC_TPA2M_SB_RTL_TOP_FBIF_NMB_IO_ALL_FUSE(val)\ argument
7872 #define VXGE_HAL_RF_XT_TRACE_RTL_TOP_MP_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7874 #define VXGE_HAL_RF_XT_TRACE_RTL_TOP_MP_MSG_NMB_IO_ALL_FUSE(val)\ argument
7877 #define VXGE_HAL_RF_MP_XT_DTAG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7879 #define VXGE_HAL_RF_MP_XT_DTAG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6) argument
7881 #define VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_0_0_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7883 #define VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_0_0_MSG_NMB_IO_ALL_FUSE(val)\ argument
7886 #define VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_1_0_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7888 #define VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_1_0_MSG_NMB_IO_ALL_FUSE(val)\ argument
7891 #define VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_0_1_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7893 #define VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_0_1_MSG_NMB_IO_ALL_FUSE(val)\ argument
7896 #define VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_1_1_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7898 #define VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_1_1_MSG_NMB_IO_ALL_FUSE(val)\ argument
7901 #define VXGE_HAL_RF_MP_XT_ITAG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7903 #define VXGE_HAL_RF_MP_XT_ITAG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6) argument
7905 #define VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_0_0_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7907 #define VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_0_0_MSG_NMB_IO_ALL_FUSE(val)\ argument
7910 #define VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_1_0_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7912 #define VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_1_0_MSG_NMB_IO_ALL_FUSE(val)\ argument
7915 #define VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_0_1_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7917 #define VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_0_1_MSG_NMB_IO_ALL_FUSE(val)\ argument
7920 #define VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_1_1_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7922 #define VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_1_1_MSG_NMB_IO_ALL_FUSE(val)\ argument
7925 #define VXGE_HAL_RF_MSG_BWR_PF_RTL_TOP_0_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7927 #define VXGE_HAL_RF_MSG_BWR_PF_RTL_TOP_0_MSG_NMB_IO_ALL_FUSE(val)\ argument
7930 #define VXGE_HAL_RF_MSG_BWR_PF_RTL_TOP_1_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7932 #define VXGE_HAL_RF_MSG_BWR_PF_RTL_TOP_1_MSG_NMB_IO_ALL_FUSE(val)\ argument
7935 #define VXGE_HAL_RF_MSG_UMQ_RTL_TOP_0_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7937 #define VXGE_HAL_RF_MSG_UMQ_RTL_TOP_0_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 7) argument
7939 #define VXGE_HAL_RF_MSG_UMQ_RTL_TOP_1_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7941 #define VXGE_HAL_RF_MSG_UMQ_RTL_TOP_1_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 7) argument
7943 #define VXGE_HAL_RF_MSG_DMQ_RTL_TOP_0_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7945 #define VXGE_HAL_RF_MSG_DMQ_RTL_TOP_0_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6) argument
7947 #define VXGE_HAL_RF_MSG_DMQ_RTL_TOP_1_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7949 #define VXGE_HAL_RF_MSG_DMQ_RTL_TOP_1_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6) argument
7951 #define VXGE_HAL_RF_MSG_DMQ_RTL_TOP_2_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7953 #define VXGE_HAL_RF_MSG_DMQ_RTL_TOP_2_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6) argument
7955 #define VXGE_HAL_RF_MSG_DMA_RESP_RTL_TOP_0_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7957 #define VXGE_HAL_RF_MSG_DMA_RESP_RTL_TOP_0_MSG_NMB_IO_ALL_FUSE(val)\ argument
7960 #define VXGE_HAL_RF_MSG_DMA_RESP_RTL_TOP_1_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7962 #define VXGE_HAL_RF_MSG_DMA_RESP_RTL_TOP_1_MSG_NMB_IO_ALL_FUSE(val)\ argument
7965 #define VXGE_HAL_RF_MSG_DMA_RESP_RTL_TOP_2_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7967 #define VXGE_HAL_RF_MSG_DMA_RESP_RTL_TOP_2_MSG_NMB_IO_ALL_FUSE(val)\ argument
7970 #define VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_0_0_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7972 #define VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_0_0_MSG_NMB_IO_ALL_FUSE(val)\ argument
7975 #define VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_1_0_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7977 #define VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_1_0_MSG_NMB_IO_ALL_FUSE(val)\ argument
7980 #define VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_0_1_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7982 #define VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_0_1_MSG_NMB_IO_ALL_FUSE(val)\ argument
7985 #define VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_1_1_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7987 #define VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_1_1_MSG_NMB_IO_ALL_FUSE(val)\ argument
7990 #define VXGE_HAL_RF_MSG_TXPE2MSG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7992 #define VXGE_HAL_RF_MSG_TXPE2MSG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val)\ argument
7995 #define VXGE_HAL_RF_MSG_RXPE2MSG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
7997 #define VXGE_HAL_RF_MSG_RXPE2MSG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val)\ argument
8000 #define VXGE_HAL_RF_MSG_RPE2MSG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8002 #define VXGE_HAL_RF_MSG_RPE2MSG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val)\ argument
8005 #define VXGE_HAL_RR_TIM_BMAP_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8007 #define VXGE_HAL_RR_TIM_BMAP_RTL_TOP_MSG_NMB_IO_BANK1_FUSE(val) vBIT(val, 2, 8) argument
8008 #define VXGE_HAL_RR_TIM_BMAP_RTL_TOP_MSG_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8010 #define VXGE_HAL_RR_TIM_BMAP_RTL_TOP_MSG_NMB_IO_BANK0_FUSE(val) vBIT(val, 12, 8) argument
8011 #define VXGE_HAL_RR_TIM_BMAP_RTL_TOP_MSG_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8014 #define VXGE_HAL_RF_TIM_VBLS_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8016 #define VXGE_HAL_RF_TIM_VBLS_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8) argument
8018 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_0_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8020 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_0_MSG_NMB_IO_ALL_FUSE(val)\ argument
8023 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_0_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8025 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_0_MSG_NMB_IO_ALL_FUSE(val)\ argument
8028 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_0_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8030 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_0_MSG_NMB_IO_ALL_FUSE(val)\ argument
8033 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_1_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8035 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_1_MSG_NMB_IO_ALL_FUSE(val)\ argument
8038 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_1_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8040 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_1_MSG_NMB_IO_ALL_FUSE(val)\ argument
8043 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_1_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8045 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_1_MSG_NMB_IO_ALL_FUSE(val)\ argument
8048 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_2_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8050 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_2_MSG_NMB_IO_ALL_FUSE(val)\ argument
8053 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_2_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8055 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_2_MSG_NMB_IO_ALL_FUSE(val)\ argument
8058 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_2_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8060 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_2_MSG_NMB_IO_ALL_FUSE(val)\ argument
8063 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_3_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8065 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_3_MSG_NMB_IO_ALL_FUSE(val)\ argument
8068 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_3_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8070 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_3_MSG_NMB_IO_ALL_FUSE(val)\ argument
8073 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_3_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8075 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_3_MSG_NMB_IO_ALL_FUSE(val)\ argument
8078 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_4_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8080 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_4_MSG_NMB_IO_ALL_FUSE(val)\ argument
8083 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_4_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8085 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_4_MSG_NMB_IO_ALL_FUSE(val)\ argument
8088 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_4_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8090 #define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_4_MSG_NMB_IO_ALL_FUSE(val)\ argument
8093 #define VXGE_HAL_RF_XT_TRACE_RTL_TOP_UP_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8095 #define VXGE_HAL_RF_XT_TRACE_RTL_TOP_UP_MSG_NMB_IO_ALL_FUSE(val)\ argument
8098 #define VXGE_HAL_RF_UP_XT_DTAG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8100 #define VXGE_HAL_RF_UP_XT_DTAG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6) argument
8102 #define VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_0_0_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8104 #define VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_0_0_MSG_NMB_IO_ALL_FUSE(val)\ argument
8107 #define VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_1_0_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8109 #define VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_1_0_MSG_NMB_IO_ALL_FUSE(val)\ argument
8112 #define VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_0_1_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8114 #define VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_0_1_MSG_NMB_IO_ALL_FUSE(val)\ argument
8117 #define VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_1_1_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8119 #define VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_1_1_MSG_NMB_IO_ALL_FUSE(val)\ argument
8122 #define VXGE_HAL_RF_UP_XT_ITAG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8124 #define VXGE_HAL_RF_UP_XT_ITAG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6) argument
8126 #define VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_0_0_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8128 #define VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_0_0_MSG_NMB_IO_ALL_FUSE(val)\ argument
8131 #define VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_1_0_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8133 #define VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_1_0_MSG_NMB_IO_ALL_FUSE(val)\ argument
8136 #define VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_0_1_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8138 #define VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_0_1_MSG_NMB_IO_ALL_FUSE(val)\ argument
8141 #define VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_1_1_MSG_NMB_IO_REPAIR_STATUS(val)\ argument
8143 #define VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_1_1_MSG_NMB_IO_ALL_FUSE(val)\ argument
8146 #define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\ argument
8148 #define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK1_FUSE(val)\ argument
8150 #define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8152 #define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK0_FUSE(val)\ argument
8154 #define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8157 #define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\ argument
8159 #define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK1_FUSE(val)\ argument
8161 #define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8163 #define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK0_FUSE(val)\ argument
8165 #define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8168 #define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\ argument
8170 #define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_0_ONE_NMB_IO_BANK1_FUSE(val)\ argument
8172 #define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_0_ONE_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8174 #define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_0_ONE_NMB_IO_BANK0_FUSE(val)\ argument
8176 #define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_0_ONE_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8179 #define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\ argument
8181 #define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_1_ONE_NMB_IO_BANK1_FUSE(val)\ argument
8183 #define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_1_ONE_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8185 #define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_1_ONE_NMB_IO_BANK0_FUSE(val)\ argument
8187 #define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_1_ONE_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8190 #define VXGE_HAL_RF_RXPE_MSG2RXPE_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\ argument
8192 #define VXGE_HAL_RF_RXPE_MSG2RXPE_RTL_TOP_0_ONE_NMB_IO_ALL_FUSE(val)\ argument
8195 #define VXGE_HAL_RF_RXPE_MSG2RXPE_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\ argument
8197 #define VXGE_HAL_RF_RXPE_MSG2RXPE_RTL_TOP_1_ONE_NMB_IO_ALL_FUSE(val)\ argument
8200 #define VXGE_HAL_RF_RXPE_XT0_FRM_RTL_TOP_ONE_NMB_IO_REPAIR_STATUS(val)\ argument
8202 #define VXGE_HAL_RF_RXPE_XT0_FRM_RTL_TOP_ONE_NMB_IO_ALL_FUSE(val)\ argument
8205 #define VXGE_HAL_RF_RPE_PDM_RCMD_RTL_TOP_ONE_NMB_IO_REPAIR_STATUS(val)\ argument
8207 #define VXGE_HAL_RF_RPE_PDM_RCMD_RTL_TOP_ONE_NMB_IO_ALL_FUSE(val)\ argument
8210 #define VXGE_HAL_RF_RPE_RCQ_RTL_TOP_ONE_NMB_IO_REPAIR_STATUS(val)\ argument
8212 #define VXGE_HAL_RF_RPE_RCQ_RTL_TOP_ONE_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8) argument
8214 #define VXGE_HAL_RF_RPE_RCO_PBLE_RTL_TOP_ONE_NMB_IO_REPAIR_STATUS(val)\ argument
8216 #define VXGE_HAL_RF_RPE_RCO_PBLE_RTL_TOP_ONE_NMB_IO_ALL_FUSE(val)\ argument
8219 #define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\ argument
8221 #define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK1_FUSE(val)\ argument
8223 #define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8225 #define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK0_FUSE(val)\ argument
8227 #define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8230 #define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\ argument
8232 #define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK1_FUSE(val)\ argument
8234 #define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8236 #define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK0_FUSE(val)\ argument
8238 #define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8241 #define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\ argument
8243 #define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_0_ONE_NMB_IO_BANK1_FUSE(val)\ argument
8245 #define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_0_ONE_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8247 #define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_0_ONE_NMB_IO_BANK0_FUSE(val)\ argument
8249 #define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_0_ONE_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8252 #define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\ argument
8254 #define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_1_ONE_NMB_IO_BANK1_FUSE(val)\ argument
8256 #define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_1_ONE_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8258 #define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_1_ONE_NMB_IO_BANK0_FUSE(val)\ argument
8260 #define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_1_ONE_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8263 #define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\ argument
8265 #define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_0_ONE_NMB_IO_BANK1_FUSE(val)\ argument
8267 #define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_0_ONE_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8269 #define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_0_ONE_NMB_IO_BANK0_FUSE(val)\ argument
8271 #define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_0_ONE_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8274 #define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\ argument
8276 #define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_1_ONE_NMB_IO_BANK1_FUSE(val)\ argument
8278 #define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_1_ONE_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8280 #define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_1_ONE_NMB_IO_BANK0_FUSE(val)\ argument
8282 #define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_1_ONE_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8285 #define VXGE_HAL_RF_PE_DLM_LWRQ_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\ argument
8287 #define VXGE_HAL_RF_PE_DLM_LWRQ_RTL_TOP_0_ONE_NMB_IO_ALL_FUSE(val)\ argument
8290 #define VXGE_HAL_RF_PE_DLM_LWRQ_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\ argument
8292 #define VXGE_HAL_RF_PE_DLM_LWRQ_RTL_TOP_1_ONE_NMB_IO_ALL_FUSE(val)\ argument
8295 #define VXGE_HAL_RF_TXPE_MSG2TXPE_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\ argument
8297 #define VXGE_HAL_RF_TXPE_MSG2TXPE_RTL_TOP_0_ONE_NMB_IO_ALL_FUSE(val)\ argument
8300 #define VXGE_HAL_RF_TXPE_MSG2TXPE_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\ argument
8302 #define VXGE_HAL_RF_TXPE_MSG2TXPE_RTL_TOP_1_ONE_NMB_IO_ALL_FUSE(val)\ argument
8305 #define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_0_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8307 #define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_0_PCI_NMB_IO_ALL_FUSE(val)\ argument
8310 #define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_1_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8312 #define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_1_PCI_NMB_IO_ALL_FUSE(val)\ argument
8315 #define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_2_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8317 #define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_2_PCI_NMB_IO_ALL_FUSE(val)\ argument
8320 #define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_3_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8322 #define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_3_PCI_NMB_IO_ALL_FUSE(val)\ argument
8325 #define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_4_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8327 #define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_4_PCI_NMB_IO_ALL_FUSE(val)\ argument
8330 #define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_5_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8332 #define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_5_PCI_NMB_IO_ALL_FUSE(val)\ argument
8335 #define VXGE_HAL_RF_PCI_SOT_BUF_RTL_TOP_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8337 #define VXGE_HAL_RF_PCI_SOT_BUF_RTL_TOP_PCI_NMB_IO_ALL_FUSE(val)\ argument
8340 #define VXGE_HAL_RF_PCI_RX_PH_RTL_TOP_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8342 #define VXGE_HAL_RF_PCI_RX_PH_RTL_TOP_PCI_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8) argument
8344 #define VXGE_HAL_RF_PCI_RX_NPH_RTL_TOP_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8346 #define VXGE_HAL_RF_PCI_RX_NPH_RTL_TOP_PCI_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8) argument
8348 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_0_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8350 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_0_PCI_NMB_IO_ALL_FUSE(val)\ argument
8353 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_1_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8355 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_1_PCI_NMB_IO_ALL_FUSE(val)\ argument
8358 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_2_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8360 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_2_PCI_NMB_IO_ALL_FUSE(val)\ argument
8363 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_3_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8365 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_3_PCI_NMB_IO_ALL_FUSE(val)\ argument
8368 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_4_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8370 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_4_PCI_NMB_IO_ALL_FUSE(val)\ argument
8373 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_5_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8375 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_5_PCI_NMB_IO_ALL_FUSE(val)\ argument
8378 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_6_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8380 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_6_PCI_NMB_IO_ALL_FUSE(val)\ argument
8383 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_7_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8385 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_7_PCI_NMB_IO_ALL_FUSE(val)\ argument
8388 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_8_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8390 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_8_PCI_NMB_IO_ALL_FUSE(val)\ argument
8393 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_9_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8395 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_9_PCI_NMB_IO_ALL_FUSE(val)\ argument
8398 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_10_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8400 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_10_PCI_NMB_IO_ALL_FUSE(val)\ argument
8403 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_11_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8405 #define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_11_PCI_NMB_IO_ALL_FUSE(val)\ argument
8408 #define VXGE_HAL_RF_PCI_RX_NPD_RTL_TOP_0_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8410 #define VXGE_HAL_RF_PCI_RX_NPD_RTL_TOP_0_PCI_NMB_IO_ALL_FUSE(val)\ argument
8413 #define VXGE_HAL_RF_PCI_RX_NPD_RTL_TOP_1_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8415 #define VXGE_HAL_RF_PCI_RX_NPD_RTL_TOP_1_PCI_NMB_IO_ALL_FUSE(val)\ argument
8418 #define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_0_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8420 #define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_0_PCI_NMB_IO_ALL_FUSE(val)\ argument
8423 #define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_1_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8425 #define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_1_PCI_NMB_IO_ALL_FUSE(val)\ argument
8428 #define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_2_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8430 #define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_2_PCI_NMB_IO_ALL_FUSE(val)\ argument
8433 #define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_3_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8435 #define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_3_PCI_NMB_IO_ALL_FUSE(val)\ argument
8438 #define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_4_PCI_NMB_IO_REPAIR_STATUS(val)\ argument
8440 #define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_4_PCI_NMB_IO_ALL_FUSE(val)\ argument
8443 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC0_RTDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8445 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC0_RTDMA_NMB_IO_ALL_FUSE(val)\ argument
8448 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC1_RTDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8450 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC1_RTDMA_NMB_IO_ALL_FUSE(val)\ argument
8453 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC2_RTDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8455 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC2_RTDMA_NMB_IO_ALL_FUSE(val)\ argument
8458 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC3_RTDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8460 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC3_RTDMA_NMB_IO_ALL_FUSE(val)\ argument
8463 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC4_RTDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8465 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC4_RTDMA_NMB_IO_ALL_FUSE(val)\ argument
8468 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC5_RTDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8470 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC5_RTDMA_NMB_IO_ALL_FUSE(val)\ argument
8473 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC6_RTDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8475 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC6_RTDMA_NMB_IO_ALL_FUSE(val)\ argument
8478 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC7_RTDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8480 #define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC7_RTDMA_NMB_IO_ALL_FUSE(val)\ argument
8483 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC1_RTDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8485 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC1_RTDMA_NMB_IO_BANK1_FUSE(val)\ argument
8487 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC1_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8489 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC1_RTDMA_NMB_IO_BANK0_FUSE(val)\ argument
8491 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC1_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8494 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC3_RTDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8496 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC3_RTDMA_NMB_IO_BANK1_FUSE(val)\ argument
8498 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC3_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8500 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC3_RTDMA_NMB_IO_BANK0_FUSE(val)\ argument
8502 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC3_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8505 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC5_RTDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8507 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC5_RTDMA_NMB_IO_BANK1_FUSE(val)\ argument
8509 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC5_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8511 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC5_RTDMA_NMB_IO_BANK0_FUSE(val)\ argument
8513 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC5_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8516 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC7_RTDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8518 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC7_RTDMA_NMB_IO_BANK1_FUSE(val)\ argument
8520 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC7_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8522 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC7_RTDMA_NMB_IO_BANK0_FUSE(val)\ argument
8524 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC7_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8527 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC0_RTDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8529 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC0_RTDMA_NMB_IO_BANK1_FUSE(val)\ argument
8531 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC0_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8533 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC0_RTDMA_NMB_IO_BANK0_FUSE(val)\ argument
8535 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC0_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8538 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC2_RTDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8540 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC2_RTDMA_NMB_IO_BANK1_FUSE(val)\ argument
8542 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC2_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8544 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC2_RTDMA_NMB_IO_BANK0_FUSE(val)\ argument
8546 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC2_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8549 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC6_RTDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8551 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC6_RTDMA_NMB_IO_BANK1_FUSE(val)\ argument
8553 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC6_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8555 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC6_RTDMA_NMB_IO_BANK0_FUSE(val)\ argument
8557 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC6_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8560 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC4_RTDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8562 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC4_RTDMA_NMB_IO_BANK1_FUSE(val)\ argument
8564 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC4_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8566 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC4_RTDMA_NMB_IO_BANK0_FUSE(val)\ argument
8568 #define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC4_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8571 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_0_W0_WRDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8573 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_0_W0_WRDMA_NMB_IO_ALL_FUSE(val)\ argument
8576 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_1_W0_WRDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8578 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_1_W0_WRDMA_NMB_IO_ALL_FUSE(val)\ argument
8581 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_2_W0_WRDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8583 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_2_WRAPPER0_WRDMA_NMB_IO_ALL_FUSE(val)\ argument
8586 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_0_W1_WRDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8588 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_0_W1_WRDMA_NMB_IO_ALL_FUSE(val)\ argument
8591 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_1_W1_WRDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8593 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_1_W1_WRDMA_NMB_IO_ALL_FUSE(val)\ argument
8596 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_2_W1_WRDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8598 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_2_W1_WRDMA_NMB_IO_ALL_FUSE(val)\ argument
8601 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_0_W2_WRDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8603 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_0_WRAPPER2_WRDMA_NMB_IO_ALL_FUSE(val)\ argument
8606 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_1_W2_WRDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8608 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_1_W2_WRDMA_NMB_IO_ALL_FUSE(val)\ argument
8611 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_2_W2_WRDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8613 #define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_2_W2_WRDMA_NMB_IO_ALL_FUSE(val)\ argument
8616 #define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD0_WRDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8618 #define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD0_WRDMA_NMB_IO_BANK1_FUSE(val)\ argument
8620 #define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD0_WRDMA_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8622 #define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD0_WRDMA_NMB_IO_BANK0_FUSE(val)\ argument
8624 #define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD0_WRDMA_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8627 #define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD1_WRDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8629 #define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD1_WRDMA_NMB_IO_BANK1_FUSE(val)\ argument
8631 #define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD1_WRDMA_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8633 #define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD1_WRDMA_NMB_IO_BANK0_FUSE(val)\ argument
8635 #define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD1_WRDMA_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8638 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_0_WRDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8640 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_0_WRDMA_NMB_IO_ALL_FUSE(val)\ argument
8643 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_1_WRDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8645 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_1_WRDMA_NMB_IO_ALL_FUSE(val)\ argument
8648 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_2_WRDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8650 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_2_WRDMA_NMB_IO_ALL_FUSE(val)\ argument
8653 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_3_WRDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8655 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_3_WRDMA_NMB_IO_ALL_FUSE(val)\ argument
8658 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_4_WRDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8660 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_4_WRDMA_NMB_IO_ALL_FUSE(val)\ argument
8663 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_5_WRDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8665 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_5_WRDMA_NMB_IO_ALL_FUSE(val)\ argument
8668 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_6_WRDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8670 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_6_WRDMA_NMB_IO_ALL_FUSE(val)\ argument
8673 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_7_WRDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8675 #define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_7_WRDMA_NMB_IO_ALL_FUSE(val)\ argument
8678 #define VXGE_HAL_RF_ROCRC_IMMDBUF_RTL_TOP_WRDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8680 #define VXGE_HAL_RF_ROCRC_IMMDBUF_RTL_TOP_WRDMA_NMB_IO_ALL_FUSE(val)\ argument
8683 #define VXGE_HAL_RF_ROCRC_QCC_BYP_RTL_TOP_0_WRDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8685 #define VXGE_HAL_RF_ROCRC_QCC_BYP_RTL_TOP_0_WRDMA_NMB_IO_ALL_FUSE(val)\ argument
8688 #define VXGE_HAL_RF_ROCRC_QCC_BYP_RTL_TOP_1_WRDMA_NMB_IO_REPAIR_STATUS(val)\ argument
8690 #define VXGE_HAL_RF_ROCRC_QCC_BYP_RTL_TOP_1_WRDMA_NMB_IO_ALL_FUSE(val)\ argument
8693 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_0_XGMAC_NMB_IO_REPAIR_STATUS(val)\ argument
8695 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_0_XGMAC_NMB_IO_BANK1_FUSE(val)\ argument
8697 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_0_XGMAC_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8699 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_0_XGMAC_NMB_IO_BANK0_FUSE(val)\ argument
8701 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_0_XGMAC_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8704 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_1_XGMAC_NMB_IO_REPAIR_STATUS(val)\ argument
8706 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_1_XGMAC_NMB_IO_BANK1_FUSE(val)\ argument
8708 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_1_XGMAC_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8710 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_1_XGMAC_NMB_IO_BANK0_FUSE(val)\ argument
8712 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_1_XGMAC_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8715 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_2_XGMAC_NMB_IO_REPAIR_STATUS(val)\ argument
8717 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_2_XGMAC_NMB_IO_BANK1_FUSE(val)\ argument
8719 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_2_XGMAC_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8721 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_2_XGMAC_NMB_IO_BANK0_FUSE(val)\ argument
8723 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_2_XGMAC_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8726 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_3_XGMAC_NMB_IO_REPAIR_STATUS(val)\ argument
8728 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_3_XGMAC_NMB_IO_BANK1_FUSE(val)\ argument
8730 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_3_XGMAC_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8732 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_3_XGMAC_NMB_IO_BANK0_FUSE(val)\ argument
8734 #define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_3_XGMAC_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8737 #define VXGE_HAL_RR_RMAC_PN_LKP_D_RTL_TOP_XGMAC_NMB_IO_REPAIR_STATUS(val)\ argument
8739 #define VXGE_HAL_RR_RMAC_PN_LKP_D_RTL_TOP_XGMAC_NMB_IO_BANK1_FUSE(val)\ argument
8741 #define VXGE_HAL_RR_RMAC_PN_LKP_D_RTL_TOP_XGMAC_NMB_IO_BANK1_ADD_FUSE(val)\ argument
8743 #define VXGE_HAL_RR_RMAC_PN_LKP_D_RTL_TOP_XGMAC_NMB_IO_BANK0_FUSE(val)\ argument
8745 #define VXGE_HAL_RR_RMAC_PN_LKP_D_RTL_TOP_XGMAC_NMB_IO_BANK0_ADD_FUSE(val)\ argument
8748 #define VXGE_HAL_RF_RMAC_PN_LKP_S_RTL_TOP_0_XGMAC_NMB_IO_REPAIR_STATUS(val)\ argument
8750 #define VXGE_HAL_RF_RMAC_PN_LKP_S_RTL_TOP_0_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8753 #define VXGE_HAL_RF_RMAC_PN_LKP_S_RTL_TOP_1_XGMAC_NMB_IO_REPAIR_STATUS(val)\ argument
8755 #define VXGE_HAL_RF_RMAC_PN_LKP_S_RTL_TOP_1_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8758 #define VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_0_0_XGMAC_NMB_IO_REPAIR_STATUS(val)\ argument
8760 #define VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_0_0_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8763 #define VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_1_0_XGMAC_NMB_IO_REPAIR_STATUS(val)\ argument
8765 #define VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_1_0_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8768 #define VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_0_1_XGMAC_NMB_IO_REPAIR_STATUS(val)\ argument
8770 #define VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_0_1_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8773 #define VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_1_1_XGMAC_NMB_IO_REPAIR_STATUS(val)\ argument
8775 #define VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_1_1_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8778 #define VXGE_HAL_RF_RMAC_DS_LKP_RTL_TOP_XGMAC_NMB_IO_REPAIR_STATUS(val)\ argument
8780 #define VXGE_HAL_RF_RMAC_DS_LKP_RTL_TOP_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8783 #define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_0_RMAC0_XGMAC_NMB_IO_REP_STATUS(val)\ argument
8785 #define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_0_RMAC0_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8788 #define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_1_RMAC0_XGMAC_NMB_IO_REP_STATUS(val)\ argument
8790 #define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_1_RMAC0_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8793 #define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_0_RMAC1_XGMAC_NMB_IO_REP_STATUS(val)\ argument
8795 #define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_0_RMAC1_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8798 #define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_1_RMAC1_XGMAC_NMB_IO_REP_STATUS(val)\ argument
8800 #define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_1_RMAC1_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8803 #define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_0_RMAC2_XGMAC_NMB_IO_REP_STATUS(val)\ argument
8805 #define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_0_RMAC2_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8808 #define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_1_RMAC2_XGMAC_NMB_IO_REP_STATUS(val)\ argument
8810 #define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_1_RMAC2_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8813 #define VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_0_XGMAC_NMB_IO_REPAIR_STATUS(val)\ argument
8815 #define VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_0_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8818 #define VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_1_XGMAC_NMB_IO_REPAIR_STATUS(val)\ argument
8820 #define VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_1_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8823 #define VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_2_XGMAC_NMB_IO_REPAIR_STATUS(val)\ argument
8825 #define VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_2_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8828 #define VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_3_XGMAC_NMB_IO_REPAIR_STATUS(val)\ argument
8830 #define VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_3_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8833 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_0_XGMAC_NMB_IO_REPAIR_STATUS(val)\ argument
8835 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_0_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8838 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_1_XGMAC_NMB_IO_REPAIR_STATUS(val)\ argument
8840 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_1_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8843 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_2_XGMAC_NMB_IO_REPAIR_STATUS(val)\ argument
8845 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_2_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8848 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_3_XGMAC_NMB_IO_REPAIR_STATUS(val)\ argument
8850 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_3_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8853 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_4_XGMAC_NMB_IO_REPAIR_STATUS(val)\ argument
8855 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_4_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8858 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_5_XGMAC_NMB_IO_REPAIR_STATUS(val)\ argument
8860 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_5_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8863 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_6_XGMAC_NMB_IO_REPAIR_STATUS(val)\ argument
8865 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_6_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8868 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_7_XGMAC_NMB_IO_REPAIR_STATUS(val)\ argument
8870 #define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_7_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8873 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_0_XGMAC_NMB_IO_REP_STATUS(val)\ argument
8875 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_0_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8878 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_0_XGMAC_NMB_IO_REP_STATUS(val)\ argument
8880 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_0_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8883 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_1_XGMAC_NMB_IO_REP_STATUS(val)\ argument
8885 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_1_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8888 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_1_XGMAC_NMB_IO_REP_STATUS(val)\ argument
8890 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_1_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8893 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_2_XGMAC_NMB_IO_REP_STATUS(val)\ argument
8895 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_2_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8898 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_2_XGMAC_NMB_IO_REP_STATUS(val)\ argument
8900 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_2_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8903 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_3_XGMAC_NMB_IO_REP_STATUS(val)\ argument
8905 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_3_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8908 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_3_XGMAC_NMB_IO_REP_STATUS(val)\ argument
8910 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_3_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8913 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_4_XGMAC_NMB_IO_REP_STATUS(val)\ argument
8915 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_4_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8918 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_4_XGMAC_NMB_IO_REP_STATUS(val)\ argument
8920 #define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_4_XGMAC_NMB_IO_ALL_FUSE(val)\ argument
8930 #define VXGE_HAL_G3IFCMD_FB_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) vBIT(val, 24, 8) argument
8935 #define VXGE_HAL_G3IFCMD_FB_DLL_CK0_DLL_0_SA_CAL(val) vBIT(val, 0, 8) argument
8936 #define VXGE_HAL_G3IFCMD_FB_DLL_CK0_DLL_0_SB_CAL(val) vBIT(val, 8, 8) argument
8938 #define VXGE_HAL_G3IFCMD_FB_DLL_CK0_CMD_ADD_DLL_0_S(val) vBIT(val, 25, 7) argument
8940 #define VXGE_HAL_G3IFCMD_FB_DLL_CK0_DLL_UPD(val) vBIT(val, 44, 4) argument
8943 #define VXGE_HAL_G3IFCMD_FB_IO_CTRL_TERM(val) vBIT(val, 13, 3) argument
8945 #define VXGE_HAL_G3IFCMD_FB_IOCAL_RST_CYCLES(val) vBIT(val, 0, 16) argument
8946 #define VXGE_HAL_G3IFCMD_FB_IOCAL_RST_VALUE(val) vBIT(val, 17, 7) argument
8947 #define VXGE_HAL_G3IFCMD_FB_IOCAL_CORR_VALUE(val) vBIT(val, 24, 8) argument
8948 #define VXGE_HAL_G3IFCMD_FB_IOCAL_IOCAL_CTRL_CAL_VALUE0(val) vBIT(val, 33, 7) argument
8949 #define VXGE_HAL_G3IFCMD_FB_IOCAL_IOCAL_CTRL_CAL_VALUE1(val) vBIT(val, 41, 7) argument
8950 #define VXGE_HAL_G3IFCMD_FB_IOCAL_IOCAL_CTRL_CAL_VALUE2(val) vBIT(val, 49, 7) argument
8951 #define VXGE_HAL_G3IFCMD_FB_IOCAL_IOCAL_CTRL_CAL_VALUE3(val) vBIT(val, 57, 7) argument
8953 #define VXGE_HAL_G3IFCMD_FB_MASTER_DLL_CK_DDR_GR_RAW(val) vBIT(val, 1, 7) argument
8954 #define VXGE_HAL_G3IFCMD_FB_MASTER_DLL_CK_SAMPLE(val) vBIT(val, 8, 8) argument
8958 #define VXGE_HAL_G3IFCMD_FB_DLL_TRAINING_START_CODE(val) vBIT(val, 9, 7) argument
8959 #define VXGE_HAL_G3IFCMD_FB_DLL_TRAINING_END_CODE(val) vBIT(val, 17, 7) argument
8963 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8) argument
8964 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8) argument
8965 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8) argument
8966 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8) argument
8967 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7) argument
8972 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3) argument
8974 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8) argument
8975 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8) argument
8976 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7) argument
8980 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3) argument
8983 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING1_DDR_TRA_STATUS(val)\ argument
8985 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING1_DDR_TRA_MIN(val)\ argument
8987 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING1_DDR_TRA_MAX(val)\ argument
8989 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING1_DDR_ATRA_STATUS(val)\ argument
8991 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING1_DDR_ATRA_MIN(val)\ argument
8993 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING1_DDR_ATRA_MAX(val)\ argument
8996 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\ argument
8998 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\ argument
9000 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\ argument
9003 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING3_DLL_TRA_DATA00(val)\ argument
9005 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING3_DLL_TRA_DATA01(val)\ argument
9008 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ACT_TRAINING5_START_CODE(val)\ argument
9010 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ACT_TRAINING5_END_CODE(val)\ argument
9013 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ACT_TRAINING5_TCNT(val)\ argument
9027 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_OFFSET_EQUATION(val)\ argument
9029 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_OFFSET_DDR_VALUE(val)\ argument
9032 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\ argument
9034 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\ argument
9036 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRA_HOLD_DDR_TIME(val)\ argument
9038 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRA_HOLD_DDR_UPDATES(val)\ argument
9041 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\ argument
9043 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\ argument
9045 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_HOLD_DDR_TIME(val)\ argument
9047 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_HOLD_DDR_UPDATES(val)\ argument
9050 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\ argument
9052 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\ argument
9054 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\ argument
9056 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\ argument
9059 #define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_TIMER_VALUE(val)\ argument
9063 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS_SA_CAL(val)\ argument
9065 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS_SB_CAL(val)\ argument
9067 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS_ATRA_SA_CAL(val)\ argument
9069 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS_ATRA_SB_CAL(val)\ argument
9071 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS_DDR_DLL_S(val)\ argument
9077 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3) argument
9079 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8) argument
9080 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8) argument
9081 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7) argument
9085 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3) argument
9088 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING1_DDR_TRA_STATUS(val)\ argument
9090 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING1_DDR_TRA_MIN(val)\ argument
9092 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING1_DDR_TRA_MAX(val)\ argument
9094 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING1_DDR_ATRA_STATUS(val)\ argument
9096 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING1_DDR_ATRA_MIN(val)\ argument
9098 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING1_DDR_ATRA_MAX(val)\ argument
9101 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\ argument
9103 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\ argument
9105 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\ argument
9108 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING3_DLL_TRA_DATA00(val)\ argument
9110 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING3_DLL_TRA_DATA01(val)\ argument
9113 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ACT_TRAINING5_START_CODE(val)\ argument
9115 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ACT_TRAINING5_END_CODE(val)\ argument
9118 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ACT_TRAINING5_TCNT(val) vBIT(val, 28, 4) argument
9131 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_OFFSET_EQUATION(val)\ argument
9133 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_OFFSET_DDR_VALUE(val)\ argument
9136 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\ argument
9138 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\ argument
9140 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRA_HOLD_DDR_TIME(val)\ argument
9142 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRA_HOLD_DDR_UPDATES(val)\ argument
9145 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\ argument
9147 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\ argument
9149 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_HOLD_DDR_TIME(val)\ argument
9151 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_HOLD_DDR_UPDATES(val)\ argument
9154 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\ argument
9156 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\ argument
9158 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\ argument
9160 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\ argument
9163 #define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16) argument
9168 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8) argument
9169 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8) argument
9170 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8) argument
9171 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8) argument
9172 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7) argument
9177 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3) argument
9179 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8) argument
9180 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8) argument
9181 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7) argument
9185 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3) argument
9188 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING1_DDR_TRA_STATUS(val)\ argument
9190 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING1_DDR_TRA_MIN(val)\ argument
9192 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING1_DDR_TRA_MAX(val)\ argument
9194 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING1_DDR_ATRA_STATUS(val)\ argument
9196 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING1_DDR_ATRA_MIN(val)\ argument
9198 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING1_DDR_ATRA_MAX(val)\ argument
9201 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\ argument
9203 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\ argument
9205 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\ argument
9208 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING3_DLL_TRA_DATA00(val)\ argument
9210 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING3_DLL_TRA_DATA01(val)\ argument
9213 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ACT_TRAINING5_START_CODE(val)\ argument
9215 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ACT_TRAINING5_END_CODE(val)\ argument
9218 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ACT_TRAINING5_TCNT(val)\ argument
9232 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_OFFSET_EQUATION(val)\ argument
9234 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_OFFSET_DDR_VALUE(val)\ argument
9237 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\ argument
9239 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\ argument
9241 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRA_HOLD_DDR_TIME(val)\ argument
9243 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRA_HOLD_DDR_UPDATES(val)\ argument
9246 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\ argument
9248 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\ argument
9250 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_HOLD_DDR_TIME(val)\ argument
9252 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_HOLD_DDR_UPDATES(val)\ argument
9255 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\ argument
9257 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\ argument
9259 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\ argument
9261 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\ argument
9264 #define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16) argument
9267 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8) argument
9268 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8) argument
9269 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8) argument
9270 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8) argument
9271 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7) argument
9276 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3) argument
9278 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8) argument
9279 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8) argument
9280 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7) argument
9284 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3) argument
9287 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING1_DDR_TRA_STATUS(val)\ argument
9289 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING1_DDR_TRA_MIN(val)\ argument
9291 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING1_DDR_TRA_MAX(val)\ argument
9293 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING1_DDR_ATRA_STATUS(val)\ argument
9295 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING1_DDR_ATRA_MIN(val)\ argument
9297 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING1_DDR_ATRA_MAX(val)\ argument
9300 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\ argument
9302 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\ argument
9304 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\ argument
9307 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING3_DLL_TRA_DATA00(val)\ argument
9309 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING3_DLL_TRA_DATA01(val)\ argument
9312 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ACT_TRAINING5_START_CODE(val)\ argument
9314 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ACT_TRAINING5_END_CODE(val)\ argument
9317 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ACT_TRAINING5_TCNT(val) vBIT(val, 28, 4) argument
9330 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_OFFSET_EQUATION(val)\ argument
9332 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_OFFSET_DDR_VALUE(val)\ argument
9335 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\ argument
9337 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\ argument
9339 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRA_HOLD_DDR_TIME(val)\ argument
9341 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRA_HOLD_DDR_UPDATES(val)\ argument
9344 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\ argument
9346 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\ argument
9348 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_HOLD_DDR_TIME(val)\ argument
9350 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_HOLD_DDR_UPDATES(val)\ argument
9353 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\ argument
9355 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\ argument
9357 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\ argument
9359 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\ argument
9362 #define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16) argument
9372 #define VXGE_HAL_G3IFCMD_CMU_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) vBIT(val, 24, 8) argument
9377 #define VXGE_HAL_G3IFCMD_CMU_DLL_CK0_DLL_0_SA_CAL(val) vBIT(val, 0, 8) argument
9378 #define VXGE_HAL_G3IFCMD_CMU_DLL_CK0_DLL_0_SB_CAL(val) vBIT(val, 8, 8) argument
9380 #define VXGE_HAL_G3IFCMD_CMU_DLL_CK0_CMD_ADD_DLL_0_S(val) vBIT(val, 25, 7) argument
9382 #define VXGE_HAL_G3IFCMD_CMU_DLL_CK0_DLL_UPD(val) vBIT(val, 44, 4) argument
9385 #define VXGE_HAL_G3IFCMD_CMU_IO_CTRL_TERM(val) vBIT(val, 13, 3) argument
9387 #define VXGE_HAL_G3IFCMD_CMU_IOCAL_RST_CYCLES(val) vBIT(val, 0, 16) argument
9388 #define VXGE_HAL_G3IFCMD_CMU_IOCAL_RST_VALUE(val) vBIT(val, 17, 7) argument
9389 #define VXGE_HAL_G3IFCMD_CMU_IOCAL_CORR_VALUE(val) vBIT(val, 24, 8) argument
9390 #define VXGE_HAL_G3IFCMD_CMU_IOCAL_IOCAL_CTRL_CAL_VALUE0(val) vBIT(val, 33, 7) argument
9391 #define VXGE_HAL_G3IFCMD_CMU_IOCAL_IOCAL_CTRL_CAL_VALUE1(val) vBIT(val, 41, 7) argument
9392 #define VXGE_HAL_G3IFCMD_CMU_IOCAL_IOCAL_CTRL_CAL_VALUE2(val) vBIT(val, 49, 7) argument
9393 #define VXGE_HAL_G3IFCMD_CMU_IOCAL_IOCAL_CTRL_CAL_VALUE3(val) vBIT(val, 57, 7) argument
9395 #define VXGE_HAL_G3IFCMD_CMU_MASTER_DLL_CK_DDR_GR_RAW(val) vBIT(val, 1, 7) argument
9396 #define VXGE_HAL_G3IFCMD_CMU_MASTER_DLL_CK_SAMPLE(val) vBIT(val, 8, 8) argument
9400 #define VXGE_HAL_G3IFCMD_CMU_DLL_TRAINING_START_CODE(val) vBIT(val, 9, 7) argument
9401 #define VXGE_HAL_G3IFCMD_CMU_DLL_TRAINING_END_CODE(val) vBIT(val, 17, 7) argument
9405 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8) argument
9406 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8) argument
9407 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8) argument
9408 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8) argument
9409 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7) argument
9414 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3) argument
9416 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8) argument
9417 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8) argument
9418 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7) argument
9422 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3) argument
9426 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING1_DDR_TRA_STATUS(val)\ argument
9428 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING1_DDR_TRA_MIN(val)\ argument
9430 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING1_DDR_TRA_MAX(val)\ argument
9432 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING1_DDR_ATRA_STATUS(val)\ argument
9434 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING1_DDR_ATRA_MIN(val)\ argument
9436 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING1_DDR_ATRA_MAX(val)\ argument
9439 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\ argument
9441 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\ argument
9443 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\ argument
9446 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING3_DLL_TRA_DATA00(val)\ argument
9448 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING3_DLL_TRA_DATA01(val)\ argument
9451 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ACT_TRAINING5_START_CODE(val)\ argument
9453 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ACT_TRAINING5_END_CODE(val)\ argument
9456 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ACT_TRAINING5_TCNT(val)\ argument
9470 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_OFFSET_EQUATION(val)\ argument
9472 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_OFFSET_DDR_VALUE(val)\ argument
9475 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\ argument
9477 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\ argument
9479 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRA_HOLD_DDR_TIME(val)\ argument
9481 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRA_HOLD_DDR_UPDATES(val)\ argument
9484 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\ argument
9486 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\ argument
9488 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_HOLD_DDR_TIME(val)\ argument
9490 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_HOLD_DDR_UPDATES(val)\ argument
9493 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\ argument
9495 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\ argument
9497 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\ argument
9499 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\ argument
9502 #define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16) argument
9505 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8) argument
9506 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8) argument
9507 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8) argument
9508 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8) argument
9509 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7) argument
9514 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3) argument
9516 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8) argument
9517 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8) argument
9518 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7) argument
9522 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3) argument
9525 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING1_DDR_TRA_STATUS(val)\ argument
9527 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING1_DDR_TRA_MIN(val)\ argument
9529 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING1_DDR_TRA_MAX(val)\ argument
9531 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING1_DDR_ATRA_STATUS(val)\ argument
9533 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING1_DDR_ATRA_MIN(val)\ argument
9535 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING1_DDR_ATRA_MAX(val)\ argument
9538 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\ argument
9540 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\ argument
9542 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\ argument
9545 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING3_DLL_TRA_DATA00(val)\ argument
9547 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING3_DLL_TRA_DATA01(val)\ argument
9550 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ACT_TRAINING5_START_CODE(val)\ argument
9552 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ACT_TRAINING5_END_CODE(val)\ argument
9555 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ACT_TRAINING5_TCNT(val)\ argument
9569 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_OFFSET_EQUATION(val)\ argument
9571 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_OFFSET_DDR_VALUE(val)\ argument
9574 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\ argument
9576 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\ argument
9578 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRA_HOLD_DDR_TIME(val)\ argument
9580 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRA_HOLD_DDR_UPDATES(val)\ argument
9583 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\ argument
9585 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\ argument
9587 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_HOLD_DDR_TIME(val)\ argument
9589 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_HOLD_DDR_UPDATES(val)\ argument
9592 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\ argument
9594 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\ argument
9596 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\ argument
9598 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\ argument
9601 #define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16) argument
9606 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8) argument
9607 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8) argument
9608 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8) argument
9609 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8) argument
9610 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7) argument
9615 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3) argument
9617 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8) argument
9618 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8) argument
9619 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7) argument
9624 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_WDQS1_DLL_UPD(val)\ argument
9629 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING1_DDR_TRA_STATUS(val)\ argument
9631 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING1_DDR_TRA_MIN(val)\ argument
9633 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING1_DDR_TRA_MAX(val)\ argument
9635 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING1_DDR_ATRA_STATUS(val)\ argument
9637 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING1_DDR_ATRA_MIN(val)\ argument
9639 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING1_DDR_ATRA_MAX(val)\ argument
9642 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\ argument
9644 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\ argument
9646 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\ argument
9649 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING3_DLL_TRA_DATA00(val)\ argument
9651 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING3_DLL_TRA_DATA01(val)\ argument
9654 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ACT_TRAINING5_START_CODE(val)\ argument
9656 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ACT_TRAINING5_END_CODE(val)\ argument
9659 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ACT_TRAINING5_TCNT(val)\ argument
9673 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_OFFSET_EQUATION(val)\ argument
9675 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_OFFSET_DDR_VALUE(val)\ argument
9678 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\ argument
9680 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\ argument
9682 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRA_HOLD_DDR_TIME(val)\ argument
9684 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRA_HOLD_DDR_UPDATES(val)\ argument
9687 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\ argument
9689 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\ argument
9691 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_HOLD_DDR_TIME(val)\ argument
9693 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_HOLD_DDR_UPDATES(val)\ argument
9696 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\ argument
9698 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\ argument
9700 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\ argument
9702 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\ argument
9705 #define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16) argument
9708 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8) argument
9709 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8) argument
9710 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8) argument
9711 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8) argument
9712 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7) argument
9717 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3) argument
9719 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8) argument
9720 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8) argument
9721 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7) argument
9725 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3) argument
9728 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING1_DDR_TRA_STATUS(val)\ argument
9730 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING1_DDR_TRA_MIN(val)\ argument
9732 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING1_DDR_TRA_MAX(val)\ argument
9734 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING1_DDR_ATRA_STATUS(val)\ argument
9736 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING1_DDR_ATRA_MIN(val)\ argument
9738 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING1_DDR_ATRA_MAX(val)\ argument
9741 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\ argument
9743 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\ argument
9745 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\ argument
9748 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING3_DLL_TRA_DATA00(val)\ argument
9750 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING3_DLL_TRA_DATA01(val)\ argument
9753 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ACT_TRAINING5_START_CODE(val)\ argument
9755 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ACT_TRAINING5_END_CODE(val)\ argument
9759 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ACT_TRAINING5_TCNT(val)\ argument
9773 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_OFFSET_EQUATION(val)\ argument
9775 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_OFFSET_DDR_VALUE(val)\ argument
9778 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\ argument
9780 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\ argument
9782 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRA_HOLD_DDR_TIME(val)\ argument
9784 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRA_HOLD_DDR_UPDATES(val)\ argument
9787 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\ argument
9789 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\ argument
9791 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_HOLD_DDR_TIME(val)\ argument
9793 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_HOLD_DDR_UPDATES(val)\ argument
9796 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\ argument
9798 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\ argument
9800 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\ argument
9802 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\ argument
9805 #define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16) argument
9815 #define VXGE_HAL_G3IFCMD_CML_ERR_REG_G3IF_RWDQS_DLL_LOCK(val)\ argument
9821 #define VXGE_HAL_G3IFCMD_CML_DLL_CK0_DLL_0_SA_CAL(val) vBIT(val, 0, 8) argument
9822 #define VXGE_HAL_G3IFCMD_CML_DLL_CK0_DLL_0_SB_CAL(val) vBIT(val, 8, 8) argument
9824 #define VXGE_HAL_G3IFCMD_CML_DLL_CK0_CMD_ADD_DLL_0_S(val) vBIT(val, 25, 7) argument
9826 #define VXGE_HAL_G3IFCMD_CML_DLL_CK0_DLL_UPD(val) vBIT(val, 44, 4) argument
9829 #define VXGE_HAL_G3IFCMD_CML_IO_CTRL_TERM(val) vBIT(val, 13, 3) argument
9831 #define VXGE_HAL_G3IFCMD_CML_IOCAL_RST_CYCLES(val) vBIT(val, 0, 16) argument
9832 #define VXGE_HAL_G3IFCMD_CML_IOCAL_RST_VALUE(val) vBIT(val, 17, 7) argument
9833 #define VXGE_HAL_G3IFCMD_CML_IOCAL_CORR_VALUE(val) vBIT(val, 24, 8) argument
9834 #define VXGE_HAL_G3IFCMD_CML_IOCAL_IOCAL_CTRL_CAL_VALUE0(val)\ argument
9836 #define VXGE_HAL_G3IFCMD_CML_IOCAL_IOCAL_CTRL_CAL_VALUE1(val)\ argument
9838 #define VXGE_HAL_G3IFCMD_CML_IOCAL_IOCAL_CTRL_CAL_VALUE2(val)\ argument
9840 #define VXGE_HAL_G3IFCMD_CML_IOCAL_IOCAL_CTRL_CAL_VALUE3(val)\ argument
9843 #define VXGE_HAL_G3IFCMD_CML_MASTER_DLL_CK_DDR_GR_RAW(val) vBIT(val, 1, 7) argument
9844 #define VXGE_HAL_G3IFCMD_CML_MASTER_DLL_CK_SAMPLE(val) vBIT(val, 8, 8) argument
9848 #define VXGE_HAL_G3IFCMD_CML_DLL_TRAINING_START_CODE(val) vBIT(val, 9, 7) argument
9849 #define VXGE_HAL_G3IFCMD_CML_DLL_TRAINING_END_CODE(val) vBIT(val, 17, 7) argument
9853 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8) argument
9854 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8) argument
9855 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS_ATRA_SA_CAL(val)\ argument
9857 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS_ATRA_SB_CAL(val)\ argument
9859 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7) argument
9864 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3) argument
9866 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8) argument
9867 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8) argument
9868 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7) argument
9872 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3) argument
9876 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING1_DDR_TRA_STATUS(val)\ argument
9878 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING1_DDR_TRA_MIN(val)\ argument
9880 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING1_DDR_TRA_MAX(val)\ argument
9882 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING1_DDR_ATRA_STATUS(val)\ argument
9884 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING1_DDR_ATRA_MIN(val)\ argument
9886 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING1_DDR_ATRA_MAX(val)\ argument
9889 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\ argument
9891 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\ argument
9893 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\ argument
9896 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING3_DLL_TRA_DATA00(val)\ argument
9898 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING3_DLL_TRA_DATA01(val)\ argument
9901 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ACT_TRAINING5_START_CODE(val)\ argument
9903 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ACT_TRAINING5_END_CODE(val)\ argument
9906 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ACT_TRAINING5_TCNT(val)\ argument
9920 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_OFFSET_EQUATION(val)\ argument
9922 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_OFFSET_DDR_VALUE(val)\ argument
9925 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\ argument
9927 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\ argument
9929 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRA_HOLD_DDR_TIME(val)\ argument
9931 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRA_HOLD_DDR_UPDATES(val)\ argument
9934 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\ argument
9936 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\ argument
9938 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_HOLD_DDR_TIME(val)\ argument
9940 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_HOLD_DDR_UPDATES(val)\ argument
9943 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\ argument
9945 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\ argument
9947 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\ argument
9949 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\ argument
9952 #define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16) argument
9955 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8) argument
9956 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8) argument
9957 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8) argument
9958 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8) argument
9959 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7) argument
9964 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3) argument
9966 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8) argument
9967 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8) argument
9968 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7) argument
9972 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3) argument
9975 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING1_DDR_TRA_STATUS(val)\ argument
9977 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING1_DDR_TRA_MIN(val)\ argument
9979 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING1_DDR_TRA_MAX(val)\ argument
9981 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING1_DDR_ATRA_STATUS(val)\ argument
9983 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING1_DDR_ATRA_MIN(val)\ argument
9985 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING1_DDR_ATRA_MAX(val)\ argument
9988 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\ argument
9990 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\ argument
9992 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\ argument
9995 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING3_DLL_TRA_DATA00(val)\ argument
9997 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING3_DLL_TRA_DATA01(val)\ argument
10000 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ACT_TRAINING5_START_CODE(val)\ argument
10002 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ACT_TRAINING5_END_CODE(val)\ argument
10005 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ACT_TRAINING5_TCNT(val)\ argument
10019 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_OFFSET_EQUATION(val)\ argument
10021 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_OFFSET_DDR_VALUE(val)\ argument
10024 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\ argument
10026 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\ argument
10028 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRA_HOLD_DDR_TIME(val)\ argument
10030 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRA_HOLD_DDR_UPDATES(val)\ argument
10033 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\ argument
10035 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\ argument
10037 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_HOLD_DDR_TIME(val)\ argument
10039 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_HOLD_DDR_UPDATES(val)\ argument
10042 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\ argument
10044 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\ argument
10046 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\ argument
10048 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\ argument
10051 #define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_TIMER_VALUE(val)\ argument
10057 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8) argument
10058 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8) argument
10059 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8) argument
10060 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8) argument
10061 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7) argument
10066 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3) argument
10068 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8) argument
10069 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8) argument
10070 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7) argument
10074 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3) argument
10078 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING1_DDR_TRA_STATUS(val)\ argument
10080 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING1_DDR_TRA_MIN(val)\ argument
10082 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING1_DDR_TRA_MAX(val)\ argument
10084 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING1_DDR_ATRA_STATUS(val)\ argument
10086 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING1_DDR_ATRA_MIN(val)\ argument
10088 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING1_DDR_ATRA_MAX(val)\ argument
10091 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\ argument
10093 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\ argument
10095 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\ argument
10098 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING3_DLL_TRA_DATA00(val)\ argument
10100 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING3_DLL_TRA_DATA01(val)\ argument
10103 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ACT_TRAINING5_START_CODE(val)\ argument
10105 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ACT_TRAINING5_END_CODE(val)\ argument
10108 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ACT_TRAINING5_TCNT(val) \ argument
10122 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_OFFSET_EQUATION(val)\ argument
10124 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_OFFSET_DDR_VALUE(val)\ argument
10127 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\ argument
10129 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\ argument
10131 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRA_HOLD_DDR_TIME(val)\ argument
10133 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRA_HOLD_DDR_UPDATES(val)\ argument
10136 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\ argument
10138 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\ argument
10140 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_HOLD_DDR_TIME(val)\ argument
10142 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_HOLD_DDR_UPDATES(val)\ argument
10145 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\ argument
10147 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\ argument
10149 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\ argument
10151 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\ argument
10154 #define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16) argument
10157 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8) argument
10158 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8) argument
10159 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8) argument
10160 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8) argument
10161 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7) argument
10166 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3) argument
10168 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8) argument
10169 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8) argument
10170 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7) argument
10174 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3) argument
10177 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING1_DDR_TRA_STATUS(val)\ argument
10179 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING1_DDR_TRA_MIN(val)\ argument
10181 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING1_DDR_TRA_MAX(val)\ argument
10183 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING1_DDR_ATRA_STATUS(val)\ argument
10185 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING1_DDR_ATRA_MIN(val)\ argument
10187 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING1_DDR_ATRA_MAX(val)\ argument
10190 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\ argument
10192 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\ argument
10194 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\ argument
10197 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING3_DLL_TRA_DATA00(val)\ argument
10199 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING3_DLL_TRA_DATA01(val)\ argument
10202 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ACT_TRAINING5_START_CODE(val)\ argument
10204 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ACT_TRAINING5_END_CODE(val)\ argument
10207 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ACT_TRAINING5_TCNT(val)\ argument
10221 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_OFFSET_EQUATION(val)\ argument
10223 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_OFFSET_DDR_VALUE(val)\ argument
10226 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\ argument
10228 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\ argument
10230 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRA_HOLD_DDR_TIME(val)\ argument
10232 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRA_HOLD_DDR_UPDATES(val)\ argument
10235 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\ argument
10237 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\ argument
10239 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_HOLD_DDR_TIME(val)\ argument
10241 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_HOLD_DDR_UPDATES(val)\ argument
10244 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\ argument
10246 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\ argument
10248 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\ argument
10250 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\ argument
10253 #define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16) argument
10258 #define VXGE_HAL_VPATH_TO_VPLANE_MAP_VPATH_TO_VPLANE_MAP(val) vBIT(val, 3, 5) argument
10262 #define VXGE_HAL_XGXS_CFG_PORT_SIG_DETECT_FORCE_LOS(val) vBIT(val, 16, 4) argument
10263 #define VXGE_HAL_XGXS_CFG_PORT_SIG_DETECT_FORCE_VALID(val) vBIT(val, 20, 4) argument
10265 #define VXGE_HAL_XGXS_CFG_PORT_SEL_INFO_1(val) vBIT(val, 29, 3) argument
10266 #define VXGE_HAL_XGXS_CFG_PORT_TX_LANE0_SKEW(val) vBIT(val, 32, 4) argument
10267 #define VXGE_HAL_XGXS_CFG_PORT_TX_LANE1_SKEW(val) vBIT(val, 36, 4) argument
10268 #define VXGE_HAL_XGXS_CFG_PORT_TX_LANE2_SKEW(val) vBIT(val, 40, 4) argument
10269 #define VXGE_HAL_XGXS_CFG_PORT_TX_LANE3_SKEW(val) vBIT(val, 44, 4) argument
10271 #define VXGE_HAL_XGXS_RXBER_CFG_PORT_INTERVAL_DUR(val) vBIT(val, 0, 4) argument
10272 #define VXGE_HAL_XGXS_RXBER_CFG_PORT_RXGXS_INTERVAL_CNT(val) vBIT(val, 16, 48) argument
10274 #define VXGE_HAL_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_A_ERR_CNT(val)\ argument
10276 #define VXGE_HAL_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_B_ERR_CNT(val)\ argument
10278 #define VXGE_HAL_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_C_ERR_CNT(val)\ argument
10280 #define VXGE_HAL_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_D_ERR_CNT(val)\ argument
10283 #define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_TX_ACTIVITY(val) vBIT(val, 0, 4) argument
10284 #define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_RX_ACTIVITY(val) vBIT(val, 4, 4) argument
10286 #define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_BYTE_SYNC_LOST(val) vBIT(val, 12, 4) argument
10287 #define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_CTC_ERR(val) vBIT(val, 16, 4) argument
10289 #define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_DEC_ERR(val) vBIT(val, 24, 8) argument
10290 #define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_SKIP_INS_REQ(val) vBIT(val, 32, 4) argument
10291 #define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_SKIP_DEL_REQ(val) vBIT(val, 36, 4) argument
10293 #define VXGE_HAL_XGXS_PMA_RESET_PORT_SERDES_RESET(val) vBIT(val, 0, 8) argument
10301 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_TX_EN_LANE0(val) vBIT(val, 1, 3) argument
10302 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_TX_EN_LANE1(val) vBIT(val, 5, 3) argument
10303 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_TX_EN_LANE2(val) vBIT(val, 9, 3) argument
10304 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_TX_EN_LANE3(val) vBIT(val, 13, 3) argument
10319 #define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_CKO_WORD_CON(val) vBIT(val, 37, 3) argument
10328 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_BOOST_LANE0(val) vBIT(val, 0, 4) argument
10329 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_BOOST_LANE1(val) vBIT(val, 4, 4) argument
10330 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_BOOST_LANE2(val) vBIT(val, 8, 4) argument
10331 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_BOOST_LANE3(val) vBIT(val, 12, 4) argument
10332 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_ATTEN_LANE0(val) vBIT(val, 17, 3) argument
10333 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_ATTEN_LANE1(val) vBIT(val, 21, 3) argument
10334 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_ATTEN_LANE2(val) vBIT(val, 25, 3) argument
10335 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_ATTEN_LANE3(val) vBIT(val, 29, 3) argument
10348 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_EDGERATE_LANE0(val) vBIT(val, 44, 2) argument
10349 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_EDGERATE_LANE1(val) vBIT(val, 46, 2) argument
10350 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_EDGERATE_LANE2(val) vBIT(val, 48, 2) argument
10351 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_EDGERATE_LANE3(val) vBIT(val, 50, 2) argument
10352 #define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_LVL(val) vBIT(val, 55, 5) argument
10358 #define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_EQ_VAL_LANE0(val) vBIT(val, 5, 3) argument
10359 #define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_EQ_VAL_LANE1(val) vBIT(val, 9, 3) argument
10360 #define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_EQ_VAL_LANE2(val) vBIT(val, 13, 3) argument
10361 #define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_EQ_VAL_LANE3(val) vBIT(val, 17, 3) argument
10362 #define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_DPLL_MODE_LANE0(val)\ argument
10364 #define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_DPLL_MODE_LANE1(val)\ argument
10366 #define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_DPLL_MODE_LANE2(val)\ argument
10368 #define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_DPLL_MODE_LANE3(val)\ argument
10375 #define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_LOS_CTL_LANE0(val) vBIT(val, 4, 2) argument
10376 #define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_LOS_CTL_LANE1(val) vBIT(val, 6, 2) argument
10377 #define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_LOS_CTL_LANE2(val) vBIT(val, 8, 2) argument
10378 #define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_LOS_CTL_LANE3(val) vBIT(val, 10, 2) argument
10381 #define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_LOS_LVL(val) vBIT(val, 19, 5) argument
10382 #define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_CKO_ALIVE_CON(val) vBIT(val, 28, 2) argument
10384 #define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_MPLL_INT_CTL(val) vBIT(val, 33, 3) argument
10385 #define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_MPLL_PROP_CTL(val) vBIT(val, 37, 3) argument
10387 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_COMMA_DET_LANE0(val)\ argument
10389 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_COMMA_DET_LANE1(val)\ argument
10391 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_COMMA_DET_LANE2(val)\ argument
10393 #define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_COMMA_DET_LANE3(val)\ argument
10422 #define VXGE_HAL_XGXS_SERDES_CR_ACCESS_PORT_ADDR(val) vBIT(val, 16, 16) argument
10423 #define VXGE_HAL_XGXS_SERDES_CR_ACCESS_PORT_DATA(val) vBIT(val, 48, 16) argument
10427 #define VXGE_HAL_XGXS_INFO_PORT_XMACJ_INFO_0(val) vBIT(val, 0, 32) argument
10428 #define VXGE_HAL_XGXS_INFO_PORT_XMACJ_INFO_1(val) vBIT(val, 32, 32) argument
10430 #define VXGE_HAL_RATEMGMT_CFG_PORT_MODE(val) vBIT(val, 2, 2) argument
10447 #define VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_T_RETRY_PHY_QUERY(val)\ argument
10449 #define VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_T_WAIT_MDIO_RESP(val)\ argument
10451 #define VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_T_LDOWN_REAUTO_RESP(val)\ argument
10459 #define VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_T_SYNC_10G_KX4(val) vBIT(val, 16, 4) argument
10460 #define VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_T_SYNC_1G_KX(val) vBIT(val, 20, 4) argument
10461 #define VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_T_DME_EXCHANGE(val) vBIT(val, 24, 4) argument
10465 #define VXGE_HAL_ANBE_CFG_PORT_RESET_CFG_REGS(val) vBIT(val, 0, 8) argument
10466 #define VXGE_HAL_ANBE_CFG_PORT_ALIGN_10G_KX4_OVERRIDE(val) vBIT(val, 10, 2) argument
10467 #define VXGE_HAL_ANBE_CFG_PORT_SYNC_1G_KX_OVERRIDE(val) vBIT(val, 14, 2) argument
10471 #define VXGE_HAL_ANBE_MGR_CTRL_PORT_ADDR(val) vBIT(val, 15, 9) argument
10472 #define VXGE_HAL_ANBE_MGR_CTRL_PORT_DATA(val) vBIT(val, 32, 32) argument
10487 #define VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_ANBEFSM_STATE(val)\ argument
10505 #define VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_COUNT_BP(val)\ argument
10507 #define VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_COUNT_NP(val)\ argument
10515 #define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_TX_NONCE(val)\ argument
10522 #define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ECHOED_NONCE(val)\ argument
10524 #define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_SELECTOR_FIELD(val)\ argument
10527 #define VXGE_HAL_ANBE_HWFSM_NP_STATUS_PORT_RATEMGMT_NP_BITS_47_TO_32(val)\ argument
10529 #define VXGE_HAL_ANBE_HWFSM_NP_STATUS_PORT_RATEMGMT_NP_BITS_31_TO_0(val)\ argument
10537 #define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_ANTPFSM_STATE(val)\ argument
10559 #define VXGE_HAL_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ABILITY_FIELD(val)\ argument
10561 #define VXGE_HAL_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_SELECTOR_FIELD(val)\ argument
10569 #define VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_MESSAGE_CODE(val)\ argument
10571 #define VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_UNF_CODE_FIELD1(val)\ argument
10573 #define VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_UNF_CODE_FIELD2(val)\ argument
10577 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE(val) vBIT(val, 5, 3) argument
10578 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD(val) vBIT(val, 11, 5) argument
10579 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR(val) vBIT(val, 16, 16) argument
10580 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_DATA(val) vBIT(val, 32, 16) argument
10581 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ST_PATTERN(val) vBIT(val, 49, 2) argument
10583 #define VXGE_HAL_MDIO_MGR_ACCESS_PORT_PRTAD(val) vBIT(val, 55, 5) argument
10592 #define VXGE_HAL_XMAC_VSPORT_CHOICES_VH_VSPORT_VECTOR(val) vBIT(val, 0, 17) argument
10596 #define VXGE_HAL_RX_THRESH_CFG_VP_PAUSE_LOW_THR(val) vBIT(val, 0, 8) argument
10597 #define VXGE_HAL_RX_THRESH_CFG_VP_PAUSE_HIGH_THR(val) vBIT(val, 8, 8) argument
10598 #define VXGE_HAL_RX_THRESH_CFG_VP_RED_THR_0(val) vBIT(val, 16, 8) argument
10599 #define VXGE_HAL_RX_THRESH_CFG_VP_RED_THR_1(val) vBIT(val, 24, 8) argument
10600 #define VXGE_HAL_RX_THRESH_CFG_VP_RED_THR_2(val) vBIT(val, 32, 8) argument
10601 #define VXGE_HAL_RX_THRESH_CFG_VP_RED_THR_3(val) vBIT(val, 40, 8) argument
10605 #define VXGE_HAL_FAU_ADAPTIVE_LRO_VPATH_ENABLE_EN(val) vBIT(val, 0, 17) argument
10607 #define VXGE_HAL_FAU_ADAPTIVE_LRO_BASE_SID_VP_VALUE(val) vBIT(val, 2, 6) argument
10608 #define VXGE_HAL_FAU_ADAPTIVE_LRO_BASE_SID_VP_USE_HASH_WIDTH(val)\ argument