Lines Matching refs:bit8
45 (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16);
48 (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32);
51 (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET))))
54 (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET))))
57 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \
58 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)(((bit16)VALUE16)&0xFF);
61 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \
62 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \
63 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \
64 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)(((bit32)VALUE32)&0xFF);
67 (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
68 (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1)));
71 (*(bit8 *)(((bit8 *)ADDR32)+3)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
72 (*(bit8 *)(((bit8 *)ADDR32)+2)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \
73 (*(bit8 *)(((bit8 *)ADDR32)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \
74 (*(bit8 *)(((bit8 *)ADDR32))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3)));
83 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \
84 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit16)VALUE16)&0xFF);
87 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \
88 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \
89 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \
90 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit32)VALUE32)&0xFF);
93 (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
94 (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1)));
97 (*((bit8 *)(((bit8 *)ADDR32)+3))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
98 (*((bit8 *)(((bit8 *)ADDR32)+2))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \
99 (*((bit8 *)(((bit8 *)ADDR32)+1))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \
100 (*((bit8 *)(((bit8 *)ADDR32)))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3)));
103 (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16);
106 (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32);
109 (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET))));
112 (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET))));
250 #define BIT32_B0_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF))
254 #define BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8))
258 #define BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16))
262 #define BIT32_B3_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24))
363 #define BIT32_B0_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24))
367 #define BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16))
371 #define BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8))
375 #define BIT32_B3_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF))
545 #define DMA_BIT32_B0_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF))
549 #define DMA_BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8))
553 #define DMA_BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16))
557 #define DMA_BIT32_B3_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24))
713 #define DMA_BIT32_B0_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24))
717 #define DMA_BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16))
721 #define DMA_BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8))
725 #define DMA_BIT32_B3_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF))
1736 bit8 reserved1; /* reserved */
1737 …bit8 maxPorts; /* This field is valid if bit 29 of the flags field is set to 1 */
1847 bit8 regDumpSrc;
1848 bit8 regDumpNum;
1849 bit8 reserved[2];
1984 bit8 udtArray[6];
1985 bit8 udrtArray[6];
2061 bit8 phyCount; /* number of phy available in the controller */
2062 bit8 controllerSetting;/* Controller setting
2065 bit8 PCILinkRate; /* PCI generation 1/2/3 2.5g/5g/8g */
2066 bit8 PCIWidth; /* PCI number of lanes */
2157 bit8 smpFrameType; /* 0x40 for request, 0x41 for response*/
2158 bit8 function; /* 0x02 for read, 0x82 for write */
2159 bit8 registerType; /* used only in request */
2160 bit8 registerIndex; /* used only in request */
2161 bit8 registerCount; /* used only in request */
2162 bit8 functionResult; /* used only in response */
2174 bit8 reserved1;
2175 bit8 version:4;
2176 bit8 reserved2:4;
2177 bit8 gpRegisterCount:4;
2178 bit8 cfgRegisterCount:3;
2179 bit8 gpioEnable:1;
2180 bit8 supportedDriveCount;
2189 bit8 reserved;
2190 bit8 blinkGenA:4;
2191 bit8 blinkGenB:4;
2192 bit8 maxActOn:4;
2193 bit8 forceActOff:4;
2194 bit8 stretchActOn:4;
2195 bit8 stretchActOff:4;
2430 bit8 sasHwEventQueue[AGSA_MAX_VALID_PHYS];
2431 bit8 sataNCQErrorEventQueue[AGSA_MAX_VALID_PHYS];
2432 bit8 tgtITNexusEventQueue[AGSA_MAX_VALID_PHYS];
2433 bit8 tgtSSPEventQueue[AGSA_MAX_VALID_PHYS];
2434 bit8 tgtSMPEventQueue[AGSA_MAX_VALID_PHYS];
2435 bit8 iqNormalPriorityProcessingDepth;
2436 bit8 iqHighPriorityProcessingDepth;
2437 bit8 generalEventQueue;
2438 bit8 tgtDeviceRemovedEventQueue;
2448 bit8 *aap1Img; /**< AAP1 Image */
2450 bit8 *ilaImg; /**< ILA Image */
2452 bit8 *iopImg; /**< IOP Image */
2454 bit8 *istrImg; /**< Init String */
2549 bit8 sasAddressLo[4]; /**< HOST SAS address lower part */
2550 bit8 sasAddressHi[4]; /**< HOST SAS address higher part */
2551 bit8 phyIdentifier; /**< PHY IDENTIFIER of the PHY */
2565 bit8 reserved;
2567 bit8 devType_S_Rate;
2580 bit8 sasAddressHi[4];
2581 bit8 sasAddressLo[4];
2652 bit8 connection; /**< How device is connected:
2658 bit8 portMultiplierField; /**< The first 4 bits indicate that
2664 bit8 stpPhyIdentifier; /**< PHY ID of the STP PHY. Valid only if
2667 bit8 reserved;
2668 bit8 signature[8]; /**< The signature of SATA in Task
2685 bit8 initiator_ssp_stp_smp; /**< SAS initiator capabilities */
2691 bit8 target_ssp_stp_smp; /**< SAS target capabilities */
2698 bit8 phyIdentifier; /**< PHY IDENTIFIER in IDENTIFY address
2792 bit8 lun[8];
2793 bit8 reserved1;
2794 bit8 efb_tp_taskAttribute;
2795 bit8 reserved2;
2796 bit8 additionalCdbLen;
2797 bit8 cdb[MAX_CDB_LEN];
2827 bit8 udtArray[DIF_UDT_SIZE];
2828 bit8 udrtArray[DIF_UDT_SIZE];
3143 bit8 scsiCDB[16];
3274 bit8 dekBlob[80];
3278 bit8 kekBlob[48];
3293 bit8 ID[AGSA_ID_SIZE];
3359 bit8 sasAddressHi[4];
3360 bit8 sasAddressLo[4];
3844 bit8 *senseLen;
3858 bit8 additionalCdbLen;
3859 bit8 *cdb;
3860 bit8 *lun;
3862 bit8 taskAttribute; /* TD_xxx */