47 	WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);  in avivo_crtc_load_lut()
49 	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);  in avivo_crtc_load_lut()
50 	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);  in avivo_crtc_load_lut()
51 	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);  in avivo_crtc_load_lut()
53 	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);  in avivo_crtc_load_lut()
54 	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);  in avivo_crtc_load_lut()
55 	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);  in avivo_crtc_load_lut()
69 	WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);  in avivo_crtc_load_lut()
80 	WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);  in dce4_crtc_load_lut()
82 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);  in dce4_crtc_load_lut()
83 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);  in dce4_crtc_load_lut()
84 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);  in dce4_crtc_load_lut()
86 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);  in dce4_crtc_load_lut()
87 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);  in dce4_crtc_load_lut()
88 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);  in dce4_crtc_load_lut()
90 	WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);  in dce4_crtc_load_lut()
91 	WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);  in dce4_crtc_load_lut()
93 	WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);  in dce4_crtc_load_lut()
95 		WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,  in dce4_crtc_load_lut()
111 	WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
114 	WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
116 	WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
118 	WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
122 	WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);  in dce5_crtc_load_lut()
124 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);  in dce5_crtc_load_lut()
125 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);  in dce5_crtc_load_lut()
126 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);  in dce5_crtc_load_lut()
128 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);  in dce5_crtc_load_lut()
129 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);  in dce5_crtc_load_lut()
130 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);  in dce5_crtc_load_lut()
132 	WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);  in dce5_crtc_load_lut()
133 	WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);  in dce5_crtc_load_lut()
135 	WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);  in dce5_crtc_load_lut()
137 		WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
143 	WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
148 	WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
151 	WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
154 	WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
158 	WREG32(0x6940 + radeon_crtc->crtc_offset, 0);  in dce5_crtc_load_lut()