111   void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
308     int Cycles = Stage->getValueAsInt("Cycles");  in FormItineraryStageString()  local
309     ItinString += "  { " + itostr(Cycles) + ", ";  in FormItineraryStageString()
936                                            std::vector<int64_t> &Cycles,  in ExpandProcResources()  argument
938   assert(PRVec.size() == Cycles.size() && "failed precondition");  in ExpandProcResources()
958         Cycles.push_back(Cycles[i]);  in ExpandProcResources()
974         Cycles.push_back(Cycles[i]);  in ExpandProcResources()
1075       WLEntry.Cycles = 0;  in GenSchedClassTables()
1096         WLEntry.Cycles += WriteRes->getValueAsInt("Latency");  in GenSchedClassTables()
1105         std::vector<int64_t> Cycles =  in GenSchedClassTables()  local
1108         if (Cycles.empty()) {  in GenSchedClassTables()
1111           Cycles.resize(PRVec.size(), 1);  in GenSchedClassTables()
1112         } else if (Cycles.size() != PRVec.size()) {  in GenSchedClassTables()
1120                   .concat(Twine(Cycles.size())));  in GenSchedClassTables()
1123         ExpandProcResources(PRVec, Cycles, ProcModel);  in GenSchedClassTables()
1130           WPREntry.Cycles = Cycles[PRIdx];  in GenSchedClassTables()
1139               WriteProcResources[WPRIdx].Cycles += WPREntry.Cycles;  in GenSchedClassTables()
1177         RAEntry.Cycles = ReadAdvance->getValueAsInt("Cycles");  in GenSchedClassTables()
1255        << format("%2d", WPREntry.Cycles) << "}";  in EmitSchedClassTables()
1270     OS << "  {" << format("%2d", WLEntry.Cycles) << ", "  in EmitSchedClassTables()
1288        << format("%2d", RAEntry.Cycles) << "}";  in EmitSchedClassTables()