Lines Matching refs:SExtVT
27654 MVT SExtVT = SrcVT == MVT::v16i1 ? MVT::v16i8 : MVT::v32i8; in LowerBITCAST() local
27656 SDValue V = DAG.getSExtOrTrunc(Src, DL, SExtVT); in LowerBITCAST()
36213 static SDValue signExtendBitcastSrcVector(SelectionDAG &DAG, EVT SExtVT, in signExtendBitcastSrcVector() argument
36217 return DAG.getNode(ISD::SIGN_EXTEND, DL, SExtVT, Src); in signExtendBitcastSrcVector()
36222 Src.getOpcode(), DL, SExtVT, in signExtendBitcastSrcVector()
36223 signExtendBitcastSrcVector(DAG, SExtVT, Src.getOperand(0), DL), in signExtendBitcastSrcVector()
36224 signExtendBitcastSrcVector(DAG, SExtVT, Src.getOperand(1), DL)); in signExtendBitcastSrcVector()
36266 MVT SExtVT; in combineBitcastvxi1() local
36272 SExtVT = MVT::v2i64; in combineBitcastvxi1()
36275 SExtVT = MVT::v4i32; in combineBitcastvxi1()
36279 SExtVT = MVT::v4i64; in combineBitcastvxi1()
36284 SExtVT = MVT::v8i16; in combineBitcastvxi1()
36292 SExtVT = MVT::v8i32; in combineBitcastvxi1()
36297 SExtVT = MVT::v16i8; in combineBitcastvxi1()
36304 SExtVT = MVT::v32i8; in combineBitcastvxi1()
36310 SExtVT = MVT::v64i8; in combineBitcastvxi1()
36316 SDValue V = PropagateSExt ? signExtendBitcastSrcVector(DAG, SExtVT, Src, DL) in combineBitcastvxi1()
36317 : DAG.getNode(ISD::SIGN_EXTEND, DL, SExtVT, Src); in combineBitcastvxi1()
36319 if (SExtVT == MVT::v16i8 || SExtVT == MVT::v32i8 || SExtVT == MVT::v64i8) { in combineBitcastvxi1()
36322 if (SExtVT == MVT::v8i16) in combineBitcastvxi1()