345     unsigned BaseReg, IndexReg, TmpReg, Scale;  member in __anon0bf27a230111::X86AsmParser::IntelExprStateMachine
368         : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0),  in IntelExprStateMachine()
378     unsigned getIndexReg() { return IndexReg; }  in getIndexReg()
482             if (IndexReg) {  in onPlus()
486             IndexReg = TmpReg;  in onPlus()
537             if (IndexReg) {  in onMinus()
541             IndexReg = TmpReg;  in onMinus()
592           if (IndexReg) {  in onRegister()
597           IndexReg = Reg;  in onRegister()
666           if (IndexReg) {  in onInteger()
670           IndexReg = TmpReg;  in onInteger()
766             assert (!IndexReg && "BaseReg/IndexReg already set!");  in onRBrac()
767             IndexReg = TmpReg;  in onRBrac()
900                         unsigned IndexReg, unsigned Scale, SMLoc Start,
1043 static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg,  in CheckBaseRegAndIndexRegAndScale()  argument
1059   if (IndexReg != 0 &&  in CheckBaseRegAndIndexRegAndScale()
1060       !(IndexReg == X86::EIZ || IndexReg == X86::RIZ ||  in CheckBaseRegAndIndexRegAndScale()
1061         X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1062         X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1063         X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1064         X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1065         X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1066         X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg))) {  in CheckBaseRegAndIndexRegAndScale()
1071   if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg != 0) ||  in CheckBaseRegAndIndexRegAndScale()
1072       IndexReg == X86::EIP || IndexReg == X86::RIP ||  in CheckBaseRegAndIndexRegAndScale()
1073       IndexReg == X86::ESP || IndexReg == X86::RSP) {  in CheckBaseRegAndIndexRegAndScale()
1088       X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {  in CheckBaseRegAndIndexRegAndScale()
1093   if (BaseReg != 0 && IndexReg != 0) {  in CheckBaseRegAndIndexRegAndScale()
1095         (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1096          X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1097          IndexReg == X86::EIZ)) {  in CheckBaseRegAndIndexRegAndScale()
1102         (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1103          X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1104          IndexReg == X86::RIZ)) {  in CheckBaseRegAndIndexRegAndScale()
1109       if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1110           X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {  in CheckBaseRegAndIndexRegAndScale()
1115           (IndexReg != X86::SI && IndexReg != X86::DI)) {  in CheckBaseRegAndIndexRegAndScale()
1409     unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,  in CreateMemForInlineAsm()  argument
1440   if (IsGlobalLV && (BaseReg || IndexReg)) {  in CreateMemForInlineAsm()
1448                                  IndexReg, Scale, Start, End, Size, Identifier,  in CreateMemForInlineAsm()
1971   unsigned IndexReg = SM.getIndexReg();  in ParseIntelOperand()  local
1975       (IndexReg == X86::ESP || IndexReg == X86::RSP))  in ParseIntelOperand()
1976     std::swap(BaseReg, IndexReg);  in ParseIntelOperand()
1981       !(X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||  in ParseIntelOperand()
1982         X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||  in ParseIntelOperand()
1983         X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg)) &&  in ParseIntelOperand()
1987     std::swap(BaseReg, IndexReg);  in ParseIntelOperand()
1990       X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg))  in ParseIntelOperand()
2001       (IndexReg == X86::BX || IndexReg == X86::BP))  in ParseIntelOperand()
2002     std::swap(BaseReg, IndexReg);  in ParseIntelOperand()
2004   if ((BaseReg || IndexReg) &&  in ParseIntelOperand()
2005       CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),  in ParseIntelOperand()
2009     return CreateMemForInlineAsm(RegNo, Disp, BaseReg, IndexReg,  in ParseIntelOperand()
2012   if (!(BaseReg || IndexReg || RegNo))  in ParseIntelOperand()
2015                                BaseReg, IndexReg, Scale, Start, End, Size);  in ParseIntelOperand()
2294   unsigned BaseReg = 0, IndexReg = 0, Scale = 1;  in ParseMemOperand()  local
2334         IndexReg = cast<X86MCExpr>(E)->getRegNo();  in ParseMemOperand()
2339         if (IndexReg == X86::RIP)  in ParseMemOperand()
2373   if (BaseReg == X86::DX && IndexReg == 0 && Scale == 1 && SegReg == 0 &&  in ParseMemOperand()
2377   if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),  in ParseMemOperand()
2381   if (SegReg || BaseReg || IndexReg)  in ParseMemOperand()
2383                                  IndexReg, Scale, StartLoc, EndLoc);  in ParseMemOperand()