Lines Matching refs:Cond
81 SmallVectorImpl<MachineOperand> &Cond) const { in AnalyzeCondBr()
88 Cond.push_back(MachineOperand::CreateImm(Opc)); in AnalyzeCondBr()
91 Cond.push_back(Inst->getOperand(i)); in AnalyzeCondBr()
97 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
100 BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); in analyzeBranch()
107 ArrayRef<MachineOperand> Cond) const { in BuildCondBr()
108 unsigned Opc = Cond[0].getImm(); in BuildCondBr()
112 for (unsigned i = 1; i < Cond.size(); ++i) { in BuildCondBr()
113 assert((Cond[i].isImm() || Cond[i].isReg()) && in BuildCondBr()
115 MIB.add(Cond[i]); in BuildCondBr()
123 ArrayRef<MachineOperand> Cond, in insertBranch() argument
135 assert((Cond.size() <= 3) && in insertBranch()
140 BuildCondBr(MBB, TBB, DL, Cond); in insertBranch()
147 if (Cond.empty()) in insertBranch()
150 BuildCondBr(MBB, TBB, DL, Cond); in insertBranch()
183 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
184 assert( (Cond.size() && Cond.size() <= 3) && in reverseBranchCondition()
186 Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm())); in reverseBranchCondition()
192 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify, in analyzeBranch() argument
243 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond); in analyzeBranch()
272 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond); in analyzeBranch()