Lines Matching refs:BaseReg
1630 bool RegDeadKill, bool RegUndef, unsigned BaseReg, in InsertLDR_STR() argument
1638 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); in InsertLDR_STR()
1647 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); in InsertLDR_STR()
1665 Register BaseReg = BaseOp.getReg(); in FixInvalidRegPairOp() local
1673 bool Errata602117 = EvenReg == BaseReg && in FixInvalidRegPairOp()
1706 .addReg(BaseReg, getKillRegState(BaseKill)) in FixInvalidRegPairOp()
1714 .addReg(BaseReg, getKillRegState(BaseKill)) in FixInvalidRegPairOp()
1735 if (isLd && TRI->regsOverlap(EvenReg, BaseReg)) { in FixInvalidRegPairOp()
1736 assert(!TRI->regsOverlap(OddReg, BaseReg)); in FixInvalidRegPairOp()
1738 false, BaseReg, false, BaseUndef, Pred, PredReg, TII, MI); in FixInvalidRegPairOp()
1740 false, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII, in FixInvalidRegPairOp()
1751 if (EvenReg == BaseReg) in FixInvalidRegPairOp()
1754 EvenUndef, BaseReg, false, BaseUndef, Pred, PredReg, TII, in FixInvalidRegPairOp()
1757 OddUndef, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII, in FixInvalidRegPairOp()
2067 unsigned &OddReg, unsigned &BaseReg,
2151 unsigned &BaseReg, int &Offset, in CanFormLdStDWord() argument
2216 BaseReg = Op0->getOperand(1).getReg(); in CanFormLdStDWord()
2317 unsigned BaseReg = 0, PredReg = 0; in RescheduleOps() local
2324 FirstReg, SecondReg, BaseReg, in RescheduleOps()
2339 .addReg(BaseReg); in RescheduleOps()
2353 .addReg(BaseReg); in RescheduleOps()