174         int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
180         int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
625     int Offset, unsigned Base, bool BaseKill, unsigned Opcode,  in CreateLoadStoreMulti()  argument
699     int BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2ADDspImm  in CreateLoadStoreMulti()
711       BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2SUBspImm  in CreateLoadStoreMulti()
724     bool KillOldBase = BaseKill &&  in CreateLoadStoreMulti()
772     BaseKill = true; // New base is always killed straight away.  in CreateLoadStoreMulti()
791   if (isThumb1 && !SafeToClobberCPSR && Writeback && !BaseKill)  in CreateLoadStoreMulti()
808        .addReg(Base, getKillRegState(BaseKill));  in CreateLoadStoreMulti()
812     if (!BaseKill)  in CreateLoadStoreMulti()
817     MIB.addReg(Base, getKillRegState(BaseKill));  in CreateLoadStoreMulti()
832     int Offset, unsigned Base, bool BaseKill, unsigned Opcode,  in CreateLoadStoreDouble()  argument
902   bool BaseKill = LatestMI->killsRegister(Base);  in MergeOpsUpdate()  local
908     Merged = CreateLoadStoreDouble(MBB, InsertBefore, Offset, Base, BaseKill,  in MergeOpsUpdate()
912     Merged = CreateLoadStoreMulti(MBB, InsertBefore, Offset, Base, BaseKill,  in MergeOpsUpdate()
1272   bool BaseKill = BaseOP.isKill();  in MergeBaseUpdateLSMultiple()  local
1304       if (!STI->hasMinSize() || !BaseKill)  in MergeBaseUpdateLSMultiple()
1326     .addReg(Base, getKillRegState(BaseKill))  in MergeBaseUpdateLSMultiple()
1398   bool BaseKill = getLoadStoreBaseOp(*MI).isKill();  in MergeBaseUpdateLoadStore()  local
1450       .addReg(Base, getKillRegState(isLd ? BaseKill : false))  in MergeBaseUpdateLoadStore()
1631                           bool BaseKill, bool BaseUndef, ARMCC::CondCodes Pred,  in InsertLDR_STR()  argument
1638       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));  in InsertLDR_STR()
1647       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));  in InsertLDR_STR()
1690   bool BaseKill = BaseOp.isKill();  in FixInvalidRegPairOp()  local
1706         .addReg(BaseReg, getKillRegState(BaseKill))  in FixInvalidRegPairOp()
1714         .addReg(BaseReg, getKillRegState(BaseKill))  in FixInvalidRegPairOp()
1740                     false, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,  in FixInvalidRegPairOp()
1757                     OddUndef, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,  in FixInvalidRegPairOp()