Lines Matching refs:ARM
89 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
90 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
91 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
92 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
93 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
94 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
95 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
96 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
99 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
100 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
101 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
102 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
103 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
104 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
105 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
106 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
110 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), in ARMBaseInstrInfo()
191 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress()
200 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) in convertToThreeAddress()
209 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) in convertToThreeAddress()
222 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress()
229 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) in convertToThreeAddress()
437 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); in insertBranch()
439 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); in insertBranch()
550 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) || in DefinesPredicate()
551 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) { in DefinesPredicate()
562 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead()) in isCPSRDefined()
625 case ARM::tADC: // ADC (register) T1 in isEligibleForITBlock()
626 case ARM::tADDi3: // ADD (immediate) T1 in isEligibleForITBlock()
627 case ARM::tADDi8: // ADD (immediate) T2 in isEligibleForITBlock()
628 case ARM::tADDrr: // ADD (register) T1 in isEligibleForITBlock()
629 case ARM::tAND: // AND (register) T1 in isEligibleForITBlock()
630 case ARM::tASRri: // ASR (immediate) T1 in isEligibleForITBlock()
631 case ARM::tASRrr: // ASR (register) T1 in isEligibleForITBlock()
632 case ARM::tBIC: // BIC (register) T1 in isEligibleForITBlock()
633 case ARM::tEOR: // EOR (register) T1 in isEligibleForITBlock()
634 case ARM::tLSLri: // LSL (immediate) T1 in isEligibleForITBlock()
635 case ARM::tLSLrr: // LSL (register) T1 in isEligibleForITBlock()
636 case ARM::tLSRri: // LSR (immediate) T1 in isEligibleForITBlock()
637 case ARM::tLSRrr: // LSR (register) T1 in isEligibleForITBlock()
638 case ARM::tMUL: // MUL T1 in isEligibleForITBlock()
639 case ARM::tMVN: // MVN (register) T1 in isEligibleForITBlock()
640 case ARM::tORR: // ORR (register) T1 in isEligibleForITBlock()
641 case ARM::tROR: // ROR (register) T1 in isEligibleForITBlock()
642 case ARM::tRSB: // RSB (immediate) T1 in isEligibleForITBlock()
643 case ARM::tSBC: // SBC (register) T1 in isEligibleForITBlock()
644 case ARM::tSUBi3: // SUB (immediate) T1 in isEligibleForITBlock()
645 case ARM::tSUBi8: // SUB (immediate) T2 in isEligibleForITBlock()
646 case ARM::tSUBrr: // SUB (register) T1 in isEligibleForITBlock()
687 if (MO.getReg() != ARM::CPSR) in IsCPSRDead()
715 case ARM::MOVi16_ga_pcrel: in getInstSizeInBytes()
716 case ARM::MOVTi16_ga_pcrel: in getInstSizeInBytes()
717 case ARM::t2MOVi16_ga_pcrel: in getInstSizeInBytes()
718 case ARM::t2MOVTi16_ga_pcrel: in getInstSizeInBytes()
720 case ARM::MOVi32imm: in getInstSizeInBytes()
721 case ARM::t2MOVi32imm: in getInstSizeInBytes()
723 case ARM::CONSTPOOL_ENTRY: in getInstSizeInBytes()
724 case ARM::JUMPTABLE_INSTS: in getInstSizeInBytes()
725 case ARM::JUMPTABLE_ADDRS: in getInstSizeInBytes()
726 case ARM::JUMPTABLE_TBB: in getInstSizeInBytes()
727 case ARM::JUMPTABLE_TBH: in getInstSizeInBytes()
731 case ARM::Int_eh_sjlj_longjmp: in getInstSizeInBytes()
733 case ARM::tInt_eh_sjlj_longjmp: in getInstSizeInBytes()
735 case ARM::tInt_WIN_eh_sjlj_longjmp: in getInstSizeInBytes()
737 case ARM::Int_eh_sjlj_setjmp: in getInstSizeInBytes()
738 case ARM::Int_eh_sjlj_setjmp_nofp: in getInstSizeInBytes()
740 case ARM::tInt_eh_sjlj_setjmp: in getInstSizeInBytes()
741 case ARM::t2Int_eh_sjlj_setjmp: in getInstSizeInBytes()
742 case ARM::t2Int_eh_sjlj_setjmp_nofp: in getInstSizeInBytes()
744 case ARM::SPACE: in getInstSizeInBytes()
746 case ARM::INLINEASM: in getInstSizeInBytes()
747 case ARM::INLINEASM_BR: { in getInstSizeInBytes()
773 ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR) in copyFromCPSR()
774 : ARM::MRS; in copyFromCPSR()
785 .addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc)); in copyFromCPSR()
793 ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR) in copyToCPSR()
794 : ARM::MSR; in copyToCPSR()
805 .addReg(ARM::CPSR, RegState::Implicit | RegState::Define); in copyToCPSR()
821 MIB.addReg(ARM::VPR, RegState::Implicit); in addPredicatedMveVpredNOp()
834 bool GPRDest = ARM::GPRRegClass.contains(DestReg); in copyPhysReg()
835 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); in copyPhysReg()
838 BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) in copyPhysReg()
845 bool SPRDest = ARM::SPRRegClass.contains(DestReg); in copyPhysReg()
846 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); in copyPhysReg()
850 Opc = ARM::VMOVS; in copyPhysReg()
852 Opc = ARM::VMOVRS; in copyPhysReg()
854 Opc = ARM::VMOVSR; in copyPhysReg()
855 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.hasFP64()) in copyPhysReg()
856 Opc = ARM::VMOVD; in copyPhysReg()
857 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
858 Opc = Subtarget.hasNEON() ? ARM::VORRq : ARM::MVE_VORR; in copyPhysReg()
863 if (Opc == ARM::VORRq || Opc == ARM::MVE_VORR) in copyPhysReg()
865 if (Opc == ARM::MVE_VORR) in copyPhysReg()
878 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
879 Opc = Subtarget.hasNEON() ? ARM::VORRq : ARM::MVE_VORR; in copyPhysReg()
880 BeginIdx = ARM::qsub_0; in copyPhysReg()
882 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
883 Opc = Subtarget.hasNEON() ? ARM::VORRq : ARM::MVE_VORR; in copyPhysReg()
884 BeginIdx = ARM::qsub_0; in copyPhysReg()
887 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
888 Opc = ARM::VMOVD; in copyPhysReg()
889 BeginIdx = ARM::dsub_0; in copyPhysReg()
891 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
892 Opc = ARM::VMOVD; in copyPhysReg()
893 BeginIdx = ARM::dsub_0; in copyPhysReg()
895 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
896 Opc = ARM::VMOVD; in copyPhysReg()
897 BeginIdx = ARM::dsub_0; in copyPhysReg()
899 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
900 Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr; in copyPhysReg()
901 BeginIdx = ARM::gsub_0; in copyPhysReg()
903 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
904 Opc = ARM::VMOVD; in copyPhysReg()
905 BeginIdx = ARM::dsub_0; in copyPhysReg()
908 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
909 Opc = ARM::VMOVD; in copyPhysReg()
910 BeginIdx = ARM::dsub_0; in copyPhysReg()
913 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
914 Opc = ARM::VMOVD; in copyPhysReg()
915 BeginIdx = ARM::dsub_0; in copyPhysReg()
918 } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
920 Opc = ARM::VMOVS; in copyPhysReg()
921 BeginIdx = ARM::ssub_0; in copyPhysReg()
923 } else if (SrcReg == ARM::CPSR) { in copyPhysReg()
926 } else if (DestReg == ARM::CPSR) { in copyPhysReg()
929 } else if (DestReg == ARM::VPR) { in copyPhysReg()
930 assert(ARM::GPRRegClass.contains(SrcReg)); in copyPhysReg()
931 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_P0), DestReg) in copyPhysReg()
935 } else if (SrcReg == ARM::VPR) { in copyPhysReg()
936 assert(ARM::GPRRegClass.contains(DestReg)); in copyPhysReg()
937 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_P0), DestReg) in copyPhysReg()
941 } else if (DestReg == ARM::FPSCR_NZCV) { in copyPhysReg()
942 assert(ARM::GPRRegClass.contains(SrcReg)); in copyPhysReg()
943 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_FPSCR_NZCVQC), DestReg) in copyPhysReg()
947 } else if (SrcReg == ARM::FPSCR_NZCV) { in copyPhysReg()
948 assert(ARM::GPRRegClass.contains(DestReg)); in copyPhysReg()
949 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_FPSCR_NZCVQC), DestReg) in copyPhysReg()
978 if (Opc == ARM::VORRq || Opc == ARM::MVE_VORR) { in copyPhysReg()
982 if (Opc == ARM::MVE_VORR) in copyPhysReg()
987 if (Opc == ARM::MOVr) in copyPhysReg()
1006 (MI.getOpcode() == ARM::VORRq && in isCopyInstrImpl()
1039 if (ARM::HPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1040 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRH)) in storeRegToStackSlot()
1050 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1051 BuildMI(MBB, I, DebugLoc(), get(ARM::STRi12)) in storeRegToStackSlot()
1057 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1058 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRS)) in storeRegToStackSlot()
1064 } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1065 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTR_P0_off)) in storeRegToStackSlot()
1075 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1076 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRD)) in storeRegToStackSlot()
1082 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1084 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STRD)); in storeRegToStackSlot()
1085 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
1086 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
1092 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STMIA)) in storeRegToStackSlot()
1096 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
1097 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
1103 if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) { in storeRegToStackSlot()
1106 BuildMI(MBB, I, DebugLoc(), get(ARM::VST1q64)) in storeRegToStackSlot()
1113 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMQIA)) in storeRegToStackSlot()
1119 } else if (ARM::QPRRegClass.hasSubClassEq(RC) && in storeRegToStackSlot()
1121 auto MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::MVE_VSTRWU32)); in storeRegToStackSlot()
1131 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1135 BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64TPseudo)) in storeRegToStackSlot()
1143 get(ARM::VSTMDIA)) in storeRegToStackSlot()
1147 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
1148 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
1149 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
1155 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1160 BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64QPseudo)) in storeRegToStackSlot()
1168 get(ARM::VSTMDIA)) in storeRegToStackSlot()
1172 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
1173 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
1174 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
1175 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); in storeRegToStackSlot()
1181 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1182 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMDIA)) in storeRegToStackSlot()
1186 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
1187 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
1188 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
1189 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI); in storeRegToStackSlot()
1190 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI); in storeRegToStackSlot()
1191 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI); in storeRegToStackSlot()
1192 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI); in storeRegToStackSlot()
1193 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI); in storeRegToStackSlot()
1206 case ARM::STRrs: in isStoreToStackSlot()
1207 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. in isStoreToStackSlot()
1215 case ARM::STRi12: in isStoreToStackSlot()
1216 case ARM::t2STRi12: in isStoreToStackSlot()
1217 case ARM::tSTRspi: in isStoreToStackSlot()
1218 case ARM::VSTRD: in isStoreToStackSlot()
1219 case ARM::VSTRS: in isStoreToStackSlot()
1226 case ARM::VSTR_P0_off: in isStoreToStackSlot()
1230 return ARM::P0; in isStoreToStackSlot()
1233 case ARM::VST1q64: in isStoreToStackSlot()
1234 case ARM::VST1d64TPseudo: in isStoreToStackSlot()
1235 case ARM::VST1d64QPseudo: in isStoreToStackSlot()
1241 case ARM::VSTMQIA: in isStoreToStackSlot()
1281 if (ARM::HPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1282 BuildMI(MBB, I, DL, get(ARM::VLDRH), DestReg) in loadRegFromStackSlot()
1291 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1292 BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) in loadRegFromStackSlot()
1297 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1298 BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) in loadRegFromStackSlot()
1303 } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1304 BuildMI(MBB, I, DL, get(ARM::VLDR_P0_off), DestReg) in loadRegFromStackSlot()
1313 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1314 BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) in loadRegFromStackSlot()
1319 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1323 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD)); in loadRegFromStackSlot()
1324 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1325 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1331 MIB = BuildMI(MBB, I, DL, get(ARM::LDMIA)) in loadRegFromStackSlot()
1335 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1336 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1345 if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) { in loadRegFromStackSlot()
1347 BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) in loadRegFromStackSlot()
1353 BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) in loadRegFromStackSlot()
1358 } else if (ARM::QPRRegClass.hasSubClassEq(RC) && in loadRegFromStackSlot()
1360 auto MIB = BuildMI(MBB, I, DL, get(ARM::MVE_VLDRWU32), DestReg); in loadRegFromStackSlot()
1369 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1372 BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg) in loadRegFromStackSlot()
1378 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) in loadRegFromStackSlot()
1382 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1383 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1384 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1392 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1395 BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) in loadRegFromStackSlot()
1401 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) in loadRegFromStackSlot()
1405 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1406 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1407 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1408 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1416 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1417 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA)) in loadRegFromStackSlot()
1421 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1422 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1423 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1424 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1425 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1426 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1427 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1428 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1443 case ARM::LDRrs: in isLoadFromStackSlot()
1444 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. in isLoadFromStackSlot()
1452 case ARM::LDRi12: in isLoadFromStackSlot()
1453 case ARM::t2LDRi12: in isLoadFromStackSlot()
1454 case ARM::tLDRspi: in isLoadFromStackSlot()
1455 case ARM::VLDRD: in isLoadFromStackSlot()
1456 case ARM::VLDRS: in isLoadFromStackSlot()
1463 case ARM::VLDR_P0_off: in isLoadFromStackSlot()
1467 return ARM::P0; in isLoadFromStackSlot()
1470 case ARM::VLD1q64: in isLoadFromStackSlot()
1471 case ARM::VLD1d8TPseudo: in isLoadFromStackSlot()
1472 case ARM::VLD1d16TPseudo: in isLoadFromStackSlot()
1473 case ARM::VLD1d32TPseudo: in isLoadFromStackSlot()
1474 case ARM::VLD1d64TPseudo: in isLoadFromStackSlot()
1475 case ARM::VLD1d8QPseudo: in isLoadFromStackSlot()
1476 case ARM::VLD1d16QPseudo: in isLoadFromStackSlot()
1477 case ARM::VLD1d32QPseudo: in isLoadFromStackSlot()
1478 case ARM::VLD1d64QPseudo: in isLoadFromStackSlot()
1484 case ARM::VLDMQIA: in isLoadFromStackSlot()
1521 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD in expandMEMCPY()
1522 : isThumb1 ? ARM::tLDMIA_UPD in expandMEMCPY()
1523 : ARM::LDMIA_UPD)) in expandMEMCPY()
1526 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA : ARM::LDMIA)); in expandMEMCPY()
1531 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD in expandMEMCPY()
1532 : isThumb1 ? ARM::tSTMIA_UPD in expandMEMCPY()
1533 : ARM::STMIA_UPD)) in expandMEMCPY()
1536 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA)); in expandMEMCPY()
1573 if (MI.getOpcode() == ARM::MEMCPY) { in expandPostRAPseudo()
1589 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS)) in expandPostRAPseudo()
1593 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0, in expandPostRAPseudo()
1594 &ARM::DPRRegClass); in expandPostRAPseudo()
1595 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0, in expandPostRAPseudo()
1596 &ARM::DPRRegClass); in expandPostRAPseudo()
1621 MI.setDesc(get(ARM::VMOVD)); in expandPostRAPseudo()
1702 case ARM::tLDRpci_pic: in reMaterialize()
1703 case ARM::t2LDRpci_pic: { in reMaterialize()
1724 case ARM::tLDRpci_pic: in duplicate()
1725 case ARM::t2LDRpci_pic: { in duplicate()
1745 if (Opcode == ARM::t2LDRpci || in produceSameValue()
1746 Opcode == ARM::t2LDRpci_pic || in produceSameValue()
1747 Opcode == ARM::tLDRpci || in produceSameValue()
1748 Opcode == ARM::tLDRpci_pic || in produceSameValue()
1749 Opcode == ARM::LDRLIT_ga_pcrel || in produceSameValue()
1750 Opcode == ARM::LDRLIT_ga_pcrel_ldr || in produceSameValue()
1751 Opcode == ARM::tLDRLIT_ga_pcrel || in produceSameValue()
1752 Opcode == ARM::MOV_ga_pcrel || in produceSameValue()
1753 Opcode == ARM::MOV_ga_pcrel_ldr || in produceSameValue()
1754 Opcode == ARM::t2MOV_ga_pcrel) { in produceSameValue()
1765 if (Opcode == ARM::LDRLIT_ga_pcrel || in produceSameValue()
1766 Opcode == ARM::LDRLIT_ga_pcrel_ldr || in produceSameValue()
1767 Opcode == ARM::tLDRLIT_ga_pcrel || in produceSameValue()
1768 Opcode == ARM::MOV_ga_pcrel || in produceSameValue()
1769 Opcode == ARM::MOV_ga_pcrel_ldr || in produceSameValue()
1770 Opcode == ARM::t2MOV_ga_pcrel) in produceSameValue()
1792 } else if (Opcode == ARM::PICLDR) { in produceSameValue()
1847 case ARM::LDRi12: in areLoadsFromSameBasePtr()
1848 case ARM::LDRBi12: in areLoadsFromSameBasePtr()
1849 case ARM::LDRD: in areLoadsFromSameBasePtr()
1850 case ARM::LDRH: in areLoadsFromSameBasePtr()
1851 case ARM::LDRSB: in areLoadsFromSameBasePtr()
1852 case ARM::LDRSH: in areLoadsFromSameBasePtr()
1853 case ARM::VLDRD: in areLoadsFromSameBasePtr()
1854 case ARM::VLDRS: in areLoadsFromSameBasePtr()
1855 case ARM::t2LDRi8: in areLoadsFromSameBasePtr()
1856 case ARM::t2LDRBi8: in areLoadsFromSameBasePtr()
1857 case ARM::t2LDRDi8: in areLoadsFromSameBasePtr()
1858 case ARM::t2LDRSHi8: in areLoadsFromSameBasePtr()
1859 case ARM::t2LDRi12: in areLoadsFromSameBasePtr()
1860 case ARM::t2LDRBi12: in areLoadsFromSameBasePtr()
1861 case ARM::t2LDRSHi12: in areLoadsFromSameBasePtr()
1868 case ARM::LDRi12: in areLoadsFromSameBasePtr()
1869 case ARM::LDRBi12: in areLoadsFromSameBasePtr()
1870 case ARM::LDRD: in areLoadsFromSameBasePtr()
1871 case ARM::LDRH: in areLoadsFromSameBasePtr()
1872 case ARM::LDRSB: in areLoadsFromSameBasePtr()
1873 case ARM::LDRSH: in areLoadsFromSameBasePtr()
1874 case ARM::VLDRD: in areLoadsFromSameBasePtr()
1875 case ARM::VLDRS: in areLoadsFromSameBasePtr()
1876 case ARM::t2LDRi8: in areLoadsFromSameBasePtr()
1877 case ARM::t2LDRBi8: in areLoadsFromSameBasePtr()
1878 case ARM::t2LDRSHi8: in areLoadsFromSameBasePtr()
1879 case ARM::t2LDRi12: in areLoadsFromSameBasePtr()
1880 case ARM::t2LDRBi12: in areLoadsFromSameBasePtr()
1881 case ARM::t2LDRSHi12: in areLoadsFromSameBasePtr()
1933 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 && in shouldScheduleLoadsNear()
1934 Load2->getMachineOpcode() == ARM::t2LDRBi12) || in shouldScheduleLoadsNear()
1935 (Load1->getMachineOpcode() == ARM::t2LDRBi12 && in shouldScheduleLoadsNear()
1936 Load2->getMachineOpcode() == ARM::t2LDRBi8))) in shouldScheduleLoadsNear()
1972 if (I != MBB->end() && I->getOpcode() == ARM::t2IT) in isSchedulingBoundary()
1983 if (!MI.isCall() && MI.definesRegister(ARM::SP)) in isSchedulingBoundary()
2003 if (LastMI->getOpcode() == ARM::t2Bcc) { in isProfitableToIfCvt()
2093 if (MI.getOpcode() == ARM::t2Bcc && in predictBranchSizeForIfCvt()
2135 if (Opc == ARM::B) in getMatchingCondBranchOpcode()
2136 return ARM::Bcc; in getMatchingCondBranchOpcode()
2137 if (Opc == ARM::tB) in getMatchingCondBranchOpcode()
2138 return ARM::tBcc; in getMatchingCondBranchOpcode()
2139 if (Opc == ARM::t2B) in getMatchingCondBranchOpcode()
2140 return ARM::t2Bcc; in getMatchingCondBranchOpcode()
2150 case ARM::MOVCCr: in commuteInstructionImpl()
2151 case ARM::t2MOVCCr: { in commuteInstructionImpl()
2156 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstructionImpl()
2213 assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) && in analyzeSelect()
2234 assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) && in optimizeSelect()
2309 {ARM::ADDSri, ARM::ADDri},
2310 {ARM::ADDSrr, ARM::ADDrr},
2311 {ARM::ADDSrsi, ARM::ADDrsi},
2312 {ARM::ADDSrsr, ARM::ADDrsr},
2314 {ARM::SUBSri, ARM::SUBri},
2315 {ARM::SUBSrr, ARM::SUBrr},
2316 {ARM::SUBSrsi, ARM::SUBrsi},
2317 {ARM::SUBSrsr, ARM::SUBrsr},
2319 {ARM::RSBSri, ARM::RSBri},
2320 {ARM::RSBSrsi, ARM::RSBrsi},
2321 {ARM::RSBSrsr, ARM::RSBrsr},
2323 {ARM::tADDSi3, ARM::tADDi3},
2324 {ARM::tADDSi8, ARM::tADDi8},
2325 {ARM::tADDSrr, ARM::tADDrr},
2326 {ARM::tADCS, ARM::tADC},
2328 {ARM::tSUBSi3, ARM::tSUBi3},
2329 {ARM::tSUBSi8, ARM::tSUBi8},
2330 {ARM::tSUBSrr, ARM::tSUBrr},
2331 {ARM::tSBCS, ARM::tSBC},
2332 {ARM::tRSBS, ARM::tRSB},
2333 {ARM::tLSLSri, ARM::tLSLri},
2335 {ARM::t2ADDSri, ARM::t2ADDri},
2336 {ARM::t2ADDSrr, ARM::t2ADDrr},
2337 {ARM::t2ADDSrs, ARM::t2ADDrs},
2339 {ARM::t2SUBSri, ARM::t2SUBri},
2340 {ARM::t2SUBSrr, ARM::t2SUBrr},
2341 {ARM::t2SUBSrs, ARM::t2SUBrs},
2343 {ARM::t2RSBSri, ARM::t2RSBri},
2344 {ARM::t2RSBSrs, ARM::t2RSBrs},
2362 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg) in emitARMRegPlusImmediate()
2384 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; in emitARMRegPlusImmediate()
2411 bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD || in tryFoldSPUpdateIntoPushPop()
2412 MI->getOpcode() == ARM::VLDMDIA_UPD; in tryFoldSPUpdateIntoPushPop()
2413 bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH || in tryFoldSPUpdateIntoPushPop()
2414 MI->getOpcode() == ARM::tPOP || in tryFoldSPUpdateIntoPushPop()
2415 MI->getOpcode() == ARM::tPOP_RET; in tryFoldSPUpdateIntoPushPop()
2417 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP && in tryFoldSPUpdateIntoPushPop()
2418 MI->getOperand(1).getReg() == ARM::SP)) && in tryFoldSPUpdateIntoPushPop()
2436 RegClass = &ARM::DPRRegClass; in tryFoldSPUpdateIntoPushPop()
2439 RegClass = &ARM::GPRRegClass; in tryFoldSPUpdateIntoPushPop()
2467 if (IsT1PushPop && CurRegEnc > TRI->getEncodingValue(ARM::R7)) in tryFoldSPUpdateIntoPushPop()
2526 if (Opcode == ARM::INLINEASM || Opcode == ARM::INLINEASM_BR) in rewriteARMFrameIndex()
2529 if (Opcode == ARM::ADDri) { in rewriteARMFrameIndex()
2533 MI.setDesc(TII.get(ARM::MOVr)); in rewriteARMFrameIndex()
2541 MI.setDesc(TII.get(ARM::SUBri)); in rewriteARMFrameIndex()
2679 case ARM::CMPri: in analyzeCompare()
2680 case ARM::t2CMPri: in analyzeCompare()
2681 case ARM::tCMPi8: in analyzeCompare()
2687 case ARM::CMPrr: in analyzeCompare()
2688 case ARM::t2CMPrr: in analyzeCompare()
2689 case ARM::tCMPr: in analyzeCompare()
2695 case ARM::TSTri: in analyzeCompare()
2696 case ARM::t2TSTri: in analyzeCompare()
2714 case ARM::ANDri: in isSuitableForMask()
2715 case ARM::t2ANDri: in isSuitableForMask()
2749 if ((CmpI->getOpcode() == ARM::CMPrr || CmpI->getOpcode() == ARM::t2CMPrr) && in isRedundantFlagInstr()
2750 (OI->getOpcode() == ARM::SUBrr || OI->getOpcode() == ARM::t2SUBrr) && in isRedundantFlagInstr()
2759 if (CmpI->getOpcode() == ARM::tCMPr && OI->getOpcode() == ARM::tSUBrr && in isRedundantFlagInstr()
2768 if ((CmpI->getOpcode() == ARM::CMPri || CmpI->getOpcode() == ARM::t2CMPri) && in isRedundantFlagInstr()
2769 (OI->getOpcode() == ARM::SUBri || OI->getOpcode() == ARM::t2SUBri) && in isRedundantFlagInstr()
2776 if (CmpI->getOpcode() == ARM::tCMPi8 && in isRedundantFlagInstr()
2777 (OI->getOpcode() == ARM::tSUBi8 || OI->getOpcode() == ARM::tSUBi3) && in isRedundantFlagInstr()
2784 if ((CmpI->getOpcode() == ARM::CMPrr || CmpI->getOpcode() == ARM::t2CMPrr) && in isRedundantFlagInstr()
2785 (OI->getOpcode() == ARM::ADDrr || OI->getOpcode() == ARM::t2ADDrr || in isRedundantFlagInstr()
2786 OI->getOpcode() == ARM::ADDri || OI->getOpcode() == ARM::t2ADDri) && in isRedundantFlagInstr()
2794 if (CmpI->getOpcode() == ARM::tCMPr && in isRedundantFlagInstr()
2795 (OI->getOpcode() == ARM::tADDi3 || OI->getOpcode() == ARM::tADDi8 || in isRedundantFlagInstr()
2796 OI->getOpcode() == ARM::tADDrr) && in isRedundantFlagInstr()
2809 case ARM::tLSLri: in isOptimizeCompareCandidate()
2810 case ARM::tLSRri: in isOptimizeCompareCandidate()
2811 case ARM::tLSLrr: in isOptimizeCompareCandidate()
2812 case ARM::tLSRrr: in isOptimizeCompareCandidate()
2813 case ARM::tSUBrr: in isOptimizeCompareCandidate()
2814 case ARM::tADDrr: in isOptimizeCompareCandidate()
2815 case ARM::tADDi3: in isOptimizeCompareCandidate()
2816 case ARM::tADDi8: in isOptimizeCompareCandidate()
2817 case ARM::tSUBi3: in isOptimizeCompareCandidate()
2818 case ARM::tSUBi8: in isOptimizeCompareCandidate()
2819 case ARM::tMUL: in isOptimizeCompareCandidate()
2820 case ARM::tADC: in isOptimizeCompareCandidate()
2821 case ARM::tSBC: in isOptimizeCompareCandidate()
2822 case ARM::tRSB: in isOptimizeCompareCandidate()
2823 case ARM::tAND: in isOptimizeCompareCandidate()
2824 case ARM::tORR: in isOptimizeCompareCandidate()
2825 case ARM::tEOR: in isOptimizeCompareCandidate()
2826 case ARM::tBIC: in isOptimizeCompareCandidate()
2827 case ARM::tMVN: in isOptimizeCompareCandidate()
2828 case ARM::tASRri: in isOptimizeCompareCandidate()
2829 case ARM::tASRrr: in isOptimizeCompareCandidate()
2830 case ARM::tROR: in isOptimizeCompareCandidate()
2833 case ARM::RSBrr: in isOptimizeCompareCandidate()
2834 case ARM::RSBri: in isOptimizeCompareCandidate()
2835 case ARM::RSCrr: in isOptimizeCompareCandidate()
2836 case ARM::RSCri: in isOptimizeCompareCandidate()
2837 case ARM::ADDrr: in isOptimizeCompareCandidate()
2838 case ARM::ADDri: in isOptimizeCompareCandidate()
2839 case ARM::ADCrr: in isOptimizeCompareCandidate()
2840 case ARM::ADCri: in isOptimizeCompareCandidate()
2841 case ARM::SUBrr: in isOptimizeCompareCandidate()
2842 case ARM::SUBri: in isOptimizeCompareCandidate()
2843 case ARM::SBCrr: in isOptimizeCompareCandidate()
2844 case ARM::SBCri: in isOptimizeCompareCandidate()
2845 case ARM::t2RSBri: in isOptimizeCompareCandidate()
2846 case ARM::t2ADDrr: in isOptimizeCompareCandidate()
2847 case ARM::t2ADDri: in isOptimizeCompareCandidate()
2848 case ARM::t2ADCrr: in isOptimizeCompareCandidate()
2849 case ARM::t2ADCri: in isOptimizeCompareCandidate()
2850 case ARM::t2SUBrr: in isOptimizeCompareCandidate()
2851 case ARM::t2SUBri: in isOptimizeCompareCandidate()
2852 case ARM::t2SBCrr: in isOptimizeCompareCandidate()
2853 case ARM::t2SBCri: in isOptimizeCompareCandidate()
2854 case ARM::ANDrr: in isOptimizeCompareCandidate()
2855 case ARM::ANDri: in isOptimizeCompareCandidate()
2856 case ARM::t2ANDrr: in isOptimizeCompareCandidate()
2857 case ARM::t2ANDri: in isOptimizeCompareCandidate()
2858 case ARM::ORRrr: in isOptimizeCompareCandidate()
2859 case ARM::ORRri: in isOptimizeCompareCandidate()
2860 case ARM::t2ORRrr: in isOptimizeCompareCandidate()
2861 case ARM::t2ORRri: in isOptimizeCompareCandidate()
2862 case ARM::EORrr: in isOptimizeCompareCandidate()
2863 case ARM::EORri: in isOptimizeCompareCandidate()
2864 case ARM::t2EORrr: in isOptimizeCompareCandidate()
2865 case ARM::t2EORri: in isOptimizeCompareCandidate()
2866 case ARM::t2LSRri: in isOptimizeCompareCandidate()
2867 case ARM::t2LSRrr: in isOptimizeCompareCandidate()
2868 case ARM::t2LSLri: in isOptimizeCompareCandidate()
2869 case ARM::t2LSLrr: in isOptimizeCompareCandidate()
2929 if (CmpInstr.getOpcode() == ARM::CMPri || in optimizeCompareInstr()
2930 CmpInstr.getOpcode() == ARM::t2CMPri || in optimizeCompareInstr()
2931 CmpInstr.getOpcode() == ARM::tCMPi8) in optimizeCompareInstr()
2956 if (I != E && !MI->readsRegister(ARM::CPSR, TRI)) { in optimizeCompareInstr()
2959 if (I->getOpcode() != ARM::tMOVi8) { in optimizeCompareInstr()
2991 if (Instr.modifiesRegister(ARM::CPSR, TRI) || in optimizeCompareInstr()
2992 Instr.readsRegister(ARM::CPSR, TRI)) in optimizeCompareInstr()
3037 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) { in optimizeCompareInstr()
3041 if (!MO.isReg() || MO.getReg() != ARM::CPSR) in optimizeCompareInstr()
3055 case ARM::VSELEQD: in optimizeCompareInstr()
3056 case ARM::VSELEQS: in optimizeCompareInstr()
3057 case ARM::VSELEQH: in optimizeCompareInstr()
3060 case ARM::VSELGTD: in optimizeCompareInstr()
3061 case ARM::VSELGTS: in optimizeCompareInstr()
3062 case ARM::VSELGTH: in optimizeCompareInstr()
3065 case ARM::VSELGED: in optimizeCompareInstr()
3066 case ARM::VSELGES: in optimizeCompareInstr()
3067 case ARM::VSELGEH: in optimizeCompareInstr()
3070 case ARM::VSELVSD: in optimizeCompareInstr()
3071 case ARM::VSELVSS: in optimizeCompareInstr()
3072 case ARM::VSELVSH: in optimizeCompareInstr()
3086 bool IsSub = Opc == ARM::SUBrr || Opc == ARM::t2SUBrr || in optimizeCompareInstr()
3087 Opc == ARM::SUBri || Opc == ARM::t2SUBri || in optimizeCompareInstr()
3088 Opc == ARM::tSUBrr || Opc == ARM::tSUBi3 || in optimizeCompareInstr()
3089 Opc == ARM::tSUBi8; in optimizeCompareInstr()
3090 unsigned OpI = Opc != ARM::tSUBrr ? 1 : 2; in optimizeCompareInstr()
3137 if ((*SI)->isLiveIn(ARM::CPSR)) in optimizeCompareInstr()
3144 MI->getOperand(5).setReg(ARM::CPSR); in optimizeCompareInstr()
3156 MI->clearRegisterDeads(ARM::CPSR); in optimizeCompareInstr()
3184 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm) in FoldImmediate()
3197 if (MO.getReg() == ARM::CPSR && !MO.isDead()) in FoldImmediate()
3206 if (UseMI.getOperand(NumOps - 1).getReg() == ARM::CPSR) in FoldImmediate()
3219 case ARM::SUBrr: in FoldImmediate()
3220 case ARM::ADDrr: in FoldImmediate()
3221 case ARM::ORRrr: in FoldImmediate()
3222 case ARM::EORrr: in FoldImmediate()
3223 case ARM::t2SUBrr: in FoldImmediate()
3224 case ARM::t2ADDrr: in FoldImmediate()
3225 case ARM::t2ORRrr: in FoldImmediate()
3226 case ARM::t2EORrr: { in FoldImmediate()
3230 case ARM::ADDrr: in FoldImmediate()
3231 case ARM::SUBrr: in FoldImmediate()
3232 if (UseOpc == ARM::SUBrr && Commute) in FoldImmediate()
3238 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::ADDri : ARM::SUBri; in FoldImmediate()
3241 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::SUBri : ARM::ADDri; in FoldImmediate()
3247 case ARM::ORRrr: in FoldImmediate()
3248 case ARM::EORrr: in FoldImmediate()
3255 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break; in FoldImmediate()
3256 case ARM::EORrr: NewUseOpc = ARM::EORri; break; in FoldImmediate()
3259 case ARM::t2ADDrr: in FoldImmediate()
3260 case ARM::t2SUBrr: { in FoldImmediate()
3261 if (UseOpc == ARM::t2SUBrr && Commute) in FoldImmediate()
3266 const bool ToSP = DefMI.getOperand(0).getReg() == ARM::SP; in FoldImmediate()
3267 const unsigned t2ADD = ToSP ? ARM::t2ADDspImm : ARM::t2ADDri; in FoldImmediate()
3268 const unsigned t2SUB = ToSP ? ARM::t2SUBspImm : ARM::t2SUBri; in FoldImmediate()
3270 NewUseOpc = UseOpc == ARM::t2ADDrr ? t2ADD : t2SUB; in FoldImmediate()
3273 NewUseOpc = UseOpc == ARM::t2ADDrr ? t2SUB : t2ADD; in FoldImmediate()
3280 case ARM::t2ORRrr: in FoldImmediate()
3281 case ARM::t2EORrr: in FoldImmediate()
3288 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break; in FoldImmediate()
3289 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break; in FoldImmediate()
3318 case ARM::t2ADDspImm: in FoldImmediate()
3319 case ARM::t2SUBspImm: in FoldImmediate()
3320 case ARM::t2ADDri: in FoldImmediate()
3321 case ARM::t2SUBri: in FoldImmediate()
3337 case ARM::LDRrs: in getNumMicroOpsSwiftLdSt()
3338 case ARM::LDRBrs: in getNumMicroOpsSwiftLdSt()
3339 case ARM::STRrs: in getNumMicroOpsSwiftLdSt()
3340 case ARM::STRBrs: { in getNumMicroOpsSwiftLdSt()
3352 case ARM::LDRH: in getNumMicroOpsSwiftLdSt()
3353 case ARM::STRH: { in getNumMicroOpsSwiftLdSt()
3368 case ARM::LDRSB: in getNumMicroOpsSwiftLdSt()
3369 case ARM::LDRSH: in getNumMicroOpsSwiftLdSt()
3372 case ARM::LDRSB_POST: in getNumMicroOpsSwiftLdSt()
3373 case ARM::LDRSH_POST: { in getNumMicroOpsSwiftLdSt()
3379 case ARM::LDR_PRE_REG: in getNumMicroOpsSwiftLdSt()
3380 case ARM::LDRB_PRE_REG: { in getNumMicroOpsSwiftLdSt()
3396 case ARM::STR_PRE_REG: in getNumMicroOpsSwiftLdSt()
3397 case ARM::STRB_PRE_REG: { in getNumMicroOpsSwiftLdSt()
3409 case ARM::LDRH_PRE: in getNumMicroOpsSwiftLdSt()
3410 case ARM::STRH_PRE: { in getNumMicroOpsSwiftLdSt()
3420 case ARM::LDR_POST_REG: in getNumMicroOpsSwiftLdSt()
3421 case ARM::LDRB_POST_REG: in getNumMicroOpsSwiftLdSt()
3422 case ARM::LDRH_POST: { in getNumMicroOpsSwiftLdSt()
3428 case ARM::LDR_PRE_IMM: in getNumMicroOpsSwiftLdSt()
3429 case ARM::LDRB_PRE_IMM: in getNumMicroOpsSwiftLdSt()
3430 case ARM::LDR_POST_IMM: in getNumMicroOpsSwiftLdSt()
3431 case ARM::LDRB_POST_IMM: in getNumMicroOpsSwiftLdSt()
3432 case ARM::STRB_POST_IMM: in getNumMicroOpsSwiftLdSt()
3433 case ARM::STRB_POST_REG: in getNumMicroOpsSwiftLdSt()
3434 case ARM::STRB_PRE_IMM: in getNumMicroOpsSwiftLdSt()
3435 case ARM::STRH_POST: in getNumMicroOpsSwiftLdSt()
3436 case ARM::STR_POST_IMM: in getNumMicroOpsSwiftLdSt()
3437 case ARM::STR_POST_REG: in getNumMicroOpsSwiftLdSt()
3438 case ARM::STR_PRE_IMM: in getNumMicroOpsSwiftLdSt()
3441 case ARM::LDRSB_PRE: in getNumMicroOpsSwiftLdSt()
3442 case ARM::LDRSH_PRE: { in getNumMicroOpsSwiftLdSt()
3460 case ARM::LDRD: { in getNumMicroOpsSwiftLdSt()
3470 case ARM::STRD: { in getNumMicroOpsSwiftLdSt()
3478 case ARM::LDRD_POST: in getNumMicroOpsSwiftLdSt()
3479 case ARM::t2LDRD_POST: in getNumMicroOpsSwiftLdSt()
3482 case ARM::STRD_POST: in getNumMicroOpsSwiftLdSt()
3483 case ARM::t2STRD_POST: in getNumMicroOpsSwiftLdSt()
3486 case ARM::LDRD_PRE: { in getNumMicroOpsSwiftLdSt()
3496 case ARM::t2LDRD_PRE: { in getNumMicroOpsSwiftLdSt()
3502 case ARM::STRD_PRE: { in getNumMicroOpsSwiftLdSt()
3510 case ARM::t2STRD_PRE: in getNumMicroOpsSwiftLdSt()
3513 case ARM::t2LDR_POST: in getNumMicroOpsSwiftLdSt()
3514 case ARM::t2LDRB_POST: in getNumMicroOpsSwiftLdSt()
3515 case ARM::t2LDRB_PRE: in getNumMicroOpsSwiftLdSt()
3516 case ARM::t2LDRSBi12: in getNumMicroOpsSwiftLdSt()
3517 case ARM::t2LDRSBi8: in getNumMicroOpsSwiftLdSt()
3518 case ARM::t2LDRSBpci: in getNumMicroOpsSwiftLdSt()
3519 case ARM::t2LDRSBs: in getNumMicroOpsSwiftLdSt()
3520 case ARM::t2LDRH_POST: in getNumMicroOpsSwiftLdSt()
3521 case ARM::t2LDRH_PRE: in getNumMicroOpsSwiftLdSt()
3522 case ARM::t2LDRSBT: in getNumMicroOpsSwiftLdSt()
3523 case ARM::t2LDRSB_POST: in getNumMicroOpsSwiftLdSt()
3524 case ARM::t2LDRSB_PRE: in getNumMicroOpsSwiftLdSt()
3525 case ARM::t2LDRSH_POST: in getNumMicroOpsSwiftLdSt()
3526 case ARM::t2LDRSH_PRE: in getNumMicroOpsSwiftLdSt()
3527 case ARM::t2LDRSHi12: in getNumMicroOpsSwiftLdSt()
3528 case ARM::t2LDRSHi8: in getNumMicroOpsSwiftLdSt()
3529 case ARM::t2LDRSHpci: in getNumMicroOpsSwiftLdSt()
3530 case ARM::t2LDRSHs: in getNumMicroOpsSwiftLdSt()
3533 case ARM::t2LDRDi8: { in getNumMicroOpsSwiftLdSt()
3539 case ARM::t2STRB_POST: in getNumMicroOpsSwiftLdSt()
3540 case ARM::t2STRB_PRE: in getNumMicroOpsSwiftLdSt()
3541 case ARM::t2STRBs: in getNumMicroOpsSwiftLdSt()
3542 case ARM::t2STRDi8: in getNumMicroOpsSwiftLdSt()
3543 case ARM::t2STRH_POST: in getNumMicroOpsSwiftLdSt()
3544 case ARM::t2STRH_PRE: in getNumMicroOpsSwiftLdSt()
3545 case ARM::t2STRHs: in getNumMicroOpsSwiftLdSt()
3546 case ARM::t2STR_POST: in getNumMicroOpsSwiftLdSt()
3547 case ARM::t2STR_PRE: in getNumMicroOpsSwiftLdSt()
3548 case ARM::t2STRs: in getNumMicroOpsSwiftLdSt()
3596 case ARM::VLDMDIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3597 case ARM::VLDMDDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3598 case ARM::VLDMSIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3599 case ARM::VLDMSDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3600 case ARM::VSTMDIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3601 case ARM::VSTMDDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3602 case ARM::VSTMSIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3603 case ARM::VSTMSDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3604 case ARM::LDMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3605 case ARM::LDMDA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3606 case ARM::LDMDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3607 case ARM::LDMIB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3608 case ARM::STMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3609 case ARM::STMDA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3610 case ARM::STMDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3611 case ARM::STMIB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3612 case ARM::tLDMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3613 case ARM::tSTMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3614 case ARM::t2LDMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3615 case ARM::t2LDMDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3616 case ARM::t2STMIA_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3617 case ARM::t2STMDB_UPD: in getNumMicroOpsSingleIssuePlusExtras()
3620 case ARM::LDMIA_RET: in getNumMicroOpsSingleIssuePlusExtras()
3621 case ARM::tPOP_RET: in getNumMicroOpsSingleIssuePlusExtras()
3622 case ARM::t2LDMIA_RET: in getNumMicroOpsSingleIssuePlusExtras()
3648 case ARM::VLDMQIA: in getNumMicroOps()
3649 case ARM::VSTMQIA: in getNumMicroOps()
3662 case ARM::VLDMDIA: in getNumMicroOps()
3663 case ARM::VLDMDIA_UPD: in getNumMicroOps()
3664 case ARM::VLDMDDB_UPD: in getNumMicroOps()
3665 case ARM::VLDMSIA: in getNumMicroOps()
3666 case ARM::VLDMSIA_UPD: in getNumMicroOps()
3667 case ARM::VLDMSDB_UPD: in getNumMicroOps()
3668 case ARM::VSTMDIA: in getNumMicroOps()
3669 case ARM::VSTMDIA_UPD: in getNumMicroOps()
3670 case ARM::VSTMDDB_UPD: in getNumMicroOps()
3671 case ARM::VSTMSIA: in getNumMicroOps()
3672 case ARM::VSTMSIA_UPD: in getNumMicroOps()
3673 case ARM::VSTMSDB_UPD: { in getNumMicroOps()
3678 case ARM::LDMIA_RET: in getNumMicroOps()
3679 case ARM::LDMIA: in getNumMicroOps()
3680 case ARM::LDMDA: in getNumMicroOps()
3681 case ARM::LDMDB: in getNumMicroOps()
3682 case ARM::LDMIB: in getNumMicroOps()
3683 case ARM::LDMIA_UPD: in getNumMicroOps()
3684 case ARM::LDMDA_UPD: in getNumMicroOps()
3685 case ARM::LDMDB_UPD: in getNumMicroOps()
3686 case ARM::LDMIB_UPD: in getNumMicroOps()
3687 case ARM::STMIA: in getNumMicroOps()
3688 case ARM::STMDA: in getNumMicroOps()
3689 case ARM::STMDB: in getNumMicroOps()
3690 case ARM::STMIB: in getNumMicroOps()
3691 case ARM::STMIA_UPD: in getNumMicroOps()
3692 case ARM::STMDA_UPD: in getNumMicroOps()
3693 case ARM::STMDB_UPD: in getNumMicroOps()
3694 case ARM::STMIB_UPD: in getNumMicroOps()
3695 case ARM::tLDMIA: in getNumMicroOps()
3696 case ARM::tLDMIA_UPD: in getNumMicroOps()
3697 case ARM::tSTMIA_UPD: in getNumMicroOps()
3698 case ARM::tPOP_RET: in getNumMicroOps()
3699 case ARM::tPOP: in getNumMicroOps()
3700 case ARM::tPUSH: in getNumMicroOps()
3701 case ARM::t2LDMIA_RET: in getNumMicroOps()
3702 case ARM::t2LDMIA: in getNumMicroOps()
3703 case ARM::t2LDMDB: in getNumMicroOps()
3704 case ARM::t2LDMIA_UPD: in getNumMicroOps()
3705 case ARM::t2LDMDB_UPD: in getNumMicroOps()
3706 case ARM::t2STMIA: in getNumMicroOps()
3707 case ARM::t2STMDB: in getNumMicroOps()
3708 case ARM::t2STMIA_UPD: in getNumMicroOps()
3709 case ARM::t2STMDB_UPD: { in getNumMicroOps()
3764 case ARM::VLDMSIA: in getVLDMDefCycle()
3765 case ARM::VLDMSIA_UPD: in getVLDMDefCycle()
3766 case ARM::VLDMSDB_UPD: in getVLDMDefCycle()
3855 case ARM::VSTMSIA: in getVSTMUseCycle()
3856 case ARM::VSTMSIA_UPD: in getVSTMUseCycle()
3857 case ARM::VSTMSDB_UPD: in getVSTMUseCycle()
3925 case ARM::VLDMDIA: in getOperandLatency()
3926 case ARM::VLDMDIA_UPD: in getOperandLatency()
3927 case ARM::VLDMDDB_UPD: in getOperandLatency()
3928 case ARM::VLDMSIA: in getOperandLatency()
3929 case ARM::VLDMSIA_UPD: in getOperandLatency()
3930 case ARM::VLDMSDB_UPD: in getOperandLatency()
3934 case ARM::LDMIA_RET: in getOperandLatency()
3935 case ARM::LDMIA: in getOperandLatency()
3936 case ARM::LDMDA: in getOperandLatency()
3937 case ARM::LDMDB: in getOperandLatency()
3938 case ARM::LDMIB: in getOperandLatency()
3939 case ARM::LDMIA_UPD: in getOperandLatency()
3940 case ARM::LDMDA_UPD: in getOperandLatency()
3941 case ARM::LDMDB_UPD: in getOperandLatency()
3942 case ARM::LDMIB_UPD: in getOperandLatency()
3943 case ARM::tLDMIA: in getOperandLatency()
3944 case ARM::tLDMIA_UPD: in getOperandLatency()
3945 case ARM::tPUSH: in getOperandLatency()
3946 case ARM::t2LDMIA_RET: in getOperandLatency()
3947 case ARM::t2LDMIA: in getOperandLatency()
3948 case ARM::t2LDMDB: in getOperandLatency()
3949 case ARM::t2LDMIA_UPD: in getOperandLatency()
3950 case ARM::t2LDMDB_UPD: in getOperandLatency()
3966 case ARM::VSTMDIA: in getOperandLatency()
3967 case ARM::VSTMDIA_UPD: in getOperandLatency()
3968 case ARM::VSTMDDB_UPD: in getOperandLatency()
3969 case ARM::VSTMSIA: in getOperandLatency()
3970 case ARM::VSTMSIA_UPD: in getOperandLatency()
3971 case ARM::VSTMSDB_UPD: in getOperandLatency()
3975 case ARM::STMIA: in getOperandLatency()
3976 case ARM::STMDA: in getOperandLatency()
3977 case ARM::STMDB: in getOperandLatency()
3978 case ARM::STMIB: in getOperandLatency()
3979 case ARM::STMIA_UPD: in getOperandLatency()
3980 case ARM::STMDA_UPD: in getOperandLatency()
3981 case ARM::STMDB_UPD: in getOperandLatency()
3982 case ARM::STMIB_UPD: in getOperandLatency()
3983 case ARM::tSTMIA_UPD: in getOperandLatency()
3984 case ARM::tPOP_RET: in getOperandLatency()
3985 case ARM::tPOP: in getOperandLatency()
3986 case ARM::t2STMIA: in getOperandLatency()
3987 case ARM::t2STMDB: in getOperandLatency()
3988 case ARM::t2STMIA_UPD: in getOperandLatency()
3989 case ARM::t2STMDB_UPD: in getOperandLatency()
4053 if (II->getOpcode() != ARM::t2IT) in getBundledUseMI()
4079 case ARM::LDRrs: in adjustDefLatency()
4080 case ARM::LDRBrs: { in adjustDefLatency()
4088 case ARM::t2LDRs: in adjustDefLatency()
4089 case ARM::t2LDRBs: in adjustDefLatency()
4090 case ARM::t2LDRHs: in adjustDefLatency()
4091 case ARM::t2LDRSHs: { in adjustDefLatency()
4104 case ARM::LDRrs: in adjustDefLatency()
4105 case ARM::LDRBrs: { in adjustDefLatency()
4119 case ARM::t2LDRs: in adjustDefLatency()
4120 case ARM::t2LDRBs: in adjustDefLatency()
4121 case ARM::t2LDRHs: in adjustDefLatency()
4122 case ARM::t2LDRSHs: { in adjustDefLatency()
4135 case ARM::VLD1q8: in adjustDefLatency()
4136 case ARM::VLD1q16: in adjustDefLatency()
4137 case ARM::VLD1q32: in adjustDefLatency()
4138 case ARM::VLD1q64: in adjustDefLatency()
4139 case ARM::VLD1q8wb_fixed: in adjustDefLatency()
4140 case ARM::VLD1q16wb_fixed: in adjustDefLatency()
4141 case ARM::VLD1q32wb_fixed: in adjustDefLatency()
4142 case ARM::VLD1q64wb_fixed: in adjustDefLatency()
4143 case ARM::VLD1q8wb_register: in adjustDefLatency()
4144 case ARM::VLD1q16wb_register: in adjustDefLatency()
4145 case ARM::VLD1q32wb_register: in adjustDefLatency()
4146 case ARM::VLD1q64wb_register: in adjustDefLatency()
4147 case ARM::VLD2d8: in adjustDefLatency()
4148 case ARM::VLD2d16: in adjustDefLatency()
4149 case ARM::VLD2d32: in adjustDefLatency()
4150 case ARM::VLD2q8: in adjustDefLatency()
4151 case ARM::VLD2q16: in adjustDefLatency()
4152 case ARM::VLD2q32: in adjustDefLatency()
4153 case ARM::VLD2d8wb_fixed: in adjustDefLatency()
4154 case ARM::VLD2d16wb_fixed: in adjustDefLatency()
4155 case ARM::VLD2d32wb_fixed: in adjustDefLatency()
4156 case ARM::VLD2q8wb_fixed: in adjustDefLatency()
4157 case ARM::VLD2q16wb_fixed: in adjustDefLatency()
4158 case ARM::VLD2q32wb_fixed: in adjustDefLatency()
4159 case ARM::VLD2d8wb_register: in adjustDefLatency()
4160 case ARM::VLD2d16wb_register: in adjustDefLatency()
4161 case ARM::VLD2d32wb_register: in adjustDefLatency()
4162 case ARM::VLD2q8wb_register: in adjustDefLatency()
4163 case ARM::VLD2q16wb_register: in adjustDefLatency()
4164 case ARM::VLD2q32wb_register: in adjustDefLatency()
4165 case ARM::VLD3d8: in adjustDefLatency()
4166 case ARM::VLD3d16: in adjustDefLatency()
4167 case ARM::VLD3d32: in adjustDefLatency()
4168 case ARM::VLD1d64T: in adjustDefLatency()
4169 case ARM::VLD3d8_UPD: in adjustDefLatency()
4170 case ARM::VLD3d16_UPD: in adjustDefLatency()
4171 case ARM::VLD3d32_UPD: in adjustDefLatency()
4172 case ARM::VLD1d64Twb_fixed: in adjustDefLatency()
4173 case ARM::VLD1d64Twb_register: in adjustDefLatency()
4174 case ARM::VLD3q8_UPD: in adjustDefLatency()
4175 case ARM::VLD3q16_UPD: in adjustDefLatency()
4176 case ARM::VLD3q32_UPD: in adjustDefLatency()
4177 case ARM::VLD4d8: in adjustDefLatency()
4178 case ARM::VLD4d16: in adjustDefLatency()
4179 case ARM::VLD4d32: in adjustDefLatency()
4180 case ARM::VLD1d64Q: in adjustDefLatency()
4181 case ARM::VLD4d8_UPD: in adjustDefLatency()
4182 case ARM::VLD4d16_UPD: in adjustDefLatency()
4183 case ARM::VLD4d32_UPD: in adjustDefLatency()
4184 case ARM::VLD1d64Qwb_fixed: in adjustDefLatency()
4185 case ARM::VLD1d64Qwb_register: in adjustDefLatency()
4186 case ARM::VLD4q8_UPD: in adjustDefLatency()
4187 case ARM::VLD4q16_UPD: in adjustDefLatency()
4188 case ARM::VLD4q32_UPD: in adjustDefLatency()
4189 case ARM::VLD1DUPq8: in adjustDefLatency()
4190 case ARM::VLD1DUPq16: in adjustDefLatency()
4191 case ARM::VLD1DUPq32: in adjustDefLatency()
4192 case ARM::VLD1DUPq8wb_fixed: in adjustDefLatency()
4193 case ARM::VLD1DUPq16wb_fixed: in adjustDefLatency()
4194 case ARM::VLD1DUPq32wb_fixed: in adjustDefLatency()
4195 case ARM::VLD1DUPq8wb_register: in adjustDefLatency()
4196 case ARM::VLD1DUPq16wb_register: in adjustDefLatency()
4197 case ARM::VLD1DUPq32wb_register: in adjustDefLatency()
4198 case ARM::VLD2DUPd8: in adjustDefLatency()
4199 case ARM::VLD2DUPd16: in adjustDefLatency()
4200 case ARM::VLD2DUPd32: in adjustDefLatency()
4201 case ARM::VLD2DUPd8wb_fixed: in adjustDefLatency()
4202 case ARM::VLD2DUPd16wb_fixed: in adjustDefLatency()
4203 case ARM::VLD2DUPd32wb_fixed: in adjustDefLatency()
4204 case ARM::VLD2DUPd8wb_register: in adjustDefLatency()
4205 case ARM::VLD2DUPd16wb_register: in adjustDefLatency()
4206 case ARM::VLD2DUPd32wb_register: in adjustDefLatency()
4207 case ARM::VLD4DUPd8: in adjustDefLatency()
4208 case ARM::VLD4DUPd16: in adjustDefLatency()
4209 case ARM::VLD4DUPd32: in adjustDefLatency()
4210 case ARM::VLD4DUPd8_UPD: in adjustDefLatency()
4211 case ARM::VLD4DUPd16_UPD: in adjustDefLatency()
4212 case ARM::VLD4DUPd32_UPD: in adjustDefLatency()
4213 case ARM::VLD1LNd8: in adjustDefLatency()
4214 case ARM::VLD1LNd16: in adjustDefLatency()
4215 case ARM::VLD1LNd32: in adjustDefLatency()
4216 case ARM::VLD1LNd8_UPD: in adjustDefLatency()
4217 case ARM::VLD1LNd16_UPD: in adjustDefLatency()
4218 case ARM::VLD1LNd32_UPD: in adjustDefLatency()
4219 case ARM::VLD2LNd8: in adjustDefLatency()
4220 case ARM::VLD2LNd16: in adjustDefLatency()
4221 case ARM::VLD2LNd32: in adjustDefLatency()
4222 case ARM::VLD2LNq16: in adjustDefLatency()
4223 case ARM::VLD2LNq32: in adjustDefLatency()
4224 case ARM::VLD2LNd8_UPD: in adjustDefLatency()
4225 case ARM::VLD2LNd16_UPD: in adjustDefLatency()
4226 case ARM::VLD2LNd32_UPD: in adjustDefLatency()
4227 case ARM::VLD2LNq16_UPD: in adjustDefLatency()
4228 case ARM::VLD2LNq32_UPD: in adjustDefLatency()
4229 case ARM::VLD4LNd8: in adjustDefLatency()
4230 case ARM::VLD4LNd16: in adjustDefLatency()
4231 case ARM::VLD4LNd32: in adjustDefLatency()
4232 case ARM::VLD4LNq16: in adjustDefLatency()
4233 case ARM::VLD4LNq32: in adjustDefLatency()
4234 case ARM::VLD4LNd8_UPD: in adjustDefLatency()
4235 case ARM::VLD4LNd16_UPD: in adjustDefLatency()
4236 case ARM::VLD4LNd32_UPD: in adjustDefLatency()
4237 case ARM::VLD4LNq16_UPD: in adjustDefLatency()
4238 case ARM::VLD4LNq32_UPD: in adjustDefLatency()
4289 if (Reg == ARM::CPSR) { in getOperandLatencyImpl()
4290 if (DefMI.getOpcode() == ARM::FMSTAT) { in getOperandLatencyImpl()
4383 case ARM::LDRrs: in getOperandLatency()
4384 case ARM::LDRBrs: { in getOperandLatency()
4393 case ARM::t2LDRs: in getOperandLatency()
4394 case ARM::t2LDRBs: in getOperandLatency()
4395 case ARM::t2LDRHs: in getOperandLatency()
4396 case ARM::t2LDRSHs: { in getOperandLatency()
4410 case ARM::LDRrs: in getOperandLatency()
4411 case ARM::LDRBrs: { in getOperandLatency()
4423 case ARM::t2LDRs: in getOperandLatency()
4424 case ARM::t2LDRBs: in getOperandLatency()
4425 case ARM::t2LDRHs: in getOperandLatency()
4426 case ARM::t2LDRSHs: in getOperandLatency()
4436 case ARM::VLD1q8: in getOperandLatency()
4437 case ARM::VLD1q16: in getOperandLatency()
4438 case ARM::VLD1q32: in getOperandLatency()
4439 case ARM::VLD1q64: in getOperandLatency()
4440 case ARM::VLD1q8wb_register: in getOperandLatency()
4441 case ARM::VLD1q16wb_register: in getOperandLatency()
4442 case ARM::VLD1q32wb_register: in getOperandLatency()
4443 case ARM::VLD1q64wb_register: in getOperandLatency()
4444 case ARM::VLD1q8wb_fixed: in getOperandLatency()
4445 case ARM::VLD1q16wb_fixed: in getOperandLatency()
4446 case ARM::VLD1q32wb_fixed: in getOperandLatency()
4447 case ARM::VLD1q64wb_fixed: in getOperandLatency()
4448 case ARM::VLD2d8: in getOperandLatency()
4449 case ARM::VLD2d16: in getOperandLatency()
4450 case ARM::VLD2d32: in getOperandLatency()
4451 case ARM::VLD2q8Pseudo: in getOperandLatency()
4452 case ARM::VLD2q16Pseudo: in getOperandLatency()
4453 case ARM::VLD2q32Pseudo: in getOperandLatency()
4454 case ARM::VLD2d8wb_fixed: in getOperandLatency()
4455 case ARM::VLD2d16wb_fixed: in getOperandLatency()
4456 case ARM::VLD2d32wb_fixed: in getOperandLatency()
4457 case ARM::VLD2q8PseudoWB_fixed: in getOperandLatency()
4458 case ARM::VLD2q16PseudoWB_fixed: in getOperandLatency()
4459 case ARM::VLD2q32PseudoWB_fixed: in getOperandLatency()
4460 case ARM::VLD2d8wb_register: in getOperandLatency()
4461 case ARM::VLD2d16wb_register: in getOperandLatency()
4462 case ARM::VLD2d32wb_register: in getOperandLatency()
4463 case ARM::VLD2q8PseudoWB_register: in getOperandLatency()
4464 case ARM::VLD2q16PseudoWB_register: in getOperandLatency()
4465 case ARM::VLD2q32PseudoWB_register: in getOperandLatency()
4466 case ARM::VLD3d8Pseudo: in getOperandLatency()
4467 case ARM::VLD3d16Pseudo: in getOperandLatency()
4468 case ARM::VLD3d32Pseudo: in getOperandLatency()
4469 case ARM::VLD1d8TPseudo: in getOperandLatency()
4470 case ARM::VLD1d16TPseudo: in getOperandLatency()
4471 case ARM::VLD1d32TPseudo: in getOperandLatency()
4472 case ARM::VLD1d64TPseudo: in getOperandLatency()
4473 case ARM::VLD1d64TPseudoWB_fixed: in getOperandLatency()
4474 case ARM::VLD1d64TPseudoWB_register: in getOperandLatency()
4475 case ARM::VLD3d8Pseudo_UPD: in getOperandLatency()
4476 case ARM::VLD3d16Pseudo_UPD: in getOperandLatency()
4477 case ARM::VLD3d32Pseudo_UPD: in getOperandLatency()
4478 case ARM::VLD3q8Pseudo_UPD: in getOperandLatency()
4479 case ARM::VLD3q16Pseudo_UPD: in getOperandLatency()
4480 case ARM::VLD3q32Pseudo_UPD: in getOperandLatency()
4481 case ARM::VLD3q8oddPseudo: in getOperandLatency()
4482 case ARM::VLD3q16oddPseudo: in getOperandLatency()
4483 case ARM::VLD3q32oddPseudo: in getOperandLatency()
4484 case ARM::VLD3q8oddPseudo_UPD: in getOperandLatency()
4485 case ARM::VLD3q16oddPseudo_UPD: in getOperandLatency()
4486 case ARM::VLD3q32oddPseudo_UPD: in getOperandLatency()
4487 case ARM::VLD4d8Pseudo: in getOperandLatency()
4488 case ARM::VLD4d16Pseudo: in getOperandLatency()
4489 case ARM::VLD4d32Pseudo: in getOperandLatency()
4490 case ARM::VLD1d8QPseudo: in getOperandLatency()
4491 case ARM::VLD1d16QPseudo: in getOperandLatency()
4492 case ARM::VLD1d32QPseudo: in getOperandLatency()
4493 case ARM::VLD1d64QPseudo: in getOperandLatency()
4494 case ARM::VLD1d64QPseudoWB_fixed: in getOperandLatency()
4495 case ARM::VLD1d64QPseudoWB_register: in getOperandLatency()
4496 case ARM::VLD1q8HighQPseudo: in getOperandLatency()
4497 case ARM::VLD1q8LowQPseudo_UPD: in getOperandLatency()
4498 case ARM::VLD1q8HighTPseudo: in getOperandLatency()
4499 case ARM::VLD1q8LowTPseudo_UPD: in getOperandLatency()
4500 case ARM::VLD1q16HighQPseudo: in getOperandLatency()
4501 case ARM::VLD1q16LowQPseudo_UPD: in getOperandLatency()
4502 case ARM::VLD1q16HighTPseudo: in getOperandLatency()
4503 case ARM::VLD1q16LowTPseudo_UPD: in getOperandLatency()
4504 case ARM::VLD1q32HighQPseudo: in getOperandLatency()
4505 case ARM::VLD1q32LowQPseudo_UPD: in getOperandLatency()
4506 case ARM::VLD1q32HighTPseudo: in getOperandLatency()
4507 case ARM::VLD1q32LowTPseudo_UPD: in getOperandLatency()
4508 case ARM::VLD1q64HighQPseudo: in getOperandLatency()
4509 case ARM::VLD1q64LowQPseudo_UPD: in getOperandLatency()
4510 case ARM::VLD1q64HighTPseudo: in getOperandLatency()
4511 case ARM::VLD1q64LowTPseudo_UPD: in getOperandLatency()
4512 case ARM::VLD4d8Pseudo_UPD: in getOperandLatency()
4513 case ARM::VLD4d16Pseudo_UPD: in getOperandLatency()
4514 case ARM::VLD4d32Pseudo_UPD: in getOperandLatency()
4515 case ARM::VLD4q8Pseudo_UPD: in getOperandLatency()
4516 case ARM::VLD4q16Pseudo_UPD: in getOperandLatency()
4517 case ARM::VLD4q32Pseudo_UPD: in getOperandLatency()
4518 case ARM::VLD4q8oddPseudo: in getOperandLatency()
4519 case ARM::VLD4q16oddPseudo: in getOperandLatency()
4520 case ARM::VLD4q32oddPseudo: in getOperandLatency()
4521 case ARM::VLD4q8oddPseudo_UPD: in getOperandLatency()
4522 case ARM::VLD4q16oddPseudo_UPD: in getOperandLatency()
4523 case ARM::VLD4q32oddPseudo_UPD: in getOperandLatency()
4524 case ARM::VLD1DUPq8: in getOperandLatency()
4525 case ARM::VLD1DUPq16: in getOperandLatency()
4526 case ARM::VLD1DUPq32: in getOperandLatency()
4527 case ARM::VLD1DUPq8wb_fixed: in getOperandLatency()
4528 case ARM::VLD1DUPq16wb_fixed: in getOperandLatency()
4529 case ARM::VLD1DUPq32wb_fixed: in getOperandLatency()
4530 case ARM::VLD1DUPq8wb_register: in getOperandLatency()
4531 case ARM::VLD1DUPq16wb_register: in getOperandLatency()
4532 case ARM::VLD1DUPq32wb_register: in getOperandLatency()
4533 case ARM::VLD2DUPd8: in getOperandLatency()
4534 case ARM::VLD2DUPd16: in getOperandLatency()
4535 case ARM::VLD2DUPd32: in getOperandLatency()
4536 case ARM::VLD2DUPd8wb_fixed: in getOperandLatency()
4537 case ARM::VLD2DUPd16wb_fixed: in getOperandLatency()
4538 case ARM::VLD2DUPd32wb_fixed: in getOperandLatency()
4539 case ARM::VLD2DUPd8wb_register: in getOperandLatency()
4540 case ARM::VLD2DUPd16wb_register: in getOperandLatency()
4541 case ARM::VLD2DUPd32wb_register: in getOperandLatency()
4542 case ARM::VLD2DUPq8EvenPseudo: in getOperandLatency()
4543 case ARM::VLD2DUPq8OddPseudo: in getOperandLatency()
4544 case ARM::VLD2DUPq16EvenPseudo: in getOperandLatency()
4545 case ARM::VLD2DUPq16OddPseudo: in getOperandLatency()
4546 case ARM::VLD2DUPq32EvenPseudo: in getOperandLatency()
4547 case ARM::VLD2DUPq32OddPseudo: in getOperandLatency()
4548 case ARM::VLD3DUPq8EvenPseudo: in getOperandLatency()
4549 case ARM::VLD3DUPq8OddPseudo: in getOperandLatency()
4550 case ARM::VLD3DUPq16EvenPseudo: in getOperandLatency()
4551 case ARM::VLD3DUPq16OddPseudo: in getOperandLatency()
4552 case ARM::VLD3DUPq32EvenPseudo: in getOperandLatency()
4553 case ARM::VLD3DUPq32OddPseudo: in getOperandLatency()
4554 case ARM::VLD4DUPd8Pseudo: in getOperandLatency()
4555 case ARM::VLD4DUPd16Pseudo: in getOperandLatency()
4556 case ARM::VLD4DUPd32Pseudo: in getOperandLatency()
4557 case ARM::VLD4DUPd8Pseudo_UPD: in getOperandLatency()
4558 case ARM::VLD4DUPd16Pseudo_UPD: in getOperandLatency()
4559 case ARM::VLD4DUPd32Pseudo_UPD: in getOperandLatency()
4560 case ARM::VLD4DUPq8EvenPseudo: in getOperandLatency()
4561 case ARM::VLD4DUPq8OddPseudo: in getOperandLatency()
4562 case ARM::VLD4DUPq16EvenPseudo: in getOperandLatency()
4563 case ARM::VLD4DUPq16OddPseudo: in getOperandLatency()
4564 case ARM::VLD4DUPq32EvenPseudo: in getOperandLatency()
4565 case ARM::VLD4DUPq32OddPseudo: in getOperandLatency()
4566 case ARM::VLD1LNq8Pseudo: in getOperandLatency()
4567 case ARM::VLD1LNq16Pseudo: in getOperandLatency()
4568 case ARM::VLD1LNq32Pseudo: in getOperandLatency()
4569 case ARM::VLD1LNq8Pseudo_UPD: in getOperandLatency()
4570 case ARM::VLD1LNq16Pseudo_UPD: in getOperandLatency()
4571 case ARM::VLD1LNq32Pseudo_UPD: in getOperandLatency()
4572 case ARM::VLD2LNd8Pseudo: in getOperandLatency()
4573 case ARM::VLD2LNd16Pseudo: in getOperandLatency()
4574 case ARM::VLD2LNd32Pseudo: in getOperandLatency()
4575 case ARM::VLD2LNq16Pseudo: in getOperandLatency()
4576 case ARM::VLD2LNq32Pseudo: in getOperandLatency()
4577 case ARM::VLD2LNd8Pseudo_UPD: in getOperandLatency()
4578 case ARM::VLD2LNd16Pseudo_UPD: in getOperandLatency()
4579 case ARM::VLD2LNd32Pseudo_UPD: in getOperandLatency()
4580 case ARM::VLD2LNq16Pseudo_UPD: in getOperandLatency()
4581 case ARM::VLD2LNq32Pseudo_UPD: in getOperandLatency()
4582 case ARM::VLD4LNd8Pseudo: in getOperandLatency()
4583 case ARM::VLD4LNd16Pseudo: in getOperandLatency()
4584 case ARM::VLD4LNd32Pseudo: in getOperandLatency()
4585 case ARM::VLD4LNq16Pseudo: in getOperandLatency()
4586 case ARM::VLD4LNq32Pseudo: in getOperandLatency()
4587 case ARM::VLD4LNd8Pseudo_UPD: in getOperandLatency()
4588 case ARM::VLD4LNd16Pseudo_UPD: in getOperandLatency()
4589 case ARM::VLD4LNd32Pseudo_UPD: in getOperandLatency()
4590 case ARM::VLD4LNq16Pseudo_UPD: in getOperandLatency()
4591 case ARM::VLD4LNq32Pseudo_UPD: in getOperandLatency()
4611 if (MCID.isCall() || (MCID.hasImplicitDefOfPhysReg(ARM::CPSR) && in getPredicationCost()
4634 if (I->getOpcode() != ARM::t2IT) in getInstrLatency()
4641 if (PredCost && (MCID.isCall() || (MCID.hasImplicitDefOfPhysReg(ARM::CPSR) && in getInstrLatency()
4683 case ARM::VLDMQIA: in getInstrLatency()
4684 case ARM::VSTMQIA: in getInstrLatency()
4732 if (MI.getOpcode() == ARM::tMOVr && !Subtarget.hasV6Ops()) { in verifyInstruction()
4734 if (!ARM::hGPRRegClass.contains(MI.getOperand(0).getReg()) && in verifyInstruction()
4735 !ARM::hGPRRegClass.contains(MI.getOperand(1).getReg())) { in verifyInstruction()
4740 if (MI.getOpcode() == ARM::tPUSH || in verifyInstruction()
4741 MI.getOpcode() == ARM::tPOP || in verifyInstruction()
4742 MI.getOpcode() == ARM::tPOP_RET) { in verifyInstruction()
4748 if (Reg < ARM::R0 || Reg > ARM::R7) { in verifyInstruction()
4749 if (!(MI.getOpcode() == ARM::tPUSH && Reg == ARM::LR) && in verifyInstruction()
4750 !(MI.getOpcode() == ARM::tPOP_RET && Reg == ARM::PC)) { in verifyInstruction()
4839 if (MI.getOpcode() == ARM::VMOVD && !isPredicated(MI)) in getExecutionDomain()
4845 (MI.getOpcode() == ARM::VMOVRS || MI.getOpcode() == ARM::VMOVSR || in getExecutionDomain()
4846 MI.getOpcode() == ARM::VMOVS)) in getExecutionDomain()
4868 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
4871 if (DReg != ARM::NoRegister) in getCorrespondingDRegAndLane()
4875 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
4908 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1); in getImplicitSPRUseForDPRUse()
4933 case ARM::VMOVD: in setExecutionDomain()
4951 MI.setDesc(get(ARM::VORRd)); in setExecutionDomain()
4957 case ARM::VMOVRS: in setExecutionDomain()
4974 MI.setDesc(get(ARM::VGETLNi32)); in setExecutionDomain()
4984 case ARM::VMOVSR: { in setExecutionDomain()
5004 MI.setDesc(get(ARM::VSETLNi32)); in setExecutionDomain()
5018 case ARM::VMOVS: { in setExecutionDomain()
5040 MI.setDesc(get(ARM::VDUPLN32d)); in setExecutionDomain()
5068 NewMIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::VEXTd32), in setExecutionDomain()
5087 MI.setDesc(get(ARM::VEXTd32)); in setExecutionDomain()
5148 case ARM::VLDRS: in getPartialRegUpdateClearance()
5149 case ARM::FCONSTS: in getPartialRegUpdateClearance()
5150 case ARM::VMOVSR: in getPartialRegUpdateClearance()
5151 case ARM::VMOVv8i8: in getPartialRegUpdateClearance()
5152 case ARM::VMOVv4i16: in getPartialRegUpdateClearance()
5153 case ARM::VMOVv2i32: in getPartialRegUpdateClearance()
5154 case ARM::VMOVv2f32: in getPartialRegUpdateClearance()
5155 case ARM::VMOVv1i64: in getPartialRegUpdateClearance()
5160 case ARM::VLD1LNd32: in getPartialRegUpdateClearance()
5177 } else if (ARM::SPRRegClass.contains(Reg)) { in getPartialRegUpdateClearance()
5179 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0, in getPartialRegUpdateClearance()
5180 &ARM::DPRRegClass); in getPartialRegUpdateClearance()
5204 if (ARM::SPRRegClass.contains(Reg)) { in breakPartialRegDependency()
5205 DReg = ARM::D0 + (Reg - ARM::S0) / 2; in breakPartialRegDependency()
5209 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps"); in breakPartialRegDependency()
5220 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::FCONSTD), DReg) in breakPartialRegDependency()
5227 return Subtarget.getFeatureBits()[ARM::HasV6KOps]; in hasNOP()
5251 case ARM::VMOVDRR: in getRegSequenceLikeInputs()
5260 MOReg->getSubReg(), ARM::ssub_0)); in getRegSequenceLikeInputs()
5265 MOReg->getSubReg(), ARM::ssub_1)); in getRegSequenceLikeInputs()
5278 case ARM::VMOVRRD: in getExtractSubregLikeInputs()
5288 InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1; in getExtractSubregLikeInputs()
5301 case ARM::VSETLNi32: in getInsertSubregLikeInputs()
5313 InsertedReg.SubIdx = MOIndex.getImm() == 0 ? ARM::ssub_0 : ARM::ssub_1; in getInsertSubregLikeInputs()
5360 if (Opcode == ARM::SUBri) in isAddImmediate()
5362 else if (Opcode != ARM::ADDri) in isAddImmediate()
5394 if (CmpMI->modifiesRegister(ARM::CPSR, TRI)) in findCMPToFoldIntoCBZ()
5396 if (CmpMI->readsRegister(ARM::CPSR, TRI)) in findCMPToFoldIntoCBZ()
5402 if (CmpMI->getOpcode() != ARM::tCMPi8 && CmpMI->getOpcode() != ARM::t2CMPri) in findCMPToFoldIntoCBZ()