155     addRegisterClass(MVT::v2i16, &AMDGPU::SReg_32RegClass);  in SITargetLowering()
194   setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);  in SITargetLowering()
232   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);  in SITargetLowering()
317   setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i16, Custom);  in SITargetLowering()
322   setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom);  in SITargetLowering()
525     for (MVT VT : {MVT::v2i16, MVT::v2f16, MVT::v4i16, MVT::v4f16}) {  in SITargetLowering()
549     setOperationAction(ISD::Constant, MVT::v2i16, Legal);  in SITargetLowering()
552     setOperationAction(ISD::UNDEF, MVT::v2i16, Legal);  in SITargetLowering()
555     setOperationAction(ISD::STORE, MVT::v2i16, Promote);  in SITargetLowering()
556     AddPromotedToType(ISD::STORE, MVT::v2i16, MVT::i32);  in SITargetLowering()
560     setOperationAction(ISD::LOAD, MVT::v2i16, Promote);  in SITargetLowering()
561     AddPromotedToType(ISD::LOAD, MVT::v2i16, MVT::i32);  in SITargetLowering()
565     setOperationAction(ISD::AND, MVT::v2i16, Promote);  in SITargetLowering()
566     AddPromotedToType(ISD::AND, MVT::v2i16, MVT::i32);  in SITargetLowering()
567     setOperationAction(ISD::OR, MVT::v2i16, Promote);  in SITargetLowering()
568     AddPromotedToType(ISD::OR, MVT::v2i16, MVT::i32);  in SITargetLowering()
569     setOperationAction(ISD::XOR, MVT::v2i16, Promote);  in SITargetLowering()
570     AddPromotedToType(ISD::XOR, MVT::v2i16, MVT::i32);  in SITargetLowering()
592       setOperationAction(ISD::BUILD_VECTOR, MVT::v2i16, Custom);  in SITargetLowering()
614     setOperationAction(ISD::ADD, MVT::v2i16, Legal);  in SITargetLowering()
615     setOperationAction(ISD::SUB, MVT::v2i16, Legal);  in SITargetLowering()
616     setOperationAction(ISD::MUL, MVT::v2i16, Legal);  in SITargetLowering()
617     setOperationAction(ISD::SHL, MVT::v2i16, Legal);  in SITargetLowering()
618     setOperationAction(ISD::SRL, MVT::v2i16, Legal);  in SITargetLowering()
619     setOperationAction(ISD::SRA, MVT::v2i16, Legal);  in SITargetLowering()
620     setOperationAction(ISD::SMIN, MVT::v2i16, Legal);  in SITargetLowering()
621     setOperationAction(ISD::UMIN, MVT::v2i16, Legal);  in SITargetLowering()
622     setOperationAction(ISD::SMAX, MVT::v2i16, Legal);  in SITargetLowering()
623     setOperationAction(ISD::UMAX, MVT::v2i16, Legal);  in SITargetLowering()
634     setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom);  in SITargetLowering()
672     setOperationAction(ISD::SELECT, MVT::v2i16, Promote);  in SITargetLowering()
673     AddPromotedToType(ISD::SELECT, MVT::v2i16, MVT::i32);  in SITargetLowering()
678     setOperationAction(ISD::SELECT, MVT::v2i16, Custom);  in SITargetLowering()
694   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2i16, Custom);  in SITargetLowering()
698   setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v2i16, Custom);  in SITargetLowering()
708   setOperationAction(ISD::INTRINSIC_VOID, MVT::v2i16, Custom);  in SITargetLowering()
811       return VT.isInteger() ? MVT::v2i16 : MVT::v2f16;  in getRegisterTypeForCallingConv()
869       RegisterVT = VT.isInteger() ? MVT::v2i16 : MVT::v2f16;  in getVectorTypeBreakdownForCallingConv()
4320         Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, Cvt));  in ReplaceNodeResults()
4829     SDValue LoVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, LoHalf);  in lowerINSERT_VECTOR_ELT()
4830     SDValue HiVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, HiHalf);  in lowerINSERT_VECTOR_ELT()
4834     SDValue InsHalf = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, MVT::v2i16,  in lowerINSERT_VECTOR_ELT()
4932   EVT PackVT = ResultVT.isInteger() ? MVT::v2i16 : MVT::v2f16;  in lowerVECTOR_SHUFFLE()
5000   assert(VT == MVT::v2f16 || VT == MVT::v2i16);  in lowerBUILD_VECTOR()
5466     const MVT VectorVT = VAddrScalarVT == MVT::f16 ? MVT::v2f16 : MVT::v2i16;  in lowerImage()
10092     if (VT == MVT::v2i16 || VT == MVT::v2f16) {  in PerformDAGCombine()