Lines Matching refs:SDValue
74 static bool isNullConstantOrUndef(SDValue V) { in isNullConstantOrUndef()
82 static bool getConstantValue(SDValue N, uint32_t &Out) { in getConstantValue()
167 std::pair<SDValue, SDValue> foldFrameIndex(SDValue N) const;
168 bool isNoNanSrc(SDValue N) const;
196 SDNode *glueCopyToOp(SDNode *N, SDValue NewChain, SDValue Glue) const;
197 SDNode *glueCopyToM0(SDNode *N, SDValue Val) const;
201 virtual bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
202 virtual bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
203 bool isDSOffsetLegal(SDValue Base, unsigned Offset,
205 bool SelectDS1Addr1Offset(SDValue Ptr, SDValue &Base, SDValue &Offset) const;
206 bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
207 SDValue &Offset1) const;
208 bool SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
209 SDValue &SOffset, SDValue &Offset, SDValue &Offen,
210 SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC,
211 SDValue &TFE, SDValue &DLC, SDValue &SWZ) const;
212 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
213 SDValue &SOffset, SDValue &Offset, SDValue &GLC,
214 SDValue &SLC, SDValue &TFE, SDValue &DLC,
215 SDValue &SWZ) const;
216 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
217 SDValue &VAddr, SDValue &SOffset, SDValue &Offset,
218 SDValue &SLC) const;
220 SDValue Addr, SDValue &RSrc, SDValue &VAddr,
221 SDValue &SOffset, SDValue &ImmOffset) const;
223 SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
224 SDValue &Offset) const;
226 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset,
227 SDValue &Offset, SDValue &GLC, SDValue &SLC,
228 SDValue &TFE, SDValue &DLC, SDValue &SWZ) const;
229 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
230 SDValue &Offset, SDValue &SLC) const;
231 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
232 SDValue &Offset) const;
235 bool SelectFlatOffset(SDNode *N, SDValue Addr, SDValue &VAddr,
236 SDValue &Offset, SDValue &SLC) const;
237 bool SelectFlatAtomic(SDNode *N, SDValue Addr, SDValue &VAddr,
238 SDValue &Offset, SDValue &SLC) const;
239 bool SelectFlatAtomicSigned(SDNode *N, SDValue Addr, SDValue &VAddr,
240 SDValue &Offset, SDValue &SLC) const;
242 bool SelectSMRDOffset(SDValue ByteOffsetNode, SDValue &Offset,
244 SDValue Expand32BitAddress(SDValue Addr) const;
245 bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue &Offset,
247 bool SelectSMRDImm(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
248 bool SelectSMRDImm32(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
249 bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
250 bool SelectSMRDBufferImm(SDValue Addr, SDValue &Offset) const;
251 bool SelectSMRDBufferImm32(SDValue Addr, SDValue &Offset) const;
252 bool SelectMOVRELOffset(SDValue Index, SDValue &Base, SDValue &Offset) const;
254 bool SelectVOP3Mods_NNaN(SDValue In, SDValue &Src, SDValue &SrcMods) const;
255 bool SelectVOP3Mods_f32(SDValue In, SDValue &Src, SDValue &SrcMods) const;
256 bool SelectVOP3ModsImpl(SDValue In, SDValue &Src, unsigned &SrcMods) const;
257 bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
258 bool SelectVOP3NoMods(SDValue In, SDValue &Src) const;
259 bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods,
260 SDValue &Clamp, SDValue &Omod) const;
261 bool SelectVOP3NoMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
262 SDValue &Clamp, SDValue &Omod) const;
264 bool SelectVOP3OMods(SDValue In, SDValue &Src,
265 SDValue &Clamp, SDValue &Omod) const;
267 bool SelectVOP3PMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
268 bool SelectVOP3PMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
269 SDValue &Clamp) const;
271 bool SelectVOP3OpSel(SDValue In, SDValue &Src, SDValue &SrcMods) const;
272 bool SelectVOP3OpSel0(SDValue In, SDValue &Src, SDValue &SrcMods,
273 SDValue &Clamp) const;
275 bool SelectVOP3OpSelMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
276 bool SelectVOP3OpSelMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
277 SDValue &Clamp) const;
278 bool SelectVOP3PMadMixModsImpl(SDValue In, SDValue &Src, unsigned &Mods) const;
279 bool SelectVOP3PMadMixMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
281 SDValue getHi16Elt(SDValue In) const;
283 SDValue getMaterializedScalarImm32(int64_t Val, const SDLoc &DL) const;
294 SDNode *getS_BFE(unsigned Opcode, const SDLoc &DL, SDValue Val,
317 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
318 bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
319 SDValue& Offset);
326 bool SelectADDRIndirect(SDValue Addr, SDValue &Base,
327 SDValue &Offset) override;
328 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
329 SDValue &Offset) override;
340 static SDValue stripBitcast(SDValue Val) { in stripBitcast()
345 static bool isExtractHiElt(SDValue In, SDValue &Out) { in isExtractHiElt()
350 SDValue Srl = In.getOperand(0); in isExtractHiElt()
365 static SDValue stripExtractLoElt(SDValue In) { in stripExtractLoElt()
367 SDValue Src = In.getOperand(0); in stripExtractLoElt()
422 SDValue Lo = N->getOperand(0); in matchLoadD16FromBuildVector()
423 SDValue Hi = N->getOperand(1); in matchLoadD16FromBuildVector()
436 SDValue TiedIn = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), VT, Lo); in matchLoadD16FromBuildVector()
437 SDValue Ops[] = { in matchLoadD16FromBuildVector()
449 SDValue NewLoadHi = in matchLoadD16FromBuildVector()
454 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), NewLoadHi); in matchLoadD16FromBuildVector()
455 CurDAG->ReplaceAllUsesOfValueWith(SDValue(LdHi, 1), NewLoadHi.getValue(1)); in matchLoadD16FromBuildVector()
464 SDValue TiedIn = getHi16Elt(Hi); in matchLoadD16FromBuildVector()
479 SDValue Ops[] = { in matchLoadD16FromBuildVector()
483 SDValue NewLoadLo = in matchLoadD16FromBuildVector()
488 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), NewLoadLo); in matchLoadD16FromBuildVector()
489 CurDAG->ReplaceAllUsesOfValueWith(SDValue(LdLo, 1), NewLoadLo.getValue(1)); in matchLoadD16FromBuildVector()
524 bool AMDGPUDAGToDAGISel::isNoNanSrc(SDValue N) const { in isNoNanSrc()
599 SDValue SubRegOp = N->getOperand(OpNo + 1); in getOperandRegClass()
607 SDNode *AMDGPUDAGToDAGISel::glueCopyToOp(SDNode *N, SDValue NewChain, in glueCopyToOp()
608 SDValue Glue) const { in glueCopyToOp()
609 SmallVector <SDValue, 8> Ops; in glueCopyToOp()
618 SDNode *AMDGPUDAGToDAGISel::glueCopyToM0(SDNode *N, SDValue Val) const { in glueCopyToM0()
624 SDValue M0 = Lowering.copyToM0(*CurDAG, N->getOperand(0), SDLoc(N), Val); in glueCopyToM0()
650 const SDValue Ops[] = { in buildSMovImm64()
652 SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32), in buildSMovImm64()
653 SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)}; in buildSMovImm64()
686 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector()
699 SmallVector<SDValue, 32 * 2 + 1> RegSeqArgs(NumVectorElts * 2 + 1); in SelectBuildVector()
721 RegSeqArgs[1 + (2 * i)] = SDValue(ImpDef, 0); in SelectBuildVector()
809 SDValue RC, SubReg0, SubReg1; in Select()
822 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0, in Select()
959 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base, in SelectADDRVTX_READ()
960 SDValue &Offset) { in SelectADDRVTX_READ()
964 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base, in SelectADDRIndirect()
965 SDValue &Offset) { in SelectADDRIndirect()
988 SDValue AMDGPUDAGToDAGISel::getMaterializedScalarImm32(int64_t Val, in getMaterializedScalarImm32()
993 return SDValue(Mov, 0); in getMaterializedScalarImm32()
999 SDValue LHS = N->getOperand(0); in SelectADD_SUB_I64()
1000 SDValue RHS = N->getOperand(1); in SelectADD_SUB_I64()
1008 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); in SelectADD_SUB_I64()
1009 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in SelectADD_SUB_I64()
1028 SDValue Args[] = { SDValue(Lo0, 0), SDValue(Lo1, 0) }; in SelectADD_SUB_I64()
1031 SDValue Args[] = { SDValue(Lo0, 0), SDValue(Lo1, 0), N->getOperand(2) }; in SelectADD_SUB_I64()
1034 SDValue AddHiArgs[] = { in SelectADD_SUB_I64()
1035 SDValue(Hi0, 0), in SelectADD_SUB_I64()
1036 SDValue(Hi1, 0), in SelectADD_SUB_I64()
1037 SDValue(AddLo, 1) in SelectADD_SUB_I64()
1041 SDValue RegSequenceArgs[] = { in SelectADD_SUB_I64()
1043 SDValue(AddLo,0), in SelectADD_SUB_I64()
1045 SDValue(AddHi,0), in SelectADD_SUB_I64()
1053 ReplaceUses(SDValue(N, 1), SDValue(AddHi, 1)); in SelectADD_SUB_I64()
1062 SDValue LHS = N->getOperand(0); in SelectAddcSubb()
1063 SDValue RHS = N->getOperand(1); in SelectAddcSubb()
1064 SDValue CI = N->getOperand(2); in SelectAddcSubb()
1089 SDValue Ops[10]; in SelectFMA_W_CHAIN()
1103 SDValue Ops[8]; in SelectFMUL_W_CHAIN()
1124 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) }; in SelectDIV_SCALE()
1140 SDValue CarryIn = N->getOperand(3); in SelectDIV_FMAS()
1142 SDValue VCC = CurDAG->getCopyToReg(CurDAG->getEntryNode(), SL, in SelectDIV_FMAS()
1143 TRI->getVCC(), CarryIn, SDValue()); in SelectDIV_FMAS()
1145 SDValue Ops[10]; in SelectDIV_FMAS()
1164 SDValue Clamp = CurDAG->getTargetConstant(0, SL, MVT::i1); in SelectMAD_64_32()
1165 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), in SelectMAD_64_32()
1170 bool AMDGPUDAGToDAGISel::isDSOffsetLegal(SDValue Base, unsigned Offset, in isDSOffsetLegal()
1185 bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base, in SelectDS1Addr1Offset()
1186 SDValue &Offset) const { in SelectDS1Addr1Offset()
1189 SDValue N0 = Addr.getOperand(0); in SelectDS1Addr1Offset()
1190 SDValue N1 = Addr.getOperand(1); in SelectDS1Addr1Offset()
1203 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32); in SelectDS1Addr1Offset()
1208 SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32, in SelectDS1Addr1Offset()
1212 SmallVector<SDValue, 3> Opnds; in SelectDS1Addr1Offset()
1227 Base = SDValue(MachineSub, 0); in SelectDS1Addr1Offset()
1242 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32); in SelectDS1Addr1Offset()
1245 Base = SDValue(MovZero, 0); in SelectDS1Addr1Offset()
1258 bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base, in SelectDS64Bit4ByteAligned()
1259 SDValue &Offset0, in SelectDS64Bit4ByteAligned()
1260 SDValue &Offset1) const { in SelectDS64Bit4ByteAligned()
1264 SDValue N0 = Addr.getOperand(0); in SelectDS64Bit4ByteAligned()
1265 SDValue N1 = Addr.getOperand(1); in SelectDS64Bit4ByteAligned()
1284 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32); in SelectDS64Bit4ByteAligned()
1289 SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32, in SelectDS64Bit4ByteAligned()
1293 SmallVector<SDValue, 3> Opnds; in SelectDS64Bit4ByteAligned()
1306 Base = SDValue(MachineSub, 0); in SelectDS64Bit4ByteAligned()
1319 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32); in SelectDS64Bit4ByteAligned()
1323 Base = SDValue(MovZero, 0); in SelectDS64Bit4ByteAligned()
1338 bool AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr, in SelectMUBUF()
1339 SDValue &VAddr, SDValue &SOffset, in SelectMUBUF()
1340 SDValue &Offset, SDValue &Offen, in SelectMUBUF()
1341 SDValue &Idxen, SDValue &Addr64, in SelectMUBUF()
1342 SDValue &GLC, SDValue &SLC, in SelectMUBUF()
1343 SDValue &TFE, SDValue &DLC, in SelectMUBUF()
1344 SDValue &SWZ) const { in SelectMUBUF()
1365 SDValue N0 = Addr; in SelectMUBUF()
1377 SDValue N2 = N0.getOperand(0); in SelectMUBUF()
1378 SDValue N3 = N0.getOperand(1); in SelectMUBUF()
1385 Ptr = SDValue(buildSMovImm64(DL, 0, MVT::v2i32), 0); in SelectMUBUF()
1401 Ptr = SDValue(buildSMovImm64(DL, 0, MVT::v2i32), 0); in SelectMUBUF()
1426 SDValue(CurDAG->getMachineNode( in SelectMUBUF()
1433 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, in SelectMUBUFAddr64()
1434 SDValue &VAddr, SDValue &SOffset, in SelectMUBUFAddr64()
1435 SDValue &Offset, SDValue &GLC, in SelectMUBUFAddr64()
1436 SDValue &SLC, SDValue &TFE, in SelectMUBUFAddr64()
1437 SDValue &DLC, SDValue &SWZ) const { in SelectMUBUFAddr64()
1438 SDValue Ptr, Offen, Idxen, Addr64; in SelectMUBUFAddr64()
1455 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0); in SelectMUBUFAddr64()
1462 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, in SelectMUBUFAddr64()
1463 SDValue &VAddr, SDValue &SOffset, in SelectMUBUFAddr64()
1464 SDValue &Offset, in SelectMUBUFAddr64()
1465 SDValue &SLC) const { in SelectMUBUFAddr64()
1467 SDValue GLC, TFE, DLC, SWZ; in SelectMUBUFAddr64()
1477 std::pair<SDValue, SDValue> AMDGPUDAGToDAGISel::foldFrameIndex(SDValue N) const { in foldFrameIndex()
1482 SDValue TFI = CurDAG->getTargetFrameIndex(FI->getIndex(), in foldFrameIndex()
1498 SDValue Addr, SDValue &Rsrc, in SelectMUBUFScratchOffen()
1499 SDValue &VAddr, SDValue &SOffset, in SelectMUBUFScratchOffen()
1500 SDValue &ImmOffset) const { in SelectMUBUFScratchOffen()
1511 SDValue HighBits = CurDAG->getTargetConstant(Imm & ~4095, DL, MVT::i32); in SelectMUBUFScratchOffen()
1514 VAddr = SDValue(MovHighBits, 0); in SelectMUBUFScratchOffen()
1530 SDValue N0 = Addr.getOperand(0); in SelectMUBUFScratchOffen()
1531 SDValue N1 = Addr.getOperand(1); in SelectMUBUFScratchOffen()
1565 SDValue Addr, in SelectMUBUFScratchOffset()
1566 SDValue &SRsrc, in SelectMUBUFScratchOffset()
1567 SDValue &SOffset, in SelectMUBUFScratchOffset()
1568 SDValue &Offset) const { in SelectMUBUFScratchOffset()
1591 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, in SelectMUBUFOffset()
1592 SDValue &SOffset, SDValue &Offset, in SelectMUBUFOffset()
1593 SDValue &GLC, SDValue &SLC, in SelectMUBUFOffset()
1594 SDValue &TFE, SDValue &DLC, in SelectMUBUFOffset()
1595 SDValue &SWZ) const { in SelectMUBUFOffset()
1596 SDValue Ptr, VAddr, Offen, Idxen, Addr64; in SelectMUBUFOffset()
1614 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0); in SelectMUBUFOffset()
1620 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, in SelectMUBUFOffset()
1621 SDValue &Soffset, SDValue &Offset in SelectMUBUFOffset()
1623 SDValue GLC, SLC, TFE, DLC, SWZ; in SelectMUBUFOffset()
1627 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, in SelectMUBUFOffset()
1628 SDValue &Soffset, SDValue &Offset, in SelectMUBUFOffset()
1629 SDValue &SLC) const { in SelectMUBUFOffset()
1630 SDValue GLC, TFE, DLC, SWZ; in SelectMUBUFOffset()
1638 N = AMDGPUTargetLowering::stripBitcast(SDValue(N,0)).getNode(); in findMemSDNode()
1642 for (SDValue V : N->op_values()) in findMemSDNode()
1651 SDValue Addr, in SelectFlatOffset()
1652 SDValue &VAddr, in SelectFlatOffset()
1653 SDValue &Offset, in SelectFlatOffset()
1654 SDValue &SLC) const { in SelectFlatOffset()
1661 SDValue N0 = Addr.getOperand(0); in SelectFlatOffset()
1662 SDValue N1 = Addr.getOperand(1); in SelectFlatOffset()
1706 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); in SelectFlatOffset()
1707 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in SelectFlatOffset()
1714 SDValue AddOffsetLo in SelectFlatOffset()
1716 SDValue AddOffsetHi in SelectFlatOffset()
1720 SDValue Clamp = CurDAG->getTargetConstant(0, DL, MVT::i1); in SelectFlatOffset()
1724 {AddOffsetLo, SDValue(N0Lo, 0), Clamp}); in SelectFlatOffset()
1728 {AddOffsetHi, SDValue(N0Hi, 0), SDValue(Add, 1), Clamp}); in SelectFlatOffset()
1730 SDValue RegSequenceArgs[] = { in SelectFlatOffset()
1732 SDValue(Add, 0), Sub0, SDValue(Addc, 0), Sub1 in SelectFlatOffset()
1735 Addr = SDValue(CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL, in SelectFlatOffset()
1747 SDValue Addr, in SelectFlatAtomic()
1748 SDValue &VAddr, in SelectFlatAtomic()
1749 SDValue &Offset, in SelectFlatAtomic()
1750 SDValue &SLC) const { in SelectFlatAtomic()
1755 SDValue Addr, in SelectFlatAtomicSigned()
1756 SDValue &VAddr, in SelectFlatAtomicSigned()
1757 SDValue &Offset, in SelectFlatAtomicSigned()
1758 SDValue &SLC) const { in SelectFlatAtomicSigned()
1762 bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode, in SelectSMRDOffset()
1763 SDValue &Offset, bool &Imm) const { in SelectSMRDOffset()
1788 SDValue C32Bit = CurDAG->getTargetConstant(ByteOffset, SL, MVT::i32); in SelectSMRDOffset()
1789 Offset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SL, MVT::i32, in SelectSMRDOffset()
1796 SDValue AMDGPUDAGToDAGISel::Expand32BitAddress(SDValue Addr) const { in Expand32BitAddress()
1806 SDValue AddrHi = CurDAG->getTargetConstant(AddrHiVal, SL, MVT::i32); in Expand32BitAddress()
1808 const SDValue Ops[] = { in Expand32BitAddress()
1812 SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SL, MVT::i32, AddrHi), in Expand32BitAddress()
1817 return SDValue(CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, SL, MVT::i64, in Expand32BitAddress()
1821 bool AMDGPUDAGToDAGISel::SelectSMRD(SDValue Addr, SDValue &SBase, in SelectSMRD()
1822 SDValue &Offset, bool &Imm) const { in SelectSMRD()
1830 SDValue N0 = Addr.getOperand(0); in SelectSMRD()
1831 SDValue N1 = Addr.getOperand(1); in SelectSMRD()
1844 bool AMDGPUDAGToDAGISel::SelectSMRDImm(SDValue Addr, SDValue &SBase, in SelectSMRDImm()
1845 SDValue &Offset) const { in SelectSMRDImm()
1850 bool AMDGPUDAGToDAGISel::SelectSMRDImm32(SDValue Addr, SDValue &SBase, in SelectSMRDImm32()
1851 SDValue &Offset) const { in SelectSMRDImm32()
1863 bool AMDGPUDAGToDAGISel::SelectSMRDSgpr(SDValue Addr, SDValue &SBase, in SelectSMRDSgpr()
1864 SDValue &Offset) const { in SelectSMRDSgpr()
1870 bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm(SDValue Addr, in SelectSMRDBufferImm()
1871 SDValue &Offset) const { in SelectSMRDBufferImm()
1876 bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm32(SDValue Addr, in SelectSMRDBufferImm32()
1877 SDValue &Offset) const { in SelectSMRDBufferImm32()
1888 bool AMDGPUDAGToDAGISel::SelectMOVRELOffset(SDValue Index, in SelectMOVRELOffset()
1889 SDValue &Base, in SelectMOVRELOffset()
1890 SDValue &Offset) const { in SelectMOVRELOffset()
1894 SDValue N0 = Index.getOperand(0); in SelectMOVRELOffset()
1895 SDValue N1 = Index.getOperand(1); in SelectMOVRELOffset()
1917 SDValue Val, uint32_t Offset, in getS_BFE()
1923 SDValue PackedConst = CurDAG->getTargetConstant(PackedVal, DL, MVT::i32); in getS_BFE()
1933 const SDValue &Shl = N->getOperand(0); in SelectS_BFEFromShifts()
1959 const SDValue &Srl = N->getOperand(0); in SelectS_BFE()
1981 const SDValue &And = N->getOperand(0); in SelectS_BFE()
2011 SDValue Src = N->getOperand(0); in SelectS_BFE()
2034 SDValue Cond = N->getOperand(1); in isCBranchSCC()
2056 SDValue Cond = N->getOperand(1); in SelectBRCOND()
2086 Cond = SDValue(CurDAG->getMachineNode(ST->isWave32() ? AMDGPU::S_AND_B32 in SelectBRCOND()
2096 SDValue VCC = CurDAG->getCopyToReg(N->getOperand(0), SL, CondReg, Cond); in SelectBRCOND()
2113 SDValue Src0 = N->getOperand(0); in SelectFMAD_FMA()
2114 SDValue Src1 = N->getOperand(1); in SelectFMAD_FMA()
2115 SDValue Src2 = N->getOperand(2); in SelectFMAD_FMA()
2131 SDValue Zero = CurDAG->getTargetConstant(0, SDLoc(), MVT::i32); in SelectFMAD_FMA()
2132 SDValue Ops[] = { in SelectFMAD_FMA()
2164 SDValue SRsrc, VAddr, SOffset, Offset, SLC; in SelectATOMIC_CMP_SWAP()
2169 SDValue CmpVal = Mem->getOperand(2); in SelectATOMIC_CMP_SWAP()
2173 SDValue Ops[] = { in SelectATOMIC_CMP_SWAP()
2182 SDValue SRsrc, SOffset, Offset, SLC; in SelectATOMIC_CMP_SWAP()
2187 SDValue CmpVal = Mem->getOperand(2); in SelectATOMIC_CMP_SWAP()
2188 SDValue Ops[] = { in SelectATOMIC_CMP_SWAP()
2205 SDValue Extract in SelectATOMIC_CMP_SWAP()
2206 = CurDAG->getTargetExtractSubreg(SubReg, SL, VT, SDValue(CmpSwap, 0)); in SelectATOMIC_CMP_SWAP()
2208 ReplaceUses(SDValue(N, 0), Extract); in SelectATOMIC_CMP_SWAP()
2209 ReplaceUses(SDValue(N, 1), SDValue(CmpSwap, 1)); in SelectATOMIC_CMP_SWAP()
2219 SDValue Chain = N->getOperand(0); in SelectDSAppendConsume()
2220 SDValue Ptr = N->getOperand(2); in SelectDSAppendConsume()
2225 SDValue Offset; in SelectDSAppendConsume()
2227 SDValue PtrBase = Ptr.getOperand(0); in SelectDSAppendConsume()
2228 SDValue PtrOffset = Ptr.getOperand(1); in SelectDSAppendConsume()
2242 SDValue Ops[] = { in SelectDSAppendConsume()
2285 SDValue BaseOffset = N->getOperand(HasVSrc ? 3 : 2); in SelectDS_GWS()
2318 SDValue(SGPROffset, 0), in SelectDS_GWS()
2320 glueCopyToM0(N, SDValue(M0Base, 0)); in SelectDS_GWS()
2323 SDValue Chain = N->getOperand(0); in SelectDS_GWS()
2324 SDValue OffsetField = CurDAG->getTargetConstant(ImmOffset, SL, MVT::i32); in SelectDS_GWS()
2327 SDValue GDS = CurDAG->getTargetConstant(1, SL, MVT::i1); in SelectDS_GWS()
2330 SmallVector<SDValue, 5> Ops; in SelectDS_GWS()
2374 SDValue Src = N->getOperand(1); in SelectINTRINSIC_WO_CHAIN()
2396 bool AMDGPUDAGToDAGISel::SelectVOP3ModsImpl(SDValue In, SDValue &Src, in SelectVOP3ModsImpl()
2414 bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src, in SelectVOP3Mods()
2415 SDValue &SrcMods) const { in SelectVOP3Mods()
2425 bool AMDGPUDAGToDAGISel::SelectVOP3Mods_NNaN(SDValue In, SDValue &Src, in SelectVOP3Mods_NNaN()
2426 SDValue &SrcMods) const { in SelectVOP3Mods_NNaN()
2431 bool AMDGPUDAGToDAGISel::SelectVOP3Mods_f32(SDValue In, SDValue &Src, in SelectVOP3Mods_f32()
2432 SDValue &SrcMods) const { in SelectVOP3Mods_f32()
2440 bool AMDGPUDAGToDAGISel::SelectVOP3NoMods(SDValue In, SDValue &Src) const { in SelectVOP3NoMods()
2448 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src, in SelectVOP3Mods0()
2449 SDValue &SrcMods, SDValue &Clamp, in SelectVOP3Mods0()
2450 SDValue &Omod) const { in SelectVOP3Mods0()
2458 bool AMDGPUDAGToDAGISel::SelectVOP3OMods(SDValue In, SDValue &Src, in SelectVOP3OMods()
2459 SDValue &Clamp, SDValue &Omod) const { in SelectVOP3OMods()
2469 bool AMDGPUDAGToDAGISel::SelectVOP3PMods(SDValue In, SDValue &Src, in SelectVOP3PMods()
2470 SDValue &SrcMods) const { in SelectVOP3PMods()
2482 SDValue Lo = stripBitcast(Src.getOperand(0)); in SelectVOP3PMods()
2483 SDValue Hi = stripBitcast(Src.getOperand(1)); in SelectVOP3PMods()
2523 bool AMDGPUDAGToDAGISel::SelectVOP3PMods0(SDValue In, SDValue &Src, in SelectVOP3PMods0()
2524 SDValue &SrcMods, in SelectVOP3PMods0()
2525 SDValue &Clamp) const { in SelectVOP3PMods0()
2534 bool AMDGPUDAGToDAGISel::SelectVOP3OpSel(SDValue In, SDValue &Src, in SelectVOP3OpSel()
2535 SDValue &SrcMods) const { in SelectVOP3OpSel()
2542 bool AMDGPUDAGToDAGISel::SelectVOP3OpSel0(SDValue In, SDValue &Src, in SelectVOP3OpSel0()
2543 SDValue &SrcMods, in SelectVOP3OpSel0()
2544 SDValue &Clamp) const { in SelectVOP3OpSel0()
2553 bool AMDGPUDAGToDAGISel::SelectVOP3OpSelMods(SDValue In, SDValue &Src, in SelectVOP3OpSelMods()
2554 SDValue &SrcMods) const { in SelectVOP3OpSelMods()
2559 bool AMDGPUDAGToDAGISel::SelectVOP3OpSelMods0(SDValue In, SDValue &Src, in SelectVOP3OpSelMods0()
2560 SDValue &SrcMods, in SelectVOP3OpSelMods0()
2561 SDValue &Clamp) const { in SelectVOP3OpSelMods0()
2572 bool AMDGPUDAGToDAGISel::SelectVOP3PMadMixModsImpl(SDValue In, SDValue &Src, in SelectVOP3PMadMixModsImpl()
2613 bool AMDGPUDAGToDAGISel::SelectVOP3PMadMixMods(SDValue In, SDValue &Src, in SelectVOP3PMadMixMods()
2614 SDValue &SrcMods) const { in SelectVOP3PMadMixMods()
2621 SDValue AMDGPUDAGToDAGISel::getHi16Elt(SDValue In) const { in getHi16Elt()
2636 SDValue Src; in getHi16Elt()
2640 return SDValue(); in getHi16Elt()
2757 bool R600DAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr, in SelectGlobalValueConstantOffset()
2758 SDValue& IntPtr) { in SelectGlobalValueConstantOffset()
2767 bool R600DAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr, in SelectGlobalValueVariableOffset()
2768 SDValue& BaseReg, SDValue &Offset) { in SelectGlobalValueVariableOffset()
2814 bool R600DAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base, in SelectADDRIndirect()
2815 SDValue &Offset) { in SelectADDRIndirect()
2838 bool R600DAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base, in SelectADDRVTX_READ()
2839 SDValue &Offset) { in SelectADDRVTX_READ()