151 	dpll_md_reg = DPLL_MD(intel_crtc->pipe);  in intel_crt_mode_set()
176 		adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);  in intel_crt_mode_set()
177 	else if (intel_crtc->pipe == 0)  in intel_crt_mode_set()
183 		I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);  in intel_crt_mode_set()
332 	uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;  in intel_crt_load_detect()  local
350 	bclrpat_reg = BCLRPAT(pipe);  in intel_crt_load_detect()
351 	vtotal_reg = VTOTAL(pipe);  in intel_crt_load_detect()
352 	vblank_reg = VBLANK(pipe);  in intel_crt_load_detect()
353 	vsync_reg = VSYNC(pipe);  in intel_crt_load_detect()
354 	pipeconf_reg = PIPECONF(pipe);  in intel_crt_load_detect()
355 	pipe_dsl_reg = PIPEDSL(pipe);  in intel_crt_load_detect()
376 		intel_wait_for_vblank(dev, pipe);  in intel_crt_load_detect()