Lines Matching refs:Base
98 int Offset, unsigned Base, bool BaseKill, int Opcode,
109 unsigned Base,
117 void MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base,
288 int Offset, unsigned Base, bool BaseKill, in MergeOps() argument
343 .addReg(Base, getKillRegState(BaseKill)).addImm(Offset) in MergeOps()
345 Base = NewBase; in MergeOps()
354 .addReg(Base, getKillRegState(BaseKill)) in MergeOps()
429 unsigned Base, bool BaseKill, in MergeOpsUpdate() argument
482 if (!MergeOps(MBB, Loc, Offset, Base, BaseKill, Opcode, in MergeOpsUpdate()
524 unsigned Base, int Opcode, unsigned Size, in MergeLDR_STR() argument
579 Base, false, Opcode, Pred, PredReg, Scratch, dl, Merges); in MergeLDR_STR()
580 MergeLDR_STR(MBB, i, Base, Opcode, Size, Pred, PredReg, Scratch, in MergeLDR_STR()
589 bool BaseKill = Loc->findRegisterUseOperandIdx(Base, true) != -1; in MergeLDR_STR()
591 Base, BaseKill, Opcode, Pred, PredReg, Scratch, dl, Merges); in MergeLDR_STR()
609 static bool isMatchingDecrement(MachineInstr *MI, unsigned Base, in isMatchingDecrement() argument
632 if (!(MI->getOperand(0).getReg() == Base && in isMatchingDecrement()
633 MI->getOperand(1).getReg() == Base && in isMatchingDecrement()
642 static bool isMatchingIncrement(MachineInstr *MI, unsigned Base, in isMatchingIncrement() argument
665 if (!(MI->getOperand(0).getReg() == Base && in isMatchingIncrement()
666 MI->getOperand(1).getReg() == Base && in isMatchingIncrement()
795 unsigned Base = MI->getOperand(0).getReg(); in MergeBaseUpdateLSMultiple() local
806 if (MI->getOperand(i).getReg() == Base) in MergeBaseUpdateLSMultiple()
819 isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) { in MergeBaseUpdateLSMultiple()
823 isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) { in MergeBaseUpdateLSMultiple()
838 isMatchingIncrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) { in MergeBaseUpdateLSMultiple()
841 isMatchingDecrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) { in MergeBaseUpdateLSMultiple()
858 .addReg(Base, getDefRegState(true)) // WB base register in MergeBaseUpdateLSMultiple()
859 .addReg(Base, getKillRegState(BaseKill)) in MergeBaseUpdateLSMultiple()
931 unsigned Base = MI->getOperand(1).getReg(); in MergeBaseUpdateLoadStore() local
948 if (MI->getOperand(0).getReg() == Base) in MergeBaseUpdateLoadStore()
965 if (isMatchingDecrement(PrevMBBI, Base, Bytes, Limit, Pred, PredReg)) { in MergeBaseUpdateLoadStore()
969 isMatchingIncrement(PrevMBBI, Base, Bytes, Limit,Pred,PredReg)) { in MergeBaseUpdateLoadStore()
985 isMatchingDecrement(NextMBBI, Base, Bytes, Limit, Pred, PredReg)) { in MergeBaseUpdateLoadStore()
988 } else if (isMatchingIncrement(NextMBBI, Base, Bytes, Limit,Pred,PredReg)) { in MergeBaseUpdateLoadStore()
1011 .addReg(Base, getDefRegState(true)) // WB base register in MergeBaseUpdateLoadStore()
1012 .addReg(Base, getKillRegState(isLd ? BaseKill : false)) in MergeBaseUpdateLoadStore()
1022 .addReg(Base, RegState::Define) in MergeBaseUpdateLoadStore()
1023 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg); in MergeBaseUpdateLoadStore()
1027 .addReg(Base, RegState::Define) in MergeBaseUpdateLoadStore()
1028 .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg); in MergeBaseUpdateLoadStore()
1034 .addReg(Base, RegState::Define) in MergeBaseUpdateLoadStore()
1035 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg); in MergeBaseUpdateLoadStore()
1045 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base) in MergeBaseUpdateLoadStore()
1047 .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg); in MergeBaseUpdateLoadStore()
1051 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base) in MergeBaseUpdateLoadStore()
1053 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg); in MergeBaseUpdateLoadStore()
1327 unsigned Base = MBBI->getOperand(1).getReg(); in LoadStoreMultipleOpti() local
1340 Clobber = (isi32Load(Opcode) && Base == MBBI->getOperand(0).getReg()); in LoadStoreMultipleOpti()
1359 CurrBase = Base; in LoadStoreMultipleOpti()
1373 if (CurrOpc == Opcode && CurrBase == Base && CurrPred == Pred) { in LoadStoreMultipleOpti()
1568 unsigned Base, bool isLd,
1591 static bool IsSafeAndProfitableToMove(bool isLd, unsigned Base, in IsSafeAndProfitableToMove() argument
1623 if (MO.isDef() && TRI->regsOverlap(Reg, Base)) in IsSafeAndProfitableToMove()
1625 if (Reg != Base && !MemRegs.count(Reg)) in IsSafeAndProfitableToMove()
1740 unsigned Base, bool isLd, in RescheduleOps() argument
1804 DoMove = IsSafeAndProfitableToMove(isLd, Base, FirstOp, LastOp, in RescheduleOps()
1924 unsigned Base = MI->getOperand(1).getReg(); in RescheduleLoadStoreInstrs() local
1930 Base2LdsMap.find(Base); in RescheduleLoadStoreInstrs()
1941 Base2LdsMap[Base].push_back(MI); in RescheduleLoadStoreInstrs()
1942 LdBases.push_back(Base); in RescheduleLoadStoreInstrs()
1946 Base2StsMap.find(Base); in RescheduleLoadStoreInstrs()
1957 Base2StsMap[Base].push_back(MI); in RescheduleLoadStoreInstrs()
1958 StBases.push_back(Base); in RescheduleLoadStoreInstrs()
1972 unsigned Base = LdBases[i]; in RescheduleLoadStoreInstrs() local
1973 SmallVectorImpl<MachineInstr *> &Lds = Base2LdsMap[Base]; in RescheduleLoadStoreInstrs()
1975 RetVal |= RescheduleOps(MBB, Lds, Base, true, MI2LocMap); in RescheduleLoadStoreInstrs()
1980 unsigned Base = StBases[i]; in RescheduleLoadStoreInstrs() local
1981 SmallVectorImpl<MachineInstr *> &Sts = Base2StsMap[Base]; in RescheduleLoadStoreInstrs()
1983 RetVal |= RescheduleOps(MBB, Sts, Base, false, MI2LocMap); in RescheduleLoadStoreInstrs()