Lines Matching refs:pipe
136 pipe_name(crtc->pipe)); in intel_pipe_update_start()
187 enum i915_pipe pipe = crtc->pipe; in intel_pipe_update_end() local
217 pipe_name(pipe), crtc->debug.start_vbl_count, in intel_pipe_update_end()
227 pipe_name(pipe), in intel_pipe_update_end()
241 enum i915_pipe pipe = plane->pipe; in skl_update_plane() local
267 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), in skl_update_plane()
274 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value); in skl_update_plane()
275 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value); in skl_update_plane()
276 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask); in skl_update_plane()
279 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x); in skl_update_plane()
280 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride); in skl_update_plane()
281 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); in skl_update_plane()
282 I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), in skl_update_plane()
284 I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id), in skl_update_plane()
294 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), in skl_update_plane()
296 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0); in skl_update_plane()
297 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); in skl_update_plane()
298 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), in skl_update_plane()
301 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0); in skl_update_plane()
303 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x); in skl_update_plane()
306 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl); in skl_update_plane()
307 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), in skl_update_plane()
309 POSTING_READ_FW(PLANE_SURF(pipe, plane_id)); in skl_update_plane()
319 enum i915_pipe pipe = plane->pipe; in skl_disable_plane() local
324 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0); in skl_disable_plane()
326 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0); in skl_disable_plane()
327 POSTING_READ_FW(PLANE_SURF(pipe, plane_id)); in skl_disable_plane()
338 enum i915_pipe pipe = plane->pipe; in skl_plane_get_hw_state() local
341 power_domain = POWER_DOMAIN_PIPE(pipe); in skl_plane_get_hw_state()
345 ret = I915_READ(PLANE_CTL(pipe, plane_id)) & PLANE_CTL_ENABLE; in skl_plane_get_hw_state()
462 enum i915_pipe pipe = plane->pipe; in vlv_update_plane() local
484 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) in vlv_update_plane()
488 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value); in vlv_update_plane()
489 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value); in vlv_update_plane()
490 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask); in vlv_update_plane()
492 I915_WRITE_FW(SPSTRIDE(pipe, plane_id), fb->pitches[0]); in vlv_update_plane()
493 I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x); in vlv_update_plane()
496 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x); in vlv_update_plane()
498 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset); in vlv_update_plane()
500 I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0); in vlv_update_plane()
502 I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w); in vlv_update_plane()
503 I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl); in vlv_update_plane()
504 I915_WRITE_FW(SPSURF(pipe, plane_id), in vlv_update_plane()
506 POSTING_READ_FW(SPSURF(pipe, plane_id)); in vlv_update_plane()
515 enum i915_pipe pipe = plane->pipe; in vlv_disable_plane() local
521 I915_WRITE_FW(SPCNTR(pipe, plane_id), 0); in vlv_disable_plane()
523 I915_WRITE_FW(SPSURF(pipe, plane_id), 0); in vlv_disable_plane()
524 POSTING_READ_FW(SPSURF(pipe, plane_id)); in vlv_disable_plane()
535 enum i915_pipe pipe = plane->pipe; in vlv_plane_get_hw_state() local
538 power_domain = POWER_DOMAIN_PIPE(pipe); in vlv_plane_get_hw_state()
542 ret = I915_READ(SPCNTR(pipe, plane_id)) & SP_ENABLE; in vlv_plane_get_hw_state()
612 enum i915_pipe pipe = plane->pipe; in ivb_update_plane() local
641 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value); in ivb_update_plane()
642 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value); in ivb_update_plane()
643 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask); in ivb_update_plane()
646 I915_WRITE_FW(SPRSTRIDE(pipe), fb->pitches[0]); in ivb_update_plane()
647 I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x); in ivb_update_plane()
652 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x); in ivb_update_plane()
654 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x); in ivb_update_plane()
656 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset); in ivb_update_plane()
658 I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); in ivb_update_plane()
660 I915_WRITE_FW(SPRSCALE(pipe), sprscale); in ivb_update_plane()
661 I915_WRITE_FW(SPRCTL(pipe), sprctl); in ivb_update_plane()
662 I915_WRITE_FW(SPRSURF(pipe), in ivb_update_plane()
664 POSTING_READ_FW(SPRSURF(pipe)); in ivb_update_plane()
673 enum i915_pipe pipe = plane->pipe; in ivb_disable_plane() local
678 I915_WRITE_FW(SPRCTL(pipe), 0); in ivb_disable_plane()
681 I915_WRITE_FW(SPRSCALE(pipe), 0); in ivb_disable_plane()
683 I915_WRITE_FW(SPRSURF(pipe), 0); in ivb_disable_plane()
684 POSTING_READ_FW(SPRSURF(pipe)); in ivb_disable_plane()
694 enum i915_pipe pipe = plane->pipe; in ivb_plane_get_hw_state() local
697 power_domain = POWER_DOMAIN_PIPE(pipe); in ivb_plane_get_hw_state()
701 ret = I915_READ(SPRCTL(pipe)) & SPRITE_ENABLE; in ivb_plane_get_hw_state()
768 enum i915_pipe pipe = plane->pipe; in g4x_update_plane() local
797 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value); in g4x_update_plane()
798 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value); in g4x_update_plane()
799 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask); in g4x_update_plane()
802 I915_WRITE_FW(DVSSTRIDE(pipe), fb->pitches[0]); in g4x_update_plane()
803 I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x); in g4x_update_plane()
806 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x); in g4x_update_plane()
808 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset); in g4x_update_plane()
810 I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); in g4x_update_plane()
811 I915_WRITE_FW(DVSSCALE(pipe), dvsscale); in g4x_update_plane()
812 I915_WRITE_FW(DVSCNTR(pipe), dvscntr); in g4x_update_plane()
813 I915_WRITE_FW(DVSSURF(pipe), in g4x_update_plane()
815 POSTING_READ_FW(DVSSURF(pipe)); in g4x_update_plane()
824 enum i915_pipe pipe = plane->pipe; in g4x_disable_plane() local
829 I915_WRITE_FW(DVSCNTR(pipe), 0); in g4x_disable_plane()
831 I915_WRITE_FW(DVSSCALE(pipe), 0); in g4x_disable_plane()
833 I915_WRITE_FW(DVSSURF(pipe), 0); in g4x_disable_plane()
834 POSTING_READ_FW(DVSSURF(pipe)); in g4x_disable_plane()
844 enum i915_pipe pipe = plane->pipe; in g4x_plane_get_hw_state() local
847 power_domain = POWER_DOMAIN_PIPE(pipe); in g4x_plane_get_hw_state()
851 ret = I915_READ(DVSCNTR(pipe)) & DVS_ENABLE; in g4x_plane_get_hw_state()
886 if (plane->pipe != crtc->pipe) { in intel_check_sprite_plane()
1283 enum i915_pipe pipe, int plane) in intel_sprite_plane_create() argument
1378 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
1387 intel_plane->pipe = pipe; in intel_sprite_plane_create()
1390 intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane); in intel_sprite_plane_create()
1393 possible_crtcs = (1 << pipe); in intel_sprite_plane_create()
1401 "plane %d%c", plane + 2, pipe_name(pipe)); in intel_sprite_plane_create()
1408 "sprite %c", sprite_name(pipe, plane)); in intel_sprite_plane_create()