Lines Matching refs:pipe
647 enum i915_pipe pipe = intel_crtc->pipe; in chv_set_phy_signal_level() local
654 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); in chv_set_phy_signal_level()
658 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); in chv_set_phy_signal_level()
661 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); in chv_set_phy_signal_level()
665 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); in chv_set_phy_signal_level()
668 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); in chv_set_phy_signal_level()
671 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); in chv_set_phy_signal_level()
674 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); in chv_set_phy_signal_level()
677 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); in chv_set_phy_signal_level()
682 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); in chv_set_phy_signal_level()
685 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); in chv_set_phy_signal_level()
690 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); in chv_set_phy_signal_level()
703 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); in chv_set_phy_signal_level()
713 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); in chv_set_phy_signal_level()
718 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); in chv_set_phy_signal_level()
722 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); in chv_set_phy_signal_level()
724 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); in chv_set_phy_signal_level()
727 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); in chv_set_phy_signal_level()
729 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); in chv_set_phy_signal_level()
742 enum i915_pipe pipe = crtc->pipe; in chv_data_lane_soft_reset() local
745 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); in chv_data_lane_soft_reset()
750 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); in chv_data_lane_soft_reset()
753 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); in chv_data_lane_soft_reset()
758 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); in chv_data_lane_soft_reset()
761 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); in chv_data_lane_soft_reset()
767 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); in chv_data_lane_soft_reset()
770 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); in chv_data_lane_soft_reset()
776 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); in chv_data_lane_soft_reset()
788 enum i915_pipe pipe = intel_crtc->pipe; in chv_phy_pre_pll_enable() local
797 if (ch == DPIO_CH0 && pipe == PIPE_B) in chv_phy_pre_pll_enable()
809 if (pipe != PIPE_B) { in chv_phy_pre_pll_enable()
810 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_phy_pre_pll_enable()
816 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); in chv_phy_pre_pll_enable()
818 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); in chv_phy_pre_pll_enable()
824 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); in chv_phy_pre_pll_enable()
828 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); in chv_phy_pre_pll_enable()
830 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
834 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); in chv_phy_pre_pll_enable()
837 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); in chv_phy_pre_pll_enable()
839 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
843 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); in chv_phy_pre_pll_enable()
851 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); in chv_phy_pre_pll_enable()
852 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
856 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); in chv_phy_pre_pll_enable()
870 int pipe = intel_crtc->pipe; in chv_phy_pre_encoder_enable() local
877 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); in chv_phy_pre_encoder_enable()
879 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); in chv_phy_pre_encoder_enable()
882 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); in chv_phy_pre_encoder_enable()
884 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); in chv_phy_pre_encoder_enable()
894 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), in chv_phy_pre_encoder_enable()
910 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); in chv_phy_pre_encoder_enable()
912 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); in chv_phy_pre_encoder_enable()
915 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); in chv_phy_pre_encoder_enable()
917 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); in chv_phy_pre_encoder_enable()
920 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), in chv_phy_pre_encoder_enable()
928 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), in chv_phy_pre_encoder_enable()
956 enum i915_pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; in chv_phy_post_pll_disable() local
962 if (pipe != PIPE_B) { in chv_phy_post_pll_disable()
963 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_phy_post_pll_disable()
965 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); in chv_phy_post_pll_disable()
967 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); in chv_phy_post_pll_disable()
969 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); in chv_phy_post_pll_disable()
994 int pipe = intel_crtc->pipe; in vlv_set_phy_signal_level() local
997 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); in vlv_set_phy_signal_level()
998 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); in vlv_set_phy_signal_level()
999 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), in vlv_set_phy_signal_level()
1001 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); in vlv_set_phy_signal_level()
1004 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph); in vlv_set_phy_signal_level()
1006 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); in vlv_set_phy_signal_level()
1007 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); in vlv_set_phy_signal_level()
1008 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); in vlv_set_phy_signal_level()
1020 int pipe = intel_crtc->pipe; in vlv_phy_pre_pll_enable() local
1024 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), in vlv_phy_pre_pll_enable()
1027 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), in vlv_phy_pre_pll_enable()
1034 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); in vlv_phy_pre_pll_enable()
1035 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); in vlv_phy_pre_pll_enable()
1036 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); in vlv_phy_pre_pll_enable()
1048 int pipe = intel_crtc->pipe; in vlv_phy_pre_encoder_enable() local
1054 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); in vlv_phy_pre_encoder_enable()
1056 if (pipe) in vlv_phy_pre_encoder_enable()
1061 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); in vlv_phy_pre_encoder_enable()
1064 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); in vlv_phy_pre_encoder_enable()
1065 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); in vlv_phy_pre_encoder_enable()
1077 int pipe = intel_crtc->pipe; in vlv_phy_reset_lanes() local
1080 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); in vlv_phy_reset_lanes()
1081 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); in vlv_phy_reset_lanes()