404 	CSR_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER);  in epinit_locked()
419 	CSR_WRITE_2(sc, EP_COMMAND, RX_RESET);  in epinit_locked()
420 	CSR_WRITE_2(sc, EP_COMMAND, TX_RESET);  in epinit_locked()
429 	CSR_WRITE_2(sc, EP_COMMAND, ACK_INTR | 0xff);  in epinit_locked()
431 	CSR_WRITE_2(sc, EP_COMMAND, SET_RD_0_MASK | S_5_INTS);  in epinit_locked()
432 	CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK | S_5_INTS);  in epinit_locked()
435 		CSR_WRITE_2(sc, EP_COMMAND, SET_RX_FILTER | FIL_INDIVIDUAL |  in epinit_locked()
438 		CSR_WRITE_2(sc, EP_COMMAND, SET_RX_FILTER | FIL_INDIVIDUAL |  in epinit_locked()
445 		CSR_WRITE_2(sc, EP_COMMAND, TX_PLL_ENABLE);  in epinit_locked()
446 	CSR_WRITE_2(sc, EP_COMMAND, RX_ENABLE);  in epinit_locked()
447 	CSR_WRITE_2(sc, EP_COMMAND, TX_ENABLE);  in epinit_locked()
461 	CSR_WRITE_2(sc, EP_COMMAND, SET_RX_EARLY_THRESH | RX_INIT_EARLY_THRESH);  in epinit_locked()
462 	CSR_WRITE_2(sc, EP_COMMAND, SET_TX_START_THRESH | 16);  in epinit_locked()
501 		CSR_WRITE_2(sc, EP_COMMAND, TX_PLL_ENABLE);  in epstart_locked()
521 		CSR_WRITE_2(sc, EP_COMMAND, SET_TX_AVAIL_THRESH | (len + pad + 4));  in epstart_locked()
529 		CSR_WRITE_2(sc, EP_COMMAND,  in epstart_locked()
581 			CSR_WRITE_2(sc, EP_COMMAND, SET_TX_AVAIL_THRESH | 8);  in epstart_locked()
615 	CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK);	/* disable all Ints */  in ep_intr_locked()
622 		CSR_WRITE_2(sc, EP_COMMAND, ACK_INTR | (status & S_MASK));  in ep_intr_locked()
676 					CSR_WRITE_2(sc, EP_COMMAND, TX_RESET);  in ep_intr_locked()
690 					CSR_WRITE_2(sc, EP_COMMAND, TX_ENABLE);  in ep_intr_locked()
696 						CSR_WRITE_2(sc, EP_COMMAND,  in ep_intr_locked()
709 	CSR_WRITE_2(sc, EP_COMMAND, C_INTR_LATCH);	/* ACK int Latch */  in ep_intr_locked()
715 	CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK | S_5_INTS);  in ep_intr_locked()
828 		CSR_WRITE_2(sc, EP_COMMAND,  in epread()
832 	CSR_WRITE_2(sc, EP_COMMAND, RX_DISCARD_TOP_PACK);  in epread()
850 	CSR_WRITE_2(sc, EP_COMMAND, SET_RX_EARLY_THRESH | RX_INIT_EARLY_THRESH);  in epread()
854 	CSR_WRITE_2(sc, EP_COMMAND, RX_DISCARD_TOP_PACK);  in epread()
864 	CSR_WRITE_2(sc, EP_COMMAND, SET_RX_EARLY_THRESH | RX_INIT_EARLY_THRESH);  in epread()
874 	CSR_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER);  in ep_ifmedia_upd()
890 			CSR_WRITE_2(sc, EP_COMMAND, START_TRANSCEIVER);  in ep_ifmedia_upd()
1009 	CSR_WRITE_2(sc, EP_COMMAND, RX_DISABLE);  in epstop()
1010 	CSR_WRITE_2(sc, EP_COMMAND, RX_DISCARD_TOP_PACK);  in epstop()
1013 	CSR_WRITE_2(sc, EP_COMMAND, TX_DISABLE);  in epstop()
1014 	CSR_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER);  in epstop()
1017 	CSR_WRITE_2(sc, EP_COMMAND, RX_RESET);  in epstop()
1019 	CSR_WRITE_2(sc, EP_COMMAND, TX_RESET);  in epstop()
1022 	CSR_WRITE_2(sc, EP_COMMAND, C_INTR_LATCH);  in epstop()
1023 	CSR_WRITE_2(sc, EP_COMMAND, SET_RD_0_MASK);  in epstop()
1024 	CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK);  in epstop()
1025 	CSR_WRITE_2(sc, EP_COMMAND, SET_RX_FILTER);  in epstop()