45 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];  in set_render_target()  local
59 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 15));  in set_render_target()
60 	radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2);  in set_render_target()
61 	radeon_ring_write(ring, gpu_addr >> 8);  in set_render_target()
62 	radeon_ring_write(ring, pitch);  in set_render_target()
63 	radeon_ring_write(ring, slice);  in set_render_target()
64 	radeon_ring_write(ring, 0);  in set_render_target()
65 	radeon_ring_write(ring, cb_color_info);  in set_render_target()
66 	radeon_ring_write(ring, 0);  in set_render_target()
67 	radeon_ring_write(ring, (w - 1) | ((h - 1) << 16));  in set_render_target()
68 	radeon_ring_write(ring, 0);  in set_render_target()
69 	radeon_ring_write(ring, 0);  in set_render_target()
70 	radeon_ring_write(ring, 0);  in set_render_target()
71 	radeon_ring_write(ring, 0);  in set_render_target()
72 	radeon_ring_write(ring, 0);  in set_render_target()
73 	radeon_ring_write(ring, 0);  in set_render_target()
74 	radeon_ring_write(ring, 0);  in set_render_target()
75 	radeon_ring_write(ring, 0);  in set_render_target()
84 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];  in cp_set_surface_sync()  local
97 		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));  in cp_set_surface_sync()
98 		radeon_ring_write(ring, (0x85e8 - PACKET3_SET_CONFIG_REG_START) >> 2);  in cp_set_surface_sync()
99 		radeon_ring_write(ring, 0); /* CP_COHER_CNTL2 */  in cp_set_surface_sync()
101 	radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));  in cp_set_surface_sync()
102 	radeon_ring_write(ring, sync_type);  in cp_set_surface_sync()
103 	radeon_ring_write(ring, cp_coher_size);  in cp_set_surface_sync()
104 	radeon_ring_write(ring, mc_addr >> 8);  in cp_set_surface_sync()
105 	radeon_ring_write(ring, 10); /* poll interval */  in cp_set_surface_sync()
112 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];  in set_shaders()  local
117 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 3));  in set_shaders()
118 	radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2);  in set_shaders()
119 	radeon_ring_write(ring, gpu_addr >> 8);  in set_shaders()
120 	radeon_ring_write(ring, 2);  in set_shaders()
121 	radeon_ring_write(ring, 0);  in set_shaders()
125 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 4));  in set_shaders()
126 	radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2);  in set_shaders()
127 	radeon_ring_write(ring, gpu_addr >> 8);  in set_shaders()
128 	radeon_ring_write(ring, 1);  in set_shaders()
129 	radeon_ring_write(ring, 0);  in set_shaders()
130 	radeon_ring_write(ring, 2);  in set_shaders()
140 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];  in set_vtx_resource()  local
155 	radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 8));  in set_vtx_resource()
156 	radeon_ring_write(ring, 0x580);  in set_vtx_resource()
157 	radeon_ring_write(ring, gpu_addr & 0xffffffff);  in set_vtx_resource()
158 	radeon_ring_write(ring, 48 - 1); /* size */  in set_vtx_resource()
159 	radeon_ring_write(ring, sq_vtx_constant_word2);  in set_vtx_resource()
160 	radeon_ring_write(ring, sq_vtx_constant_word3);  in set_vtx_resource()
161 	radeon_ring_write(ring, 0);  in set_vtx_resource()
162 	radeon_ring_write(ring, 0);  in set_vtx_resource()
163 	radeon_ring_write(ring, 0);  in set_vtx_resource()
164 	radeon_ring_write(ring, S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_BUFFER));  in set_vtx_resource()
185 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];  in set_tex_resource()  local
209 	radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 8));  in set_tex_resource()
210 	radeon_ring_write(ring, 0);  in set_tex_resource()
211 	radeon_ring_write(ring, sq_tex_resource_word0);  in set_tex_resource()
212 	radeon_ring_write(ring, sq_tex_resource_word1);  in set_tex_resource()
213 	radeon_ring_write(ring, gpu_addr >> 8);  in set_tex_resource()
214 	radeon_ring_write(ring, gpu_addr >> 8);  in set_tex_resource()
215 	radeon_ring_write(ring, sq_tex_resource_word4);  in set_tex_resource()
216 	radeon_ring_write(ring, 0);  in set_tex_resource()
217 	radeon_ring_write(ring, 0);  in set_tex_resource()
218 	radeon_ring_write(ring, sq_tex_resource_word7);  in set_tex_resource()
226 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];  in set_scissors()  local
237 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));  in set_scissors()
238 	radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);  in set_scissors()
239 	radeon_ring_write(ring, (x1 << 0) | (y1 << 16));  in set_scissors()
240 	radeon_ring_write(ring, (x2 << 0) | (y2 << 16));  in set_scissors()
242 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));  in set_scissors()
243 	radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);  in set_scissors()
244 	radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31));  in set_scissors()
245 	radeon_ring_write(ring, (x2 << 0) | (y2 << 16));  in set_scissors()
247 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));  in set_scissors()
248 	radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);  in set_scissors()
249 	radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31));  in set_scissors()
250 	radeon_ring_write(ring, (x2 << 0) | (y2 << 16));  in set_scissors()
257 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];  in draw_auto()  local
258 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));  in draw_auto()
259 	radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2);  in draw_auto()
260 	radeon_ring_write(ring, DI_PT_RECTLIST);  in draw_auto()
262 	radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0));  in draw_auto()
263 	radeon_ring_write(ring,  in draw_auto()
269 	radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0));  in draw_auto()
270 	radeon_ring_write(ring, 1);  in draw_auto()
272 	radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));  in draw_auto()
273 	radeon_ring_write(ring, 3);  in draw_auto()
274 	radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX);  in draw_auto()
282 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];  in set_default_state()  local
296 	radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));  in set_default_state()
297 	radeon_ring_write(ring, 0);  in set_default_state()
554 		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));  in set_default_state()
555 		radeon_ring_write(ring, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2);  in set_default_state()
556 		radeon_ring_write(ring, 0);  in set_default_state()
559 		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));  in set_default_state()
560 		radeon_ring_write(ring, (SQ_LDS_RESOURCE_MGMT - PACKET3_SET_CONFIG_REG_START) >> 2);  in set_default_state()
561 		radeon_ring_write(ring, 0x10001000);  in set_default_state()
564 		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 11));  in set_default_state()
565 		radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2);  in set_default_state()
566 		radeon_ring_write(ring, sq_config);  in set_default_state()
567 		radeon_ring_write(ring, sq_gpr_resource_mgmt_1);  in set_default_state()
568 		radeon_ring_write(ring, sq_gpr_resource_mgmt_2);  in set_default_state()
569 		radeon_ring_write(ring, sq_gpr_resource_mgmt_3);  in set_default_state()
570 		radeon_ring_write(ring, 0);  in set_default_state()
571 		radeon_ring_write(ring, 0);  in set_default_state()
572 		radeon_ring_write(ring, sq_thread_resource_mgmt);  in set_default_state()
573 		radeon_ring_write(ring, sq_thread_resource_mgmt_2);  in set_default_state()
574 		radeon_ring_write(ring, sq_stack_resource_mgmt_1);  in set_default_state()
575 		radeon_ring_write(ring, sq_stack_resource_mgmt_2);  in set_default_state()
576 		radeon_ring_write(ring, sq_stack_resource_mgmt_3);  in set_default_state()
580 	radeon_ring_write(ring, 0xc0012800);  in set_default_state()
581 	radeon_ring_write(ring, 0x80000000);  in set_default_state()
582 	radeon_ring_write(ring, 0x80000000);  in set_default_state()
585 	radeon_ring_write(ring, 0xc0026f00);  in set_default_state()
586 	radeon_ring_write(ring, 0x00000000);  in set_default_state()
587 	radeon_ring_write(ring, 0x00000000);  in set_default_state()
588 	radeon_ring_write(ring, 0x00000000);  in set_default_state()
591 	radeon_ring_write(ring, 0xc0036e00);  in set_default_state()
592 	radeon_ring_write(ring, 0x00000000);  in set_default_state()
593 	radeon_ring_write(ring, 0x00000012);  in set_default_state()
594 	radeon_ring_write(ring, 0x00000000);  in set_default_state()
595 	radeon_ring_write(ring, 0x00000000);  in set_default_state()
598 	radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));  in set_default_state()
599 	radeon_ring_write(ring, 1);  in set_default_state()
604 	radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));  in set_default_state()
605 	radeon_ring_write(ring, gpu_addr & 0xFFFFFFFC);  in set_default_state()
606 	radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF);  in set_default_state()
607 	radeon_ring_write(ring, dwords);  in set_default_state()