Lines Matching refs:X86

102   case X86::MOV32rr:  in postRAConvertToLEA()
103 case X86::MOV64rr: { in postRAConvertToLEA()
107 TII->get(MI->getOpcode() == X86::MOV32rr ? X86::LEA32r in postRAConvertToLEA()
108 : X86::LEA64r)) in postRAConvertToLEA()
118 case X86::ADD64ri32: in postRAConvertToLEA()
119 case X86::ADD64ri8: in postRAConvertToLEA()
120 case X86::ADD64ri32_DB: in postRAConvertToLEA()
121 case X86::ADD64ri8_DB: in postRAConvertToLEA()
122 case X86::ADD32ri: in postRAConvertToLEA()
123 case X86::ADD32ri8: in postRAConvertToLEA()
124 case X86::ADD32ri_DB: in postRAConvertToLEA()
125 case X86::ADD32ri8_DB: in postRAConvertToLEA()
126 case X86::ADD16ri: in postRAConvertToLEA()
127 case X86::ADD16ri8: in postRAConvertToLEA()
128 case X86::ADD16ri_DB: in postRAConvertToLEA()
129 case X86::ADD16ri8_DB: in postRAConvertToLEA()
136 case X86::ADD16rr: in postRAConvertToLEA()
137 case X86::ADD16rr_DB: in postRAConvertToLEA()
234 MachineOperand &p = MI->getOperand(AddrOffset + X86::AddrBaseReg); in processInstruction()
235 if (p.isReg() && p.getReg() != X86::ESP) { in processInstruction()
238 MachineOperand &q = MI->getOperand(AddrOffset + X86::AddrIndexReg); in processInstruction()
239 if (q.isReg() && q.getReg() != X86::ESP) { in processInstruction()
268 if (opcode != X86::LEA16r && opcode != X86::LEA32r && opcode != X86::LEA64r && in processInstructionForSLM()
269 opcode != X86::LEA64_32r) in processInstructionForSLM()
284 case X86::LEA16r: in processInstructionForSLM()
285 addrr_opcode = X86::ADD16rr; in processInstructionForSLM()
286 addri_opcode = X86::ADD16ri; in processInstructionForSLM()
288 case X86::LEA32r: in processInstructionForSLM()
289 addrr_opcode = X86::ADD32rr; in processInstructionForSLM()
290 addri_opcode = X86::ADD32ri; in processInstructionForSLM()
292 case X86::LEA64_32r: in processInstructionForSLM()
293 case X86::LEA64r: in processInstructionForSLM()
294 addrr_opcode = X86::ADD64rr; in processInstructionForSLM()
295 addri_opcode = X86::ADD64ri32; in processInstructionForSLM()