Lines Matching refs:M3
182 bits<4> M3;
189 let Inst{15-12} = M3;
201 bits<4> M3;
206 let Inst{35-32} = M3;
345 bits<4> M3;
350 let Inst{15-12} = M3;
499 bits<4> M3;
505 let Inst{15-12} = M3;
611 bits<4> M3;
624 let Inst{15-12} = M3;
838 bits<4> M3;
843 let Inst{15-12} = M3;
857 bits<4> M3;
862 let Inst{15-12} = M3;
965 let M3 = 0;
1043 let M3 = type;
1303 let M3 = 0;
1335 let M3 = type;
1344 let M3 = type;
1365 let M3 = type;
1523 let M3 = 0;
1610 : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
1611 mnemonic#"\t$V1, $V2, $M3", []> {
1698 : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
1699 mnemonic#"\t$V1, $XBD2, $M3",
1701 imm32zx4:$M3)))]> {
1708 : InstVRV<opcode, (outs), (ins VR128:$V1, bdvaddr12only:$VBD2, index:$M3),
1709 mnemonic#"\t$V1, $VBD2, $M3", []> {
1717 : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2, index:$M3),
1718 mnemonic#"\t$V1, $XBD2, $M3",
1719 [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2, index:$M3)]> {
1796 let M3 = 0;
1872 let M3 = type;
1905 : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
1906 mnemonic#"\t$V1, $I2, $M3",
1908 imm:$I2, index:$M3)))]> {
1933 let M3 = type;
2018 (ins VR128:$V1src, bdvaddr12only:$VBD2, index:$M3),
2019 mnemonic#"\t$V1, $VBD2, $M3", []> {
2029 (ins tr2.op:$V1src, bdxaddr12only:$XBD2, index:$M3),
2030 mnemonic#"\t$V1, $XBD2, $M3",
2033 index:$M3)))]> {