52                                SmallVectorImpl<MCFixup> &Fixups,
55                              SmallVectorImpl<MCFixup> &Fixups,
58                                   SmallVectorImpl<MCFixup> &Fixups,
61                                 SmallVectorImpl<MCFixup> &Fixups,
64                              SmallVectorImpl<MCFixup> &Fixups,
67                             SmallVectorImpl<MCFixup> &Fixups,
70                              SmallVectorImpl<MCFixup> &Fixups,
73                               SmallVectorImpl<MCFixup> &Fixups,
76                               SmallVectorImpl<MCFixup> &Fixups,
79                               SmallVectorImpl<MCFixup> &Fixups,
82                              SmallVectorImpl<MCFixup> &Fixups,
85                               SmallVectorImpl<MCFixup> &Fixups,
88                                SmallVectorImpl<MCFixup> &Fixups,
94                              SmallVectorImpl<MCFixup> &Fixups,
100                                  SmallVectorImpl<MCFixup> &Fixups,
103                          SmallVectorImpl<MCFixup> &Fixups,  in encodeInstruction()  argument
113     uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);  in encodeInstruction()
154                     SmallVectorImpl<MCFixup> &Fixups,  in getDirectBrEncoding()  argument
157   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);  in getDirectBrEncoding()
160   Fixups.push_back(MCFixup::create(0, MO.getExpr(),  in getDirectBrEncoding()
166                                      SmallVectorImpl<MCFixup> &Fixups,  in getCondBrEncoding()  argument
169   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);  in getCondBrEncoding()
172   Fixups.push_back(MCFixup::create(0, MO.getExpr(),  in getCondBrEncoding()
179                        SmallVectorImpl<MCFixup> &Fixups,  in getAbsDirectBrEncoding()  argument
182   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);  in getAbsDirectBrEncoding()
185   Fixups.push_back(MCFixup::create(0, MO.getExpr(),  in getAbsDirectBrEncoding()
192                      SmallVectorImpl<MCFixup> &Fixups,  in getAbsCondBrEncoding()  argument
195   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);  in getAbsCondBrEncoding()
198   Fixups.push_back(MCFixup::create(0, MO.getExpr(),  in getAbsCondBrEncoding()
204                                        SmallVectorImpl<MCFixup> &Fixups,  in getImm16Encoding()  argument
207   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);  in getImm16Encoding()
210   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),  in getImm16Encoding()
216                                             SmallVectorImpl<MCFixup> &Fixups,  in getMemRIEncoding()  argument
221   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16;  in getMemRIEncoding()
225     return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits;  in getMemRIEncoding()
228   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),  in getMemRIEncoding()
235                                        SmallVectorImpl<MCFixup> &Fixups,  in getMemRIXEncoding()  argument
240   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14;  in getMemRIXEncoding()
244     return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits;  in getMemRIXEncoding()
247   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),  in getMemRIXEncoding()
254                                               SmallVectorImpl<MCFixup> &Fixups,  in getSPE8DisEncoding()  argument
260   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;  in getSPE8DisEncoding()
264   uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3;  in getSPE8DisEncoding()
270                                               SmallVectorImpl<MCFixup> &Fixups,  in getSPE4DisEncoding()  argument
276   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;  in getSPE4DisEncoding()
280   uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2;  in getSPE4DisEncoding()
286                                               SmallVectorImpl<MCFixup> &Fixups,  in getSPE2DisEncoding()  argument
292   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;  in getSPE2DisEncoding()
296   uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1;  in getSPE2DisEncoding()
302                                        SmallVectorImpl<MCFixup> &Fixups,  in getTLSRegEncoding()  argument
305   if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);  in getTLSRegEncoding()
310   Fixups.push_back(MCFixup::create(0, MO.getExpr(),  in getTLSRegEncoding()
318                                        SmallVectorImpl<MCFixup> &Fixups,  in getTLSCallEncoding()  argument
324   Fixups.push_back(MCFixup::create(0, MO.getExpr(),  in getTLSCallEncoding()
326   return getDirectBrEncoding(MI, OpNo, Fixups, STI);  in getTLSCallEncoding()
331                     SmallVectorImpl<MCFixup> &Fixups,  in get_crbitm_encoding()  argument
343                   SmallVectorImpl<MCFixup> &Fixups,  in getMachineOpValue()  argument