Lines Matching refs:Opc
370 unsigned Opc = Is64Bit ? AArch64::FMOVDi : AArch64::FMOVSi; in materializeFP() local
371 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm); in materializeFP()
403 unsigned Opc = Is64Bit ? AArch64::LDRDui : AArch64::LDRSui; in materializeFP() local
405 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in materializeFP()
491 unsigned Opc = Is64Bit ? AArch64::FMOVXDr : AArch64::FMOVWSr; in fastMaterializeFloatZero() local
492 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true); in fastMaterializeFloatZero()
1252 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit]; in emitAddSub_rr() local
1261 const MCInstrDesc &II = TII.get(Opc); in emitAddSub_rr()
1294 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit]; in emitAddSub_ri() local
1306 const MCInstrDesc &II = TII.get(Opc); in emitAddSub_ri()
1333 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit]; in emitAddSub_rs() local
1342 const MCInstrDesc &II = TII.get(Opc); in emitAddSub_rs()
1370 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit]; in emitAddSub_rx() local
1382 const MCInstrDesc &II = TII.get(Opc); in emitAddSub_rx()
1443 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDri : AArch64::FCMPSri; in emitFCmp() local
1444 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)) in emitFCmp()
1454 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDrr : AArch64::FCMPSrr; in emitFCmp() local
1455 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)) in emitFCmp()
1603 unsigned Opc; in emitLogicalOp_ri() local
1613 Opc = OpcTable[Idx][0]; in emitLogicalOp_ri()
1619 Opc = OpcTable[ISDOpc - ISD::AND][1]; in emitLogicalOp_ri()
1629 fastEmitInst_ri(Opc, RC, LHSReg, LHSIsKill, in emitLogicalOp_ri()
1650 unsigned Opc; in emitLogicalOp_rs() local
1658 Opc = OpcTable[ISDOpc - ISD::AND][0]; in emitLogicalOp_rs()
1662 Opc = OpcTable[ISDOpc - ISD::AND][1]; in emitLogicalOp_rs()
1667 fastEmitInst_rri(Opc, RC, LHSReg, LHSIsKill, RHSReg, RHSIsKill, in emitLogicalOp_rs()
1748 unsigned Opc; in emitLoad() local
1763 Opc = GPOpcTable[WantZExt][2 * Idx + IsRet64Bit][0]; in emitLoad()
1768 Opc = GPOpcTable[WantZExt][2 * Idx + IsRet64Bit][1]; in emitLoad()
1773 Opc = GPOpcTable[WantZExt][2 * Idx + IsRet64Bit][2]; in emitLoad()
1778 Opc = GPOpcTable[WantZExt][2 * Idx + IsRet64Bit][3]; in emitLoad()
1782 Opc = FPOpcTable[Idx][0]; in emitLoad()
1786 Opc = FPOpcTable[Idx][1]; in emitLoad()
1794 TII.get(Opc), ResultReg); in emitLoad()
2000 unsigned Opc; in emitStore() local
2012 case MVT::i8: Opc = OpcTable[Idx][0]; break; in emitStore()
2013 case MVT::i16: Opc = OpcTable[Idx][1]; break; in emitStore()
2014 case MVT::i32: Opc = OpcTable[Idx][2]; break; in emitStore()
2015 case MVT::i64: Opc = OpcTable[Idx][3]; break; in emitStore()
2016 case MVT::f32: Opc = OpcTable[Idx][4]; break; in emitStore()
2017 case MVT::f64: Opc = OpcTable[Idx][5]; break; in emitStore()
2027 const MCInstrDesc &II = TII.get(Opc); in emitStore()
2214 unsigned Opc = OpcTable[IsBitTest][IsCmpNE][Is64Bit]; in emitCompareAndBranch() local
2215 const MCInstrDesc &II = TII.get(Opc); in emitCompareAndBranch()
2232 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)) in emitCompareAndBranch()
2543 unsigned Opc = 0; in optimizeSelect() local
2549 Opc = AArch64::ORRWrr; in optimizeSelect()
2554 Opc = AArch64::BICWrr; in optimizeSelect()
2560 Opc = AArch64::ORRWrr; in optimizeSelect()
2566 Opc = AArch64::ANDWrr; in optimizeSelect()
2570 if (!Opc) in optimizeSelect()
2587 unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg, in optimizeSelect()
2599 unsigned Opc; in selectSelect() local
2608 Opc = AArch64::CSELWr; in selectSelect()
2612 Opc = AArch64::CSELXr; in selectSelect()
2616 Opc = AArch64::FCSELSrrr; in selectSelect()
2620 Opc = AArch64::FCSELDrrr; in selectSelect()
2713 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect()
2717 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect()
2769 unsigned Opc; in selectFPToInt() local
2772 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr; in selectFPToInt()
2774 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr; in selectFPToInt()
2777 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr; in selectFPToInt()
2779 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr; in selectFPToInt()
2783 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in selectFPToInt()
2812 unsigned Opc; in selectIntToFP() local
2815 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri; in selectIntToFP()
2817 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri; in selectIntToFP()
2820 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri; in selectIntToFP()
2822 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri; in selectIntToFP()
2825 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg, in selectIntToFP()
3478 unsigned Opc; in fastLowerIntrinsicCall() local
3483 Opc = AArch64::FABSSr; in fastLowerIntrinsicCall()
3486 Opc = AArch64::FABSDr; in fastLowerIntrinsicCall()
3494 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastLowerIntrinsicCall()
3872 unsigned Opc, ZReg; in emitMul_rr() local
3879 Opc = AArch64::MADDWrrr; ZReg = AArch64::WZR; break; in emitMul_rr()
3881 Opc = AArch64::MADDXrrr; ZReg = AArch64::XZR; break; in emitMul_rr()
3886 return fastEmitInst_rrr(Opc, RC, Op0, Op0IsKill, Op1, Op1IsKill, in emitMul_rr()
3912 unsigned Opc = 0; in emitLSL_rr() local
3917 case MVT::i8: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xff; break; in emitLSL_rr()
3918 case MVT::i16: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xffff; break; in emitLSL_rr()
3919 case MVT::i32: Opc = AArch64::LSLVWr; break; in emitLSL_rr()
3920 case MVT::i64: Opc = AArch64::LSLVXr; break; in emitLSL_rr()
3929 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, in emitLSL_rr()
4002 unsigned Opc = OpcTable[IsZExt][Is64Bit]; in emitLSL_ri() local
4013 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS); in emitLSL_ri()
4018 unsigned Opc = 0; in emitLSR_rr() local
4023 case MVT::i8: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xff; break; in emitLSR_rr()
4024 case MVT::i16: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xffff; break; in emitLSR_rr()
4025 case MVT::i32: Opc = AArch64::LSRVWr; break; in emitLSR_rr()
4026 case MVT::i64: Opc = AArch64::LSRVXr; break; in emitLSR_rr()
4036 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, in emitLSR_rr()
4123 unsigned Opc = OpcTable[IsZExt][Is64Bit]; in emitLSR_ri() local
4134 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS); in emitLSR_ri()
4139 unsigned Opc = 0; in emitASR_rr() local
4144 case MVT::i8: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xff; break; in emitASR_rr()
4145 case MVT::i16: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xffff; break; in emitASR_rr()
4146 case MVT::i32: Opc = AArch64::ASRVWr; break; in emitASR_rr()
4147 case MVT::i64: Opc = AArch64::ASRVXr; break; in emitASR_rr()
4157 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, in emitASR_rr()
4232 unsigned Opc = OpcTable[IsZExt][Is64Bit]; in emitASR_ri() local
4243 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS); in emitASR_ri()
4260 unsigned Opc; in emitIntExt() local
4270 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri; in emitIntExt()
4272 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri; in emitIntExt()
4277 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri; in emitIntExt()
4279 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri; in emitIntExt()
4284 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri; in emitIntExt()
4304 return fastEmitInst_rii(Opc, RC, SrcReg, /*TODO:IsKill=*/false, 0, Imm); in emitIntExt()
4678 unsigned Opc; in selectBitCast() local
4680 Opc = AArch64::FMOVWSr; in selectBitCast()
4682 Opc = AArch64::FMOVXDr; in selectBitCast()
4684 Opc = AArch64::FMOVSWr; in selectBitCast()
4686 Opc = AArch64::FMOVDXr; in selectBitCast()
4702 unsigned ResultReg = fastEmitInst_r(Opc, RC, Op0Reg, Op0IsKill); in selectBitCast()