Lines Matching refs:op0
1060 sparc_emit_set_const32 (rtx op0, rtx op1) in sparc_emit_set_const32() argument
1062 enum machine_mode mode = GET_MODE (op0); in sparc_emit_set_const32()
1066 temp = op0; in sparc_emit_set_const32()
1083 op0, in sparc_emit_set_const32()
1093 op0, gen_rtx_LO_SUM (mode, temp, op1))); in sparc_emit_set_const32()
1105 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp) in sparc_emit_set_symbolic_const64() argument
1136 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1))); in sparc_emit_set_symbolic_const64()
1154 temp1 = op0; in sparc_emit_set_symbolic_const64()
1155 temp2 = op0; in sparc_emit_set_symbolic_const64()
1169 emit_insn (gen_setl44 (op0, temp3, op1)); in sparc_emit_set_symbolic_const64()
1192 if (rtx_equal_p (temp, op0)) in sparc_emit_set_symbolic_const64()
1197 temp1 = op0; in sparc_emit_set_symbolic_const64()
1199 temp3 = op0; in sparc_emit_set_symbolic_const64()
1200 temp4 = op0; in sparc_emit_set_symbolic_const64()
1201 temp5 = op0; in sparc_emit_set_symbolic_const64()
1219 emit_insn (gen_setlo (op0, temp5, op1)); in sparc_emit_set_symbolic_const64()
1238 temp2 = op0; in sparc_emit_set_symbolic_const64()
1248 emit_insn (gen_embmedany_losum (op0, temp2, op1)); in sparc_emit_set_symbolic_const64()
1264 if (rtx_equal_p (temp, op0)) in sparc_emit_set_symbolic_const64()
1269 temp1 = op0; in sparc_emit_set_symbolic_const64()
1271 temp3 = op0; in sparc_emit_set_symbolic_const64()
1272 temp4 = op0; in sparc_emit_set_symbolic_const64()
1273 temp5 = op0; in sparc_emit_set_symbolic_const64()
1291 emit_insn (gen_embmedany_textlo (op0, temp5, op1)); in sparc_emit_set_symbolic_const64()
1302 sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED, rtx op1 ATTRIBUTE_UNUSED) in sparc_emit_set_const64()
1356 sparc_emit_set_const64_quick1 (rtx op0, rtx temp, in sparc_emit_set_const64_quick1() argument
1369 emit_insn (gen_rtx_SET (VOIDmode, op0, in sparc_emit_set_const64_quick1()
1379 emit_insn (gen_rtx_SET (VOIDmode, op0, in sparc_emit_set_const64_quick1()
1384 emit_insn (gen_rtx_SET (VOIDmode, op0, in sparc_emit_set_const64_quick1()
1396 sparc_emit_set_const64_quick2 (rtx op0, rtx temp, in sparc_emit_set_const64_quick2() argument
1401 rtx temp2 = op0; in sparc_emit_set_const64_quick2()
1407 emit_insn (gen_rtx_SET (VOIDmode, op0, in sparc_emit_set_const64_quick2()
1419 emit_insn (gen_rtx_SET (VOIDmode, op0, in sparc_emit_set_const64_quick2()
1426 emit_insn (gen_rtx_SET (VOIDmode, op0, in sparc_emit_set_const64_quick2()
1427 gen_safe_OR64 (op0, low_immediate))); in sparc_emit_set_const64_quick2()
1436 sparc_emit_set_const64_longway (rtx op0, rtx temp, in sparc_emit_set_const64_longway() argument
1443 sub_temp = op0; in sparc_emit_set_const64_longway()
1478 emit_insn (gen_rtx_SET (VOIDmode, op0, in sparc_emit_set_const64_longway()
1483 emit_insn (gen_rtx_SET (VOIDmode, op0, in sparc_emit_set_const64_longway()
1499 emit_insn (gen_rtx_SET (VOIDmode, op0, in sparc_emit_set_const64_longway()
1502 emit_insn (gen_rtx_SET (VOIDmode, op0, in sparc_emit_set_const64_longway()
1503 gen_rtx_IOR (DImode, op0, low1))); in sparc_emit_set_const64_longway()
1504 sub_temp = op0; in sparc_emit_set_const64_longway()
1513 emit_insn (gen_rtx_SET (VOIDmode, op0, in sparc_emit_set_const64_longway()
1516 emit_insn (gen_rtx_SET (VOIDmode, op0, in sparc_emit_set_const64_longway()
1517 gen_rtx_IOR (DImode, op0, low2))); in sparc_emit_set_const64_longway()
1518 sub_temp = op0; in sparc_emit_set_const64_longway()
1525 emit_insn (gen_rtx_SET (VOIDmode, op0, in sparc_emit_set_const64_longway()
1529 emit_insn (gen_rtx_SET (VOIDmode, op0, in sparc_emit_set_const64_longway()
1530 gen_rtx_IOR (DImode, op0, low3))); in sparc_emit_set_const64_longway()
1659 sparc_emit_set_const64 (rtx op0, rtx op1) in sparc_emit_set_const64() argument
1668 && (GET_CODE (op0) == SUBREG in sparc_emit_set_const64()
1669 || (REG_P (op0) && ! SPARC_FP_REG_P (REGNO (op0))))); in sparc_emit_set_const64()
1672 temp = op0; in sparc_emit_set_const64()
1676 sparc_emit_set_symbolic_const64 (op0, op1, temp); in sparc_emit_set_const64()
1729 op0, in sparc_emit_set_const64()
1735 op0, in sparc_emit_set_const64()
1762 op0, in sparc_emit_set_const64()
1767 op0, in sparc_emit_set_const64()
1781 sparc_emit_set_const64_quick1 (op0, temp, low_bits, in sparc_emit_set_const64()
1794 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32); in sparc_emit_set_const64()
1834 emit_insn (gen_rtx_SET (VOIDmode, op0, in sparc_emit_set_const64()
1840 op0, in sparc_emit_set_const64()
1865 sparc_emit_set_const64_quick2 (op0, temp, in sparc_emit_set_const64()
1879 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32); in sparc_emit_set_const64()
1888 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits); in sparc_emit_set_const64()
2051 rtx op0 = sparc_compare_op0; in gen_v9_scc() local
2059 && rtx_equal_p (op0, operands[0])) in gen_v9_scc()
2064 op0, const0_rtx), in gen_v9_scc()
2070 if (reg_overlap_mentioned_p (operands[0], op0)) in gen_v9_scc()
2074 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0)); in gen_v9_scc()
2075 emit_move_insn (op0, sparc_compare_op0); in gen_v9_scc()
2079 if (GET_MODE (op0) != DImode) in gen_v9_scc()
2082 convert_move (temp, op0, 0); in gen_v9_scc()
2085 temp = op0; in gen_v9_scc()
2124 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label) in emit_v9_brxx_insn() argument
2130 gen_rtx_fmt_ee (code, GET_MODE (op0), in emit_v9_brxx_insn()
2131 op0, const0_rtx), in emit_v9_brxx_insn()
7465 rtx op0 = XEXP (SET_SRC (pat), 0); in set_extends() local
7469 if (GET_CODE (op0) != REG) in set_extends()
7471 if (sparc_check_64 (op0, insn) == 1) in set_extends()
7478 rtx op0 = XEXP (SET_SRC (pat), 0); in set_extends() local
7480 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0) in set_extends()