You are now in the directory for the port "cad/verilator".
The package name of this port is "verilator-5.026_1".
The license for this port is "%%LICENSE%%".
This is the one-line description for this port:
Synthesizable Verilog to C++ compiler
Please read the "description file" for a longer description.
If needed, you may contact the maintainer of this port or the port mailing-list.
This port requires package(s) "autoconf-2.73 autoconf-switch-20220527 bash-5.3.15 bison-3.8.2_1,1 gettext-runtime-0.23.1 gmake-4.4.1 help2man-1.49.3 indexinfo-0.3.1_1 libffi-3.5.1 libiconv-1.18 liblz4-1.10.0_1,1 libtextstyle-0.23.1 m4-1.4.21,1 mpdecimal-4.0.0 ncurses-6.5 p5-Locale-gettext-1.07 p5-Locale-libintl-1.37 p5-Text-Unidecode-1.30 p5-Unicode-EastAsianWidth-12.0 perl5-5.40.4 python312-3.12.12_1 readline-8.2.10 riscv32-unknown-elf-binutils-2.44_1 systemc-3.0.1 texinfo-7.1_2,1 zstd-1.5.6_1" to build.
This port requires package(s) "gettext-runtime-0.23.1 gmake-4.4.1 indexinfo-0.3.1_1 libffi-3.5.1 libiconv-1.18 liblz4-1.10.0_1,1 mpdecimal-4.0.0 ncurses-6.5 p5-Locale-libintl-1.37 p5-Text-Unidecode-1.30 p5-Unicode-EastAsianWidth-12.0 perl5-5.40.4 python312-3.12.12_1 readline-8.2.10 riscv32-unknown-elf-binutils-2.44_1 systemc-3.0.1 texinfo-7.1_2,1 zstd-1.5.6_1" to run.
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