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cad/chipvault

Project organizer for VHDL and Verilog RTL hardware designs

Flavor Version Run OSVersion Arch License Restricted Build Fetch Test Scan
200607 652 4.1 i386 No License 0 warn warn untested untested Reset Port

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Events

Machine Phase Type Time Message
m4132 fetch info 2026-11-04 02:23:55.605513 Fetch Started
m4132 fetch warn 2026-11-04 02:24:01.787229 LICENSE is not set.
m4132 fetch warn 2026-11-04 02:24:02.098988 Fetch complete.
m4132 build info 2026-11-04 20:13:11.275401 Build Started
m4132 build warn 2026-11-04 20:13:15.484535 MASTER_SITES contains non-HTTPS URLs: http://chipvault.sourceforge.net/
m4132 build warn 2026-11-04 20:13:15.497977 LICENSE is not set.
m4132 build warn 2026-11-04 20:13:15.780865 Build complete.

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