MidnightBSD Magus

cad/iverilog

Verilog simulation and synthesis tool

Flavor Version Run OSVersion Arch License Restricted Build Fetch Test Scan
12.0_1 648 4.1 amd64 gpl2 0 pass pass pass warn Reset Port

License Permissions: dist-mirror dist-sell pkg-mirror pkg-sell auto-accept

Events

Machine Phase Type Time Message
m4164 test info 2026-09-26 02:56:00.551599 Test Started
m4164 test pass 2026-09-26 02:57:15.31235 Test complete.
m4164 scan info 2026-09-22 16:52:08.756864 Scan Started
m4164 scan info 2026-09-22 16:52:24.946058 Virus scan passed.
m4164 scan info 2026-09-22 16:52:24.976271 YARA scan passed.
m4164 scan warn 2026-09-22 16:52:28.146777 USE_GITHUB resolves to non-immutable-looking GH_TAGNAME: v12_0
m4164 scan warn 2026-09-22 16:52:28.174321 Scan complete.
m4164 fetch info 2026-09-20 18:57:07.548074 Fetch Started
m4164 fetch pass 2026-09-20 18:57:12.0342 Fetch complete.
m4164b build info 2026-09-21 13:44:02.418779 Build Started
m4164b build pass 2026-09-21 13:45:49.575148 Build complete.

scan Log

== ClamAV package scan ==
/mnt/magus/packages/648/iverilog-12.0_1.mport: OK

== YARA port-file scan ==
No YARA matches.

== Source integrity scan ==
Compared cad/iverilog between 60b86f7714364c0e1a4411b214735dc6df5c236a and c8f81094d01e568b4d50d0898787ca34889bbdb7.
Changed files:
  cad/iverilog/Makefile
  cad/iverilog/distinfo
  cad/iverilog/pkg-descr
  cad/iverilog/pkg-plist
Warnings:
  SourceIntegrityMutableGithubTag: USE_GITHUB resolves to non-immutable-looking GH_TAGNAME: v12_0

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LLM Analysis