MidnightBSD Magus

cad/verilator

Synthesizable Verilog to C++ compiler

Flavor Version Run OSVersion Arch License Restricted Build Fetch Test Scan
5.026_1 646 4.1 amd64 gpl3 0 warn pass untested warn Reset Port

License Permissions: dist-mirror dist-sell pkg-mirror pkg-sell auto-accept

Events

Machine Phase Type Time Message
m4164b fetch info 2026-08-07 19:08:16.548453 Fetch Started
m4164b fetch pass 2026-08-07 19:08:26.452989 Fetch complete.
m4164b build info 2026-08-10 20:50:32.730075 Build Started
m4164b build warn 2026-08-10 21:16:15.501594 fake-qa reported: you might not need LIB_DEPENDS on libsystemc.so
m4164b build warn 2026-08-10 21:16:15.942215 Build complete.
m4164b scan info 2026-08-15 14:49:44.018092 Scan Started
m4164b scan info 2026-08-15 14:50:02.687603 Virus scan passed.
m4164b scan warn 2026-08-15 14:50:02.721572 YARA found suspicious port shell content.
m4164b scan warn 2026-08-15 14:50:07.123132 USE_GITHUB resolves to non-immutable-looking GH_TAGNAME: v5.026
m4164b scan warn 2026-08-15 14:50:07.152745 Scan complete.

scan Log

== ClamAV package scan ==
/mnt/magus/packages/646/verilator-5.026_1.mport: OK

== YARA port-file scan ==
/usr/mports/cad/verilator/Makefile(1): error: syntax error, unexpected identifier
/usr/mports/cad/verilator/Makefile(13): error: unterminated regular expression

== Source integrity scan ==
Compared cad/verilator between df708ba31ff0dac565750f8e8ea7d2b702ae7963 and 028f5c35b717a0aa8460c3c4b96c7495cad12dee.
Changed files:
  cad/verilator/Makefile
Warnings:
  SourceIntegrityMutableGithubTag: USE_GITHUB resolves to non-immutable-looking GH_TAGNAME: v5.026

Links

Depends On

Depend Of

Categories

CVEs

  • Loading CVE information...

LLM Analysis