MidnightBSD Magus

cad/gplcver

Verilog HDL simulator

Flavor Version Run OSVersion Arch License Restricted Build Fetch Test Scan
2.12.a 646 4.1 amd64 gpl2 0 warn pass untested warn Reset Port

License Permissions: dist-mirror dist-sell pkg-mirror pkg-sell auto-accept

Events

Machine Phase Type Time Message
m4164 fetch info 2026-08-07 19:02:49.508413 Fetch Started
m4164 fetch pass 2026-08-07 19:02:50.815276 Fetch complete.
m4164b build info 2026-08-08 23:07:48.124872 Build Started
m4164b build warn 2026-08-08 23:07:56.776178 MASTER_SITES contains non-HTTPS URLs: http://downloads.sourceforge.net/project/gplcver/gplcver/2.12a/, http://cfhcable.dl.sourceforge.net/project/gplcver/gplcver/2.12a/, http://cytranet.dl.sourceforge.net/project/gplcver/gplcver/2.12a/, http://deac-ams.dl.sourceforge.net/project/gplcver/gplcver/2.12a/, http://deac-fra.dl.sourceforge.net/project/gplcver/gplcver/2.12a/ and 19 more
m4164b build warn 2026-08-08 23:07:57.13236 Build complete.
m4164b scan info 2026-08-15 14:33:36.98255 Scan Started
m4164b scan info 2026-08-15 14:33:52.631701 Virus scan passed.
m4164b scan warn 2026-08-15 14:33:52.665518 YARA found suspicious port shell content.
m4164b scan info 2026-08-15 14:33:52.925818 Source integrity scan passed.
m4164b scan warn 2026-08-15 14:33:52.95363 Scan complete.

scan Log

== ClamAV package scan ==
/mnt/magus/packages/646/gplcver-2.12.a.mport: OK

== YARA port-file scan ==
/usr/mports/cad/gplcver/Makefile(1): error: syntax error, unexpected identifier
/usr/mports/cad/gplcver/Makefile(16): error: unterminated regular expression

== Source integrity scan ==
Compared cad/gplcver between 70edcb85ec50f0f11f83cbb7af2b1a051439152a and 177ae033a7ad8459e5e20760b547a2b46a0c1e79.
Changed files:
  cad/gplcver/Makefile
No source integrity warnings.

Links

Depends On

Depend Of

Nothing

Categories

CVEs

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LLM Analysis