MidnightBSD Magus

cad/iverilog

Verilog simulation and synthesis tool

Flavor Version Run OSVersion Arch License Restricted Build Fetch Test Scan
12.0_1 644 4.1 amd64 gpl2 0 pass pass pass warn Reset Port

License Permissions: dist-mirror dist-sell pkg-mirror pkg-sell auto-accept

Events

Machine Phase Type Time Message
m4164b fetch info 2026-07-25 07:38:39.015998 Fetch Started
m4164b fetch pass 2026-07-25 07:38:46.800539 Fetch complete.
m4164b build info 2026-07-27 09:08:18.992037 Build Started
m4164b build pass 2026-07-27 09:10:15.298823 Build complete.
m4164b scan info 2026-07-28 03:48:23.407588 Scan Started
m4164b scan info 2026-07-28 03:48:42.122554 Virus scan passed.
m4164b scan info 2026-07-28 03:48:42.164822 YARA scan passed.
m4164b scan warn 2026-07-28 03:48:47.871128 USE_GITHUB resolves to non-immutable-looking GH_TAGNAME: v12_0
m4164b scan warn 2026-07-28 03:48:47.898817 Scan complete.
m4164b test info 2026-07-28 22:26:51.33601 Test Started
m4164b test pass 2026-07-28 22:28:36.214445 Test complete.

scan Log

== ClamAV package scan ==
/mnt/magus/packages/644/iverilog-12.0_1.mport: OK

== YARA port-file scan ==
No YARA matches.

== Source integrity scan ==
Compared cad/iverilog between 60b86f7714364c0e1a4411b214735dc6df5c236a and c8f81094d01e568b4d50d0898787ca34889bbdb7.
Changed files:
  cad/iverilog/Makefile
  cad/iverilog/distinfo
  cad/iverilog/pkg-descr
  cad/iverilog/pkg-plist
Warnings:
  SourceIntegrityMutableGithubTag: USE_GITHUB resolves to non-immutable-looking GH_TAGNAME: v12_0

Links

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LLM Analysis