cad/iverilog
Verilog simulation and synthesis tool
| Flavor | Version | Run | OSVersion | Arch | License | Restricted | Build | Fetch | Test | Scan | |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 12.0_1 | 644 | 4.1 | amd64 | gpl2 | 0 | untested | pass | untested | untested |
License Permissions: dist-mirror dist-sell pkg-mirror pkg-sell auto-accept
Events
| Machine | Phase | Type | Time | Message |
|---|---|---|---|---|
| m4164b | fetch | info | 2026-07-25 07:38:39.015998 | Fetch Started |
| m4164b | fetch | pass | 2026-07-25 07:38:46.800539 | Fetch complete. |
Links
Depends On
- devel/autoconf (build)
- devel/bison (build)
- devel/gmake (build)
- devel/gperf (build)
- devel/readline (build)
- devel/readline (lib)
- devel/readline (run)
Depend Of
Categories
CVEs
- Loading CVE information...
MidnightBSD Magus